Blame - llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp - toolchain/llvm-project

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Jia Liu	b22310f	2012-02-18 12:03:15 +0000	[diff] [blame]	1	//===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	2	//
				3	// The LLVM Compiler Infrastructure
				4	//
				5	// This file is distributed under the University of Illinois Open Source
				6	// License. See LICENSE.TXT for details.
				7	//
				8	//===----------------------------------------------------------------------===//
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	9
				10	#define DEBUG_TYPE "arm-disassembler"
				11
Chandler Carruth	ed0881b	2012-12-03 16:50:05 +0000	[diff] [blame]	12	#include "llvm/MC/MCDisassembler.h"
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	13	#include "MCTargetDesc/ARMAddressingModes.h"
				14	#include "MCTargetDesc/ARMBaseInfo.h"
Chandler Carruth	ed0881b	2012-12-03 16:50:05 +0000	[diff] [blame]	15	#include "MCTargetDesc/ARMMCExpr.h"
Chandler Carruth	ed0881b	2012-12-03 16:50:05 +0000	[diff] [blame]	16	#include "llvm/MC/MCContext.h"
				17	#include "llvm/MC/MCExpr.h"
				18	#include "llvm/MC/MCFixedLenDisassembler.h"
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	19	#include "llvm/MC/MCInst.h"
Benjamin Kramer	48b5bbf	2011-11-11 12:39:41 +0000	[diff] [blame]	20	#include "llvm/MC/MCInstrDesc.h"
Dylan Noblesmith	7a3973d	2012-04-03 15:48:14 +0000	[diff] [blame]	21	#include "llvm/MC/MCSubtargetInfo.h"
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	22	#include "llvm/Support/Debug.h"
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	23	#include "llvm/Support/ErrorHandling.h"
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	24	#include "llvm/Support/LEB128.h"
Chandler Carruth	ed0881b	2012-12-03 16:50:05 +0000	[diff] [blame]	25	#include "llvm/Support/MemoryObject.h"
Evan Cheng	2bb4035	2011-08-24 18:08:43 +0000	[diff] [blame]	26	#include "llvm/Support/TargetRegistry.h"
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	27	#include "llvm/Support/raw_ostream.h"
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	28	#include <vector>
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	29
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	30	using namespace llvm;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	31
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	32	typedef MCDisassembler::DecodeStatus DecodeStatus;
				33
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	34	namespace {
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	35	// Handles the condition code status of instructions in IT blocks
				36	class ITStatus
				37	{
				38	public:
				39	// Returns the condition code for instruction in IT block
				40	unsigned getITCC() {
				41	unsigned CC = ARMCC::AL;
				42	if (instrInITBlock())
				43	CC = ITStates.back();
				44	return CC;
				45	}
				46
				47	// Advances the IT block state to the next T or E
				48	void advanceITState() {
				49	ITStates.pop_back();
				50	}
				51
				52	// Returns true if the current instruction is in an IT block
				53	bool instrInITBlock() {
				54	return !ITStates.empty();
				55	}
				56
				57	// Returns true if current instruction is the last instruction in an IT block
				58	bool instrLastInITBlock() {
				59	return ITStates.size() == 1;
				60	}
				61
				62	// Called when decoding an IT instruction. Sets the IT state for the following
				63	// instructions that for the IT block. Firstcond and Mask correspond to the
				64	// fields in the IT instruction encoding.
				65	void setITState(char Firstcond, char Mask) {
				66	// (3 - the number of trailing zeros) is the number of then / else.
Richard Barton	f435b09	2012-04-27 08:42:59 +0000	[diff] [blame]	67	unsigned CondBit0 = Firstcond & 1;
Michael J. Spencer	df1ecbd7	2013-05-24 22:23:49 +0000	[diff] [blame]	68	unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	69	unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
				70	assert(NumTZ <= 3 && "Invalid IT mask!");
				71	// push condition codes onto the stack the correct order for the pops
				72	for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
				73	bool T = ((Mask >> Pos) & 1) == CondBit0;
				74	if (T)
				75	ITStates.push_back(CCBits);
				76	else
				77	ITStates.push_back(CCBits ^ 1);
				78	}
				79	ITStates.push_back(CCBits);
				80	}
				81
				82	private:
				83	std::vector<unsigned char> ITStates;
				84	};
				85	}
				86
				87	namespace {
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	88	/// ARMDisassembler - ARM disassembler for all ARM platforms.
				89	class ARMDisassembler : public MCDisassembler {
				90	public:
				91	/// Constructor - Initializes the disassembler.
				92	///
James Molloy	4c493e8	2011-09-07 17:24:38 +0000	[diff] [blame]	93	ARMDisassembler(const MCSubtargetInfo &STI) :
				94	MCDisassembler(STI) {
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	95	}
				96
				97	~ARMDisassembler() {
				98	}
				99
				100	/// getInstruction - See MCDisassembler.
				101	DecodeStatus getInstruction(MCInst &instr,
				102	uint64_t &size,
Derek Schuff	56b662c	2012-02-29 01:09:06 +0000	[diff] [blame]	103	const MemoryObject &region,
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	104	uint64_t address,
Owen Anderson	a0c3b97	2011-09-15 23:38:46 +0000	[diff] [blame]	105	raw_ostream &vStream,
				106	raw_ostream &cStream) const;
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	107	};
				108
				109	/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
				110	class ThumbDisassembler : public MCDisassembler {
				111	public:
				112	/// Constructor - Initializes the disassembler.
				113	///
James Molloy	4c493e8	2011-09-07 17:24:38 +0000	[diff] [blame]	114	ThumbDisassembler(const MCSubtargetInfo &STI) :
				115	MCDisassembler(STI) {
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	116	}
				117
				118	~ThumbDisassembler() {
				119	}
				120
				121	/// getInstruction - See MCDisassembler.
				122	DecodeStatus getInstruction(MCInst &instr,
				123	uint64_t &size,
Derek Schuff	56b662c	2012-02-29 01:09:06 +0000	[diff] [blame]	124	const MemoryObject &region,
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	125	uint64_t address,
Owen Anderson	a0c3b97	2011-09-15 23:38:46 +0000	[diff] [blame]	126	raw_ostream &vStream,
				127	raw_ostream &cStream) const;
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	128
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	129	private:
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	130	mutable ITStatus ITBlock;
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	131	DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	132	void UpdateThumbVFPPredicate(MCInst&) const;
				133	};
				134	}
				135
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	136	static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	137	switch (In) {
				138	case MCDisassembler::Success:
				139	// Out stays the same.
				140	return true;
				141	case MCDisassembler::SoftFail:
				142	Out = In;
				143	return true;
				144	case MCDisassembler::Fail:
				145	Out = In;
				146	return false;
				147	}
David Blaikie	46a9f01	2012-01-20 21:51:11 +0000	[diff] [blame]	148	llvm_unreachable("Invalid DecodeStatus!");
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	149	}
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	150
James Molloy	8067df9	2011-09-07 19:42:28 +0000	[diff] [blame]	151
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	152	// Forward declare these because the autogenerated code will reference them.
				153	// Definitions are further down.
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	154	static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	155	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	156	static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	157	unsigned RegNo, uint64_t Address,
				158	const void *Decoder);
Mihai Popa	dc1764c5	2013-05-13 14:10:04 +0000	[diff] [blame]	159	static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
				160	unsigned RegNo, uint64_t Address,
				161	const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	162	static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	163	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	164	static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	165	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	166	static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	167	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	168	static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
				169	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	170	static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	171	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	172	static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	173	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	174	static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	175	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	176	static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	177	unsigned RegNo,
				178	uint64_t Address,
				179	const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	180	static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	181	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	182	static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	183	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	184	static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	185	unsigned RegNo, uint64_t Address,
				186	const void *Decoder);
Johnny Chen	74491bb	2010-08-12 01:40:54 +0000	[diff] [blame]	187
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	188	static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	189	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	190	static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	191	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	192	static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	193	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	194	static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	195	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	196	static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	197	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	198	static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	199	uint64_t Address, const void *Decoder);
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	200
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	201	static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	202	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	203	static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	204	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	205	static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	206	unsigned Insn,
				207	uint64_t Address,
				208	const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	209	static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	210	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	211	static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	212	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	213	static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	214	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	215	static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	216	uint64_t Address, const void *Decoder);
				217
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	218	static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	219	unsigned Insn,
				220	uint64_t Adddress,
				221	const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	222	static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	223	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	224	static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	225	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	226	static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	227	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	228	static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	3d2e0e9d	2011-08-09 23:05:39 +0000	[diff] [blame]	229	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	230	static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	231	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	232	static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	233	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	234	static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	235	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	236	static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	237	uint64_t Address, const void *Decoder);
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	238	static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
				239	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	240	static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	241	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	242	static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	243	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	244	static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
				245	uint64_t Address, const void *Decoder);
				246	static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
				247	uint64_t Address, const void *Decoder);
				248	static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
				249	uint64_t Address, const void *Decoder);
				250	static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
				251	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	252	static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	253	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	254	static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	255	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	256	static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	257	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	258	static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	259	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	260	static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	261	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	262	static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	263	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	264	static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	265	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	266	static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	267	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	268	static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	269	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	270	static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	271	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	272	static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	273	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	274	static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	275	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	276	static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	277	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	278	static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	279	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	280	static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	281	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	282	static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	283	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	43cb13a	2013-06-10 14:17:08 +0000	[diff] [blame]	284	static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
				285	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	286	static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	287	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	288	static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	289	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	290	static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	291	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	292	static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	293	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	294	static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	295	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	296	static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	297	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	298	static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	299	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	300	static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	301	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	302	static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	303	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	304	static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	305	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	306	static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	307	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	308	static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	309	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	310	static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	311	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	312	static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	313	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	314	static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	315	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	316	static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	317	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	318	static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	319	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	320	static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Anderson	dde461c	2011-10-28 18:02:13 +0000	[diff] [blame]	321	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	322	static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	323	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	324	static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	325	uint64_t Address, const void *Decoder);
Quentin Colombet	6f03f62	2013-04-17 18:46:12 +0000	[diff] [blame]	326	static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address,
				327	const void *Decoder);
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	328
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	329
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	330	static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	331	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	332	static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	333	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	334	static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	335	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	336	static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	337	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	338	static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	339	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	340	static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	341	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	342	static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	343	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	344	static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	345	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	346	static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	347	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	348	static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	349	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	350	static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
				351	uint64_t Address, const void* Decoder);
				352	static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
				353	uint64_t Address, const void* Decoder);
				354	static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
				355	uint64_t Address, const void* Decoder);
				356	static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
				357	uint64_t Address, const void* Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	358	static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	359	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	360	static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	361	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	362	static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbach	a05627e	2011-09-09 18:37:27 +0000	[diff] [blame]	363	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	364	static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	365	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	366	static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	367	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	368	static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	369	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	370	static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	371	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	372	static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	373	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	631df63	2013-06-08 13:38:52 +0000	[diff] [blame]	374	static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
				375	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	376	static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	377	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	378	static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	379	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	380	static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
Jim Grosbach	05541f4	2011-09-19 22:21:13 +0000	[diff] [blame]	381	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	382	static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	383	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	384	static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	385	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	386	static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	387	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	388	static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	389	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	390	static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
Owen Anderson	37612a3	2011-08-24 22:40:22 +0000	[diff] [blame]	391	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	392	static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	393	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	394	static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	395	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	396	static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	397	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	398	static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	399	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	400	static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	f01e2de	2011-09-26 21:06:22 +0000	[diff] [blame]	401	uint64_t Address, const void *Decoder);
				402
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	403	static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	404	uint64_t Address, const void *Decoder);
Silviu Baranga	41f1fcd	2012-04-18 13:12:50 +0000	[diff] [blame]	405	static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
				406	uint64_t Address, const void *Decoder);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	407	#include "ARMGenDisassemblerTables.inc"
Sean Callanan	814e69b	2010-04-13 21:21:57 +0000	[diff] [blame]	408
James Molloy	4c493e8	2011-09-07 17:24:38 +0000	[diff] [blame]	409	static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
				410	return new ARMDisassembler(STI);
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	411	}
				412
James Molloy	4c493e8	2011-09-07 17:24:38 +0000	[diff] [blame]	413	static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
				414	return new ThumbDisassembler(STI);
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	415	}
				416
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	417	DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Derek Schuff	56b662c	2012-02-29 01:09:06 +0000	[diff] [blame]	418	const MemoryObject &Region,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	419	uint64_t Address,
Owen Anderson	a0c3b97	2011-09-15 23:38:46 +0000	[diff] [blame]	420	raw_ostream &os,
				421	raw_ostream &cs) const {
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	422	CommentStream = &cs;
				423
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	424	uint8_t bytes[4];
				425
James Molloy	8067df9	2011-09-07 19:42:28 +0000	[diff] [blame]	426	assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
				427	"Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
				428
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	429	// We want to read exactly 4 bytes of data.
Benjamin Kramer	534d3a4	2013-05-24 10:54:58 +0000	[diff] [blame]	430	if (Region.readBytes(Address, 4, bytes) == -1) {
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	431	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	432	return MCDisassembler::Fail;
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	433	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	434
				435	// Encoded as a small-endian 32-bit word in the stream.
				436	uint32_t insn = (bytes[3] << 24) \|
				437	(bytes[2] << 16) \|
				438	(bytes[1] << 8) \|
				439	(bytes[0] << 0);
				440
				441	// Calling the auto-generated decoder function.
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	442	DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn,
				443	Address, this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	444	if (result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	445	Size = 4;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	446	return result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	447	}
				448
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	449	// VFP and NEON instructions, similarly, are shared between ARM
				450	// and Thumb modes.
				451	MI.clear();
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	452	result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	453	if (result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	454	Size = 4;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	455	return result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	456	}
				457
				458	MI.clear();
Joey Gouly	cc4ff9e	2013-07-04 14:57:20 +0000	[diff] [blame]	459	result = decodeInstruction(DecoderTableVFPV832, MI, insn, Address, this, STI);
				460	if (result != MCDisassembler::Fail) {
				461	Size = 4;
				462	return result;
				463	}
				464
				465	MI.clear();
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	466	result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address,
				467	this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	468	if (result != MCDisassembler::Fail) {
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	469	Size = 4;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	470	// Add a fake predicate operand, because we share these instruction
				471	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	472	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				473	return MCDisassembler::Fail;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	474	return result;
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	475	}
				476
				477	MI.clear();
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	478	result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address,
				479	this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	480	if (result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	481	Size = 4;
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	482	// Add a fake predicate operand, because we share these instruction
				483	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	484	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				485	return MCDisassembler::Fail;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	486	return result;
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	487	}
				488
				489	MI.clear();
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	490	result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address,
				491	this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	492	if (result != MCDisassembler::Fail) {
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	493	Size = 4;
				494	// Add a fake predicate operand, because we share these instruction
				495	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	496	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				497	return MCDisassembler::Fail;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	498	return result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	499	}
				500
				501	MI.clear();
Joey Gouly	df68600	2013-07-17 13:59:38 +0000	[diff] [blame^]	502	result = decodeInstruction(DecoderTablev8NEON32, MI, insn, Address,
				503	this, STI);
				504	if (result != MCDisassembler::Fail) {
				505	Size = 4;
				506	return result;
				507	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	508
Joey Gouly	df68600	2013-07-17 13:59:38 +0000	[diff] [blame^]	509	MI.clear();
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	510	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	511	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	512	}
				513
				514	namespace llvm {
Benjamin Kramer	0d6d098	2011-10-22 16:50:00 +0000	[diff] [blame]	515	extern const MCInstrDesc ARMInsts[];
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	516	}
				517
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	518	/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
				519	/// immediate Value in the MCInst. The immediate Value has had any PC
				520	/// adjustment made by the caller. If the instruction is a branch instruction
				521	/// then isBranch is true, else false. If the getOpInfo() function was set as
				522	/// part of the setupForSymbolicDisassembly() call then that function is called
				523	/// to get any symbolic information at the Address for this instruction. If
				524	/// that returns non-zero then the symbolic information it returns is used to
				525	/// create an MCExpr and that is added as an operand to the MCInst. If
				526	/// getOpInfo() returns zero and isBranch is true then a symbol look up for
				527	/// Value is done and if a symbol is found an MCExpr is created with that, else
				528	/// an MCExpr with Value is created. This function returns true if it adds an
				529	/// operand to the MCInst and false otherwise.
				530	static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
				531	bool isBranch, uint64_t InstSize,
				532	MCInst &MI, const void *Decoder) {
				533	const MCDisassembler Dis = static_cast<const MCDisassembler>(Decoder);
Ahmed Bougacha	ad1084d	2013-05-24 00:39:57 +0000	[diff] [blame]	534	// FIXME: Does it make sense for value to be negative?
				535	return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
				536	/* Offset */ 0, InstSize);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	537	}
				538
				539	/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
				540	/// referenced by a load instruction with the base register that is the Pc.
				541	/// These can often be values in a literal pool near the Address of the
				542	/// instruction. The Address of the instruction and its immediate Value are
				543	/// used as a possible literal pool entry. The SymbolLookUp call back will
Sylvestre Ledru	35521e2	2012-07-23 08:51:15 +0000	[diff] [blame]	544	/// return the name of a symbol referenced by the literal pool's entry if
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	545	/// the referenced address is that of a symbol. Or it will return a pointer to
				546	/// a literal 'C' string if the referenced address of the literal pool's entry
				547	/// is an address into a section with 'C' string literals.
				548	static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
Kevin Enderby	6fbcd8d	2012-02-23 18:18:17 +0000	[diff] [blame]	549	const void *Decoder) {
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	550	const MCDisassembler Dis = static_cast<const MCDisassembler>(Decoder);
Ahmed Bougacha	ad1084d	2013-05-24 00:39:57 +0000	[diff] [blame]	551	Dis->tryAddingPcLoadReferenceComment(Value, Address);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	552	}
				553
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	554	// Thumb1 instructions don't have explicit S bits. Rather, they
				555	// implicitly set CPSR. Since it's not represented in the encoding, the
				556	// auto-generated decoder won't inject the CPSR operand. We need to fix
				557	// that as a post-pass.
				558	static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
				559	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	560	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	561	MCInst::iterator I = MI.begin();
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	562	for (unsigned i = 0; i < NumOps; ++i, ++I) {
				563	if (I == MI.end()) break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	564	if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	565	if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	566	MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
				567	return;
				568	}
				569	}
				570
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	571	MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	572	}
				573
				574	// Most Thumb instructions don't have explicit predicates in the
				575	// encoding, but rather get their predicates from IT context. We need
				576	// to fix up the predicate operands using this context information as a
				577	// post-pass.
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	578	MCDisassembler::DecodeStatus
				579	ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	580	MCDisassembler::DecodeStatus S = Success;
				581
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	582	// A few instructions actually have predicates encoded in them. Don't
				583	// try to overwrite it if we're seeing one of those.
				584	switch (MI.getOpcode()) {
				585	case ARM::tBcc:
				586	case ARM::t2Bcc:
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	587	case ARM::tCBZ:
				588	case ARM::tCBNZ:
Owen Anderson	61e4604	2011-09-19 23:47:10 +0000	[diff] [blame]	589	case ARM::tCPS:
				590	case ARM::t2CPS3p:
				591	case ARM::t2CPS2p:
				592	case ARM::t2CPS1p:
Owen Anderson	163be01	2011-09-19 23:57:20 +0000	[diff] [blame]	593	case ARM::tMOVSr:
Owen Anderson	44f76ea	2011-10-13 17:58:39 +0000	[diff] [blame]	594	case ARM::tSETEND:
Owen Anderson	33d3953	2011-09-08 22:48:37 +0000	[diff] [blame]	595	// Some instructions (mostly conditional branches) are not
				596	// allowed in IT blocks.
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	597	if (ITBlock.instrInITBlock())
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	598	S = SoftFail;
				599	else
				600	return Success;
				601	break;
				602	case ARM::tB:
				603	case ARM::t2B:
Owen Anderson	f902d92	2011-09-19 22:34:23 +0000	[diff] [blame]	604	case ARM::t2TBB:
				605	case ARM::t2TBH:
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	606	// Some instructions (mostly unconditional branches) can
				607	// only appears at the end of, or outside of, an IT.
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	608	if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	609	S = SoftFail;
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	610	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	611	default:
				612	break;
				613	}
				614
				615	// If we're in an IT block, base the predicate on that. Otherwise,
				616	// assume a predicate of AL.
				617	unsigned CC;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	618	CC = ITBlock.getITCC();
				619	if (CC == 0xF)
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	620	CC = ARMCC::AL;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	621	if (ITBlock.instrInITBlock())
				622	ITBlock.advanceITState();
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	623
				624	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	625	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	626	MCInst::iterator I = MI.begin();
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	627	for (unsigned i = 0; i < NumOps; ++i, ++I) {
				628	if (I == MI.end()) break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	629	if (OpInfo[i].isPredicate()) {
				630	I = MI.insert(I, MCOperand::CreateImm(CC));
				631	++I;
				632	if (CC == ARMCC::AL)
				633	MI.insert(I, MCOperand::CreateReg(0));
				634	else
				635	MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	636	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	637	}
				638	}
				639
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	640	I = MI.insert(I, MCOperand::CreateImm(CC));
				641	++I;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	642	if (CC == ARMCC::AL)
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	643	MI.insert(I, MCOperand::CreateReg(0));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	644	else
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	645	MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	646
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	647	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	648	}
				649
				650	// Thumb VFP instructions are a special case. Because we share their
				651	// encodings between ARM and Thumb modes, and they are predicable in ARM
				652	// mode, the auto-generated decoder will give them an (incorrect)
				653	// predicate operand. We need to rewrite these operands based on the IT
				654	// context as a post-pass.
				655	void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
				656	unsigned CC;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	657	CC = ITBlock.getITCC();
				658	if (ITBlock.instrInITBlock())
				659	ITBlock.advanceITState();
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	660
				661	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
				662	MCInst::iterator I = MI.begin();
Owen Anderson	216cfaa	2011-08-24 21:35:46 +0000	[diff] [blame]	663	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
				664	for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	665	if (OpInfo[i].isPredicate() ) {
				666	I->setImm(CC);
				667	++I;
				668	if (CC == ARMCC::AL)
				669	I->setReg(0);
				670	else
				671	I->setReg(ARM::CPSR);
				672	return;
				673	}
				674	}
				675	}
				676
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	677	DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Derek Schuff	56b662c	2012-02-29 01:09:06 +0000	[diff] [blame]	678	const MemoryObject &Region,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	679	uint64_t Address,
Owen Anderson	a0c3b97	2011-09-15 23:38:46 +0000	[diff] [blame]	680	raw_ostream &os,
				681	raw_ostream &cs) const {
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	682	CommentStream = &cs;
				683
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	684	uint8_t bytes[4];
				685
James Molloy	8067df9	2011-09-07 19:42:28 +0000	[diff] [blame]	686	assert((STI.getFeatureBits() & ARM::ModeThumb) &&
				687	"Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
				688
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	689	// We want to read exactly 2 bytes of data.
Benjamin Kramer	534d3a4	2013-05-24 10:54:58 +0000	[diff] [blame]	690	if (Region.readBytes(Address, 2, bytes) == -1) {
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	691	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	692	return MCDisassembler::Fail;
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	693	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	694
				695	uint16_t insn16 = (bytes[1] << 8) \| bytes[0];
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	696	DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16,
				697	Address, this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	698	if (result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	699	Size = 2;
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	700	Check(result, AddThumbPredicate(MI));
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	701	return result;
Owen Anderson	91a8f9b	2011-08-16 23:45:44 +0000	[diff] [blame]	702	}
				703
				704	MI.clear();
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	705	result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16,
				706	Address, this, STI);
Owen Anderson	91a8f9b	2011-08-16 23:45:44 +0000	[diff] [blame]	707	if (result) {
				708	Size = 2;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	709	bool InITBlock = ITBlock.instrInITBlock();
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	710	Check(result, AddThumbPredicate(MI));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	711	AddThumb1SBit(MI, InITBlock);
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	712	return result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	713	}
				714
				715	MI.clear();
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	716	result = decodeInstruction(DecoderTableThumb216, MI, insn16,
				717	Address, this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	718	if (result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	719	Size = 2;
Owen Anderson	6a5c150	2011-10-06 23:33:11 +0000	[diff] [blame]	720
				721	// Nested IT blocks are UNPREDICTABLE. Must be checked before we add
				722	// the Thumb predicate.
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	723	if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
Owen Anderson	6a5c150	2011-10-06 23:33:11 +0000	[diff] [blame]	724	result = MCDisassembler::SoftFail;
				725
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	726	Check(result, AddThumbPredicate(MI));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	727
				728	// If we find an IT instruction, we need to parse its condition
				729	// code and mask operands so that we can apply them correctly
				730	// to the subsequent instructions.
				731	if (MI.getOpcode() == ARM::t2IT) {
Owen Anderson	f1e3844	2011-09-14 21:06:21 +0000	[diff] [blame]	732
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	733	unsigned Firstcond = MI.getOperand(0).getImm();
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	734	unsigned Mask = MI.getOperand(1).getImm();
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	735	ITBlock.setITState(Firstcond, Mask);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	736	}
				737
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	738	return result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	739	}
				740
				741	// We want to read exactly 4 bytes of data.
Benjamin Kramer	534d3a4	2013-05-24 10:54:58 +0000	[diff] [blame]	742	if (Region.readBytes(Address, 4, bytes) == -1) {
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	743	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	744	return MCDisassembler::Fail;
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	745	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	746
				747	uint32_t insn32 = (bytes[3] << 8) \|
				748	(bytes[2] << 0) \|
				749	(bytes[1] << 24) \|
				750	(bytes[0] << 16);
				751	MI.clear();
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	752	result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address,
				753	this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	754	if (result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	755	Size = 4;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	756	bool InITBlock = ITBlock.instrInITBlock();
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	757	Check(result, AddThumbPredicate(MI));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	758	AddThumb1SBit(MI, InITBlock);
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	759	return result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	760	}
				761
				762	MI.clear();
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	763	result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address,
				764	this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	765	if (result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	766	Size = 4;
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	767	Check(result, AddThumbPredicate(MI));
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	768	return result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	769	}
				770
Amaury de la Vieuville	8449c0d	2013-06-24 09:15:01 +0000	[diff] [blame]	771	if (fieldFromInstruction(insn32, 28, 4) == 0xE) {
				772	MI.clear();
				773	result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI);
				774	if (result != MCDisassembler::Fail) {
				775	Size = 4;
				776	UpdateThumbVFPPredicate(MI);
				777	return result;
				778	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	779	}
				780
Joey Gouly	cc4ff9e	2013-07-04 14:57:20 +0000	[diff] [blame]	781	MI.clear();
				782	result = decodeInstruction(DecoderTableVFPV832, MI, insn32, Address, this, STI);
				783	if (result != MCDisassembler::Fail) {
				784	Size = 4;
Joey Gouly	cc4ff9e	2013-07-04 14:57:20 +0000	[diff] [blame]	785	return result;
				786	}
				787
Amaury de la Vieuville	8449c0d	2013-06-24 09:15:01 +0000	[diff] [blame]	788	if (fieldFromInstruction(insn32, 28, 4) == 0xE) {
				789	MI.clear();
				790	result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address,
				791	this, STI);
				792	if (result != MCDisassembler::Fail) {
				793	Size = 4;
				794	Check(result, AddThumbPredicate(MI));
				795	return result;
				796	}
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	797	}
				798
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	799	if (fieldFromInstruction(insn32, 24, 8) == 0xF9) {
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	800	MI.clear();
				801	uint32_t NEONLdStInsn = insn32;
				802	NEONLdStInsn &= 0xF0FFFFFF;
				803	NEONLdStInsn \|= 0x04000000;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	804	result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
				805	Address, this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	806	if (result != MCDisassembler::Fail) {
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	807	Size = 4;
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	808	Check(result, AddThumbPredicate(MI));
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	809	return result;
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	810	}
				811	}
				812
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	813	if (fieldFromInstruction(insn32, 24, 4) == 0xF) {
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	814	MI.clear();
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	815	uint32_t NEONDataInsn = insn32;
				816	NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
				817	NEONDataInsn \|= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
				818	NEONDataInsn \|= 0x12000000; // Set bits 28 and 25
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	819	result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
				820	Address, this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	821	if (result != MCDisassembler::Fail) {
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	822	Size = 4;
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	823	Check(result, AddThumbPredicate(MI));
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	824	return result;
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	825	}
				826	}
				827
Joey Gouly	df68600	2013-07-17 13:59:38 +0000	[diff] [blame^]	828	MI.clear();
				829	uint32_t NEONv8Insn = insn32;
				830	NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
				831	result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
				832	this, STI);
				833	if (result != MCDisassembler::Fail) {
				834	Size = 4;
				835	return result;
				836	}
				837
				838	MI.clear();
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	839	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	840	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	841	}
				842
				843
				844	extern "C" void LLVMInitializeARMDisassembler() {
				845	TargetRegistry::RegisterMCDisassembler(TheARMTarget,
				846	createARMDisassembler);
				847	TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
				848	createThumbDisassembler);
				849	}
				850
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	851	static const uint16_t GPRDecoderTable[] = {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	852	ARM::R0, ARM::R1, ARM::R2, ARM::R3,
				853	ARM::R4, ARM::R5, ARM::R6, ARM::R7,
				854	ARM::R8, ARM::R9, ARM::R10, ARM::R11,
				855	ARM::R12, ARM::SP, ARM::LR, ARM::PC
				856	};
				857
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	858	static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	859	uint64_t Address, const void *Decoder) {
				860	if (RegNo > 15)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	861	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	862
				863	unsigned Register = GPRDecoderTable[RegNo];
				864	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	865	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	866	}
				867
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	868	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	869	DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	870	uint64_t Address, const void *Decoder) {
Silviu Baranga	32a4933	2012-03-20 15:54:56 +0000	[diff] [blame]	871	DecodeStatus S = MCDisassembler::Success;
				872
				873	if (RegNo == 15)
				874	S = MCDisassembler::SoftFail;
				875
				876	Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
				877
				878	return S;
Owen Anderson	042619f	2011-08-09 22:48:45 +0000	[diff] [blame]	879	}
				880
Mihai Popa	dc1764c5	2013-05-13 14:10:04 +0000	[diff] [blame]	881	static DecodeStatus
				882	DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
				883	uint64_t Address, const void *Decoder) {
				884	DecodeStatus S = MCDisassembler::Success;
				885
				886	if (RegNo == 15)
				887	{
				888	Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV));
				889	return MCDisassembler::Success;
				890	}
				891
				892	Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
				893	return S;
				894	}
				895
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	896	static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	897	uint64_t Address, const void *Decoder) {
				898	if (RegNo > 7)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	899	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	900	return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
				901	}
				902
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	903	static const uint16_t GPRPairDecoderTable[] = {
				904	ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
				905	ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
				906	};
				907
				908	static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
				909	uint64_t Address, const void *Decoder) {
				910	DecodeStatus S = MCDisassembler::Success;
				911
				912	if (RegNo > 13)
				913	return MCDisassembler::Fail;
				914
				915	if ((RegNo & 1) \|\| RegNo == 0xe)
				916	S = MCDisassembler::SoftFail;
				917
				918	unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
				919	Inst.addOperand(MCOperand::CreateReg(RegisterPair));
				920	return S;
				921	}
				922
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	923	static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	924	uint64_t Address, const void *Decoder) {
				925	unsigned Register = 0;
				926	switch (RegNo) {
				927	case 0:
				928	Register = ARM::R0;
				929	break;
				930	case 1:
				931	Register = ARM::R1;
				932	break;
				933	case 2:
				934	Register = ARM::R2;
				935	break;
				936	case 3:
				937	Register = ARM::R3;
				938	break;
				939	case 9:
				940	Register = ARM::R9;
				941	break;
				942	case 12:
				943	Register = ARM::R12;
				944	break;
				945	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	946	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	947	}
				948
				949	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	950	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	951	}
				952
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	953	static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	954	uint64_t Address, const void *Decoder) {
Amaury de la Vieuville	8175bda	2013-06-24 09:14:54 +0000	[diff] [blame]	955	DecodeStatus S = MCDisassembler::Success;
				956	if (RegNo == 13 \|\| RegNo == 15)
				957	S = MCDisassembler::SoftFail;
				958	Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
				959	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	960	}
				961
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	962	static const uint16_t SPRDecoderTable[] = {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	963	ARM::S0, ARM::S1, ARM::S2, ARM::S3,
				964	ARM::S4, ARM::S5, ARM::S6, ARM::S7,
				965	ARM::S8, ARM::S9, ARM::S10, ARM::S11,
				966	ARM::S12, ARM::S13, ARM::S14, ARM::S15,
				967	ARM::S16, ARM::S17, ARM::S18, ARM::S19,
				968	ARM::S20, ARM::S21, ARM::S22, ARM::S23,
				969	ARM::S24, ARM::S25, ARM::S26, ARM::S27,
				970	ARM::S28, ARM::S29, ARM::S30, ARM::S31
				971	};
				972
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	973	static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	974	uint64_t Address, const void *Decoder) {
				975	if (RegNo > 31)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	976	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	977
				978	unsigned Register = SPRDecoderTable[RegNo];
				979	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	980	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	981	}
				982
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	983	static const uint16_t DPRDecoderTable[] = {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	984	ARM::D0, ARM::D1, ARM::D2, ARM::D3,
				985	ARM::D4, ARM::D5, ARM::D6, ARM::D7,
				986	ARM::D8, ARM::D9, ARM::D10, ARM::D11,
				987	ARM::D12, ARM::D13, ARM::D14, ARM::D15,
				988	ARM::D16, ARM::D17, ARM::D18, ARM::D19,
				989	ARM::D20, ARM::D21, ARM::D22, ARM::D23,
				990	ARM::D24, ARM::D25, ARM::D26, ARM::D27,
				991	ARM::D28, ARM::D29, ARM::D30, ARM::D31
				992	};
				993
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	994	static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	995	uint64_t Address, const void *Decoder) {
				996	if (RegNo > 31)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	997	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	998
				999	unsigned Register = DPRDecoderTable[RegNo];
				1000	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1001	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1002	}
				1003
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1004	static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1005	uint64_t Address, const void *Decoder) {
				1006	if (RegNo > 7)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1007	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1008	return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
				1009	}
				1010
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1011	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1012	DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	1013	uint64_t Address, const void *Decoder) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1014	if (RegNo > 15)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1015	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1016	return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
				1017	}
				1018
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	1019	static const uint16_t QPRDecoderTable[] = {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1020	ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
				1021	ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
				1022	ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
				1023	ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
				1024	};
				1025
				1026
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1027	static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1028	uint64_t Address, const void *Decoder) {
Mihai Popa	dcf0922	2013-05-20 14:42:43 +0000	[diff] [blame]	1029	if (RegNo > 31 \|\| (RegNo & 1) != 0)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1030	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1031	RegNo >>= 1;
				1032
				1033	unsigned Register = QPRDecoderTable[RegNo];
				1034	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1035	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1036	}
				1037
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	1038	static const uint16_t DPairDecoderTable[] = {
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	1039	ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
				1040	ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
				1041	ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
				1042	ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
				1043	ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
				1044	ARM::Q15
				1045	};
				1046
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1047	static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	1048	uint64_t Address, const void *Decoder) {
				1049	if (RegNo > 30)
				1050	return MCDisassembler::Fail;
				1051
				1052	unsigned Register = DPairDecoderTable[RegNo];
				1053	Inst.addOperand(MCOperand::CreateReg(Register));
				1054	return MCDisassembler::Success;
				1055	}
				1056
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	1057	static const uint16_t DPairSpacedDecoderTable[] = {
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	1058	ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
				1059	ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
				1060	ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
				1061	ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
				1062	ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
				1063	ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
				1064	ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
				1065	ARM::D28_D30, ARM::D29_D31
				1066	};
				1067
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1068	static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	1069	unsigned RegNo,
				1070	uint64_t Address,
				1071	const void *Decoder) {
				1072	if (RegNo > 29)
				1073	return MCDisassembler::Fail;
				1074
				1075	unsigned Register = DPairSpacedDecoderTable[RegNo];
				1076	Inst.addOperand(MCOperand::CreateReg(Register));
				1077	return MCDisassembler::Success;
				1078	}
				1079
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1080	static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1081	uint64_t Address, const void *Decoder) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1082	if (Val == 0xF) return MCDisassembler::Fail;
Owen Anderson	7a2401d	2011-08-09 21:07:45 +0000	[diff] [blame]	1083	// AL predicate is not allowed on Thumb1 branches.
				1084	if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1085	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1086	Inst.addOperand(MCOperand::CreateImm(Val));
				1087	if (Val == ARMCC::AL) {
				1088	Inst.addOperand(MCOperand::CreateReg(0));
				1089	} else
				1090	Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1091	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1092	}
				1093
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1094	static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1095	uint64_t Address, const void *Decoder) {
				1096	if (Val)
				1097	Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
				1098	else
				1099	Inst.addOperand(MCOperand::CreateReg(0));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1100	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1101	}
				1102
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1103	static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1104	uint64_t Address, const void *Decoder) {
				1105	uint32_t imm = Val & 0xFF;
				1106	uint32_t rot = (Val & 0xF00) >> 7;
Eli Friedman	a7ad9f3	2011-10-13 23:36:06 +0000	[diff] [blame]	1107	uint32_t rot_imm = (imm >> rot) \| (imm << ((32-rot) & 0x1F));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1108	Inst.addOperand(MCOperand::CreateImm(rot_imm));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1109	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1110	}
				1111
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1112	static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1113	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1114	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1115
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1116	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				1117	unsigned type = fieldFromInstruction(Val, 5, 2);
				1118	unsigned imm = fieldFromInstruction(Val, 7, 5);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1119
				1120	// Register-immediate
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1121	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1122	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1123
				1124	ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
				1125	switch (type) {
				1126	case 0:
				1127	Shift = ARM_AM::lsl;
				1128	break;
				1129	case 1:
				1130	Shift = ARM_AM::lsr;
				1131	break;
				1132	case 2:
				1133	Shift = ARM_AM::asr;
				1134	break;
				1135	case 3:
				1136	Shift = ARM_AM::ror;
				1137	break;
				1138	}
				1139
				1140	if (Shift == ARM_AM::ror && imm == 0)
				1141	Shift = ARM_AM::rrx;
				1142
				1143	unsigned Op = Shift \| (imm << 3);
				1144	Inst.addOperand(MCOperand::CreateImm(Op));
				1145
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1146	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1147	}
				1148
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1149	static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1150	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1151	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1152
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1153	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				1154	unsigned type = fieldFromInstruction(Val, 5, 2);
				1155	unsigned Rs = fieldFromInstruction(Val, 8, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1156
				1157	// Register-register
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1158	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1159	return MCDisassembler::Fail;
				1160	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
				1161	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1162
				1163	ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
				1164	switch (type) {
				1165	case 0:
				1166	Shift = ARM_AM::lsl;
				1167	break;
				1168	case 1:
				1169	Shift = ARM_AM::lsr;
				1170	break;
				1171	case 2:
				1172	Shift = ARM_AM::asr;
				1173	break;
				1174	case 3:
				1175	Shift = ARM_AM::ror;
				1176	break;
				1177	}
				1178
				1179	Inst.addOperand(MCOperand::CreateImm(Shift));
				1180
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1181	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1182	}
				1183
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1184	static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1185	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1186	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1187
Owen Anderson	53db43b	2011-09-09 23:13:33 +0000	[diff] [blame]	1188	bool writebackLoad = false;
				1189	unsigned writebackReg = 0;
				1190	switch (Inst.getOpcode()) {
				1191	default:
				1192	break;
				1193	case ARM::LDMIA_UPD:
				1194	case ARM::LDMDB_UPD:
				1195	case ARM::LDMIB_UPD:
				1196	case ARM::LDMDA_UPD:
				1197	case ARM::t2LDMIA_UPD:
				1198	case ARM::t2LDMDB_UPD:
				1199	writebackLoad = true;
				1200	writebackReg = Inst.getOperand(0).getReg();
				1201	break;
				1202	}
				1203
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	1204	// Empty register lists are not allowed.
Benjamin Kramer	8bad66e	2013-05-19 22:01:57 +0000	[diff] [blame]	1205	if (Val == 0) return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1206	for (unsigned i = 0; i < 16; ++i) {
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1207	if (Val & (1 << i)) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1208	if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
				1209	return MCDisassembler::Fail;
Owen Anderson	53db43b	2011-09-09 23:13:33 +0000	[diff] [blame]	1210	// Writeback not allowed if Rn is in the target list.
				1211	if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
				1212	Check(S, MCDisassembler::SoftFail);
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1213	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1214	}
				1215
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1216	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1217	}
				1218
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1219	static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1220	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1221	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1222
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1223	unsigned Vd = fieldFromInstruction(Val, 8, 5);
				1224	unsigned regs = fieldFromInstruction(Val, 0, 8);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1225
Tim Northover	4173e29	2013-05-31 15:55:51 +0000	[diff] [blame]	1226	// In case of unpredictable encoding, tweak the operands.
				1227	if (regs == 0 \|\| (Vd + regs) > 32) {
				1228	regs = Vd + regs > 32 ? 32 - Vd : regs;
				1229	regs = std::max( 1u, regs);
				1230	S = MCDisassembler::SoftFail;
				1231	}
				1232
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1233	if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
				1234	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1235	for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1236	if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
				1237	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1238	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1239
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1240	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1241	}
				1242
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1243	static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1244	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1245	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1246
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1247	unsigned Vd = fieldFromInstruction(Val, 8, 5);
Tim Northover	4173e29	2013-05-31 15:55:51 +0000	[diff] [blame]	1248	unsigned regs = fieldFromInstruction(Val, 1, 7);
Silviu Baranga	9560af8	2012-05-03 16:38:40 +0000	[diff] [blame]	1249
Tim Northover	4173e29	2013-05-31 15:55:51 +0000	[diff] [blame]	1250	// In case of unpredictable encoding, tweak the operands.
				1251	if (regs == 0 \|\| regs > 16 \|\| (Vd + regs) > 32) {
				1252	regs = Vd + regs > 32 ? 32 - Vd : regs;
				1253	regs = std::max( 1u, regs);
				1254	regs = std::min(16u, regs);
				1255	S = MCDisassembler::SoftFail;
				1256	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1257
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1258	if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
				1259	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1260	for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1261	if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
				1262	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1263	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1264
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1265	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1266	}
				1267
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1268	static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1269	uint64_t Address, const void *Decoder) {
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	1270	// This operand encodes a mask of contiguous zeros between a specified MSB
				1271	// and LSB. To decode it, we create the mask of all bits MSB-and-lower,
				1272	// the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	1273	// the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	1274	// create the final mask.
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1275	unsigned msb = fieldFromInstruction(Val, 5, 5);
				1276	unsigned lsb = fieldFromInstruction(Val, 0, 5);
Owen Anderson	3ca958c	2011-09-16 22:29:48 +0000	[diff] [blame]	1277
Owen Anderson	502cd9d	2011-09-16 23:30:01 +0000	[diff] [blame]	1278	DecodeStatus S = MCDisassembler::Success;
Kevin Enderby	136d674	2012-11-29 23:47:11 +0000	[diff] [blame]	1279	if (lsb > msb) {
				1280	Check(S, MCDisassembler::SoftFail);
				1281	// The check above will cause the warning for the "potentially undefined
				1282	// instruction encoding" but we can't build a bad MCOperand value here
				1283	// with a lsb > msb or else printing the MCInst will cause a crash.
				1284	lsb = msb;
				1285	}
Owen Anderson	502cd9d	2011-09-16 23:30:01 +0000	[diff] [blame]	1286
Owen Anderson	b925e93	2011-09-16 23:04:48 +0000	[diff] [blame]	1287	uint32_t msb_mask = 0xFFFFFFFF;
				1288	if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
				1289	uint32_t lsb_mask = (1U << lsb) - 1;
Owen Anderson	3ca958c	2011-09-16 22:29:48 +0000	[diff] [blame]	1290
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1291	Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
Owen Anderson	502cd9d	2011-09-16 23:30:01 +0000	[diff] [blame]	1292	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1293	}
				1294
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1295	static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1296	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1297	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1298
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1299	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1300	unsigned CRd = fieldFromInstruction(Insn, 12, 4);
				1301	unsigned coproc = fieldFromInstruction(Insn, 8, 4);
				1302	unsigned imm = fieldFromInstruction(Insn, 0, 8);
				1303	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1304	unsigned U = fieldFromInstruction(Insn, 23, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1305
				1306	switch (Inst.getOpcode()) {
				1307	case ARM::LDC_OFFSET:
				1308	case ARM::LDC_PRE:
				1309	case ARM::LDC_POST:
				1310	case ARM::LDC_OPTION:
				1311	case ARM::LDCL_OFFSET:
				1312	case ARM::LDCL_PRE:
				1313	case ARM::LDCL_POST:
				1314	case ARM::LDCL_OPTION:
				1315	case ARM::STC_OFFSET:
				1316	case ARM::STC_PRE:
				1317	case ARM::STC_POST:
				1318	case ARM::STC_OPTION:
				1319	case ARM::STCL_OFFSET:
				1320	case ARM::STCL_PRE:
				1321	case ARM::STCL_POST:
				1322	case ARM::STCL_OPTION:
Owen Anderson	18d17aa	2011-09-07 21:10:42 +0000	[diff] [blame]	1323	case ARM::t2LDC_OFFSET:
				1324	case ARM::t2LDC_PRE:
				1325	case ARM::t2LDC_POST:
				1326	case ARM::t2LDC_OPTION:
				1327	case ARM::t2LDCL_OFFSET:
				1328	case ARM::t2LDCL_PRE:
				1329	case ARM::t2LDCL_POST:
				1330	case ARM::t2LDCL_OPTION:
				1331	case ARM::t2STC_OFFSET:
				1332	case ARM::t2STC_PRE:
				1333	case ARM::t2STC_POST:
				1334	case ARM::t2STC_OPTION:
				1335	case ARM::t2STCL_OFFSET:
				1336	case ARM::t2STCL_PRE:
				1337	case ARM::t2STCL_POST:
				1338	case ARM::t2STCL_OPTION:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1339	if (coproc == 0xA \|\| coproc == 0xB)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1340	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1341	break;
				1342	default:
				1343	break;
				1344	}
				1345
				1346	Inst.addOperand(MCOperand::CreateImm(coproc));
				1347	Inst.addOperand(MCOperand::CreateImm(CRd));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1348	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1349	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1350
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1351	switch (Inst.getOpcode()) {
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1352	case ARM::t2LDC2_OFFSET:
				1353	case ARM::t2LDC2L_OFFSET:
				1354	case ARM::t2LDC2_PRE:
				1355	case ARM::t2LDC2L_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1356	case ARM::t2STC2_OFFSET:
				1357	case ARM::t2STC2L_OFFSET:
				1358	case ARM::t2STC2_PRE:
				1359	case ARM::t2STC2L_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1360	case ARM::LDC2_OFFSET:
				1361	case ARM::LDC2L_OFFSET:
				1362	case ARM::LDC2_PRE:
				1363	case ARM::LDC2L_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1364	case ARM::STC2_OFFSET:
				1365	case ARM::STC2L_OFFSET:
				1366	case ARM::STC2_PRE:
				1367	case ARM::STC2L_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1368	case ARM::t2LDC_OFFSET:
				1369	case ARM::t2LDCL_OFFSET:
				1370	case ARM::t2LDC_PRE:
				1371	case ARM::t2LDCL_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1372	case ARM::t2STC_OFFSET:
				1373	case ARM::t2STCL_OFFSET:
				1374	case ARM::t2STC_PRE:
				1375	case ARM::t2STCL_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1376	case ARM::LDC_OFFSET:
				1377	case ARM::LDCL_OFFSET:
				1378	case ARM::LDC_PRE:
				1379	case ARM::LDCL_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1380	case ARM::STC_OFFSET:
				1381	case ARM::STCL_OFFSET:
				1382	case ARM::STC_PRE:
				1383	case ARM::STCL_PRE:
Jim Grosbach	a098a89	2011-10-12 21:59:02 +0000	[diff] [blame]	1384	imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
				1385	Inst.addOperand(MCOperand::CreateImm(imm));
				1386	break;
				1387	case ARM::t2LDC2_POST:
				1388	case ARM::t2LDC2L_POST:
				1389	case ARM::t2STC2_POST:
				1390	case ARM::t2STC2L_POST:
				1391	case ARM::LDC2_POST:
				1392	case ARM::LDC2L_POST:
				1393	case ARM::STC2_POST:
				1394	case ARM::STC2L_POST:
				1395	case ARM::t2LDC_POST:
				1396	case ARM::t2LDCL_POST:
				1397	case ARM::t2STC_POST:
				1398	case ARM::t2STCL_POST:
				1399	case ARM::LDC_POST:
				1400	case ARM::LDCL_POST:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1401	case ARM::STC_POST:
				1402	case ARM::STCL_POST:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1403	imm \|= U << 8;
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1404	// fall through.
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1405	default:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1406	// The 'option' variant doesn't encode 'U' in the immediate since
				1407	// the immediate is unsigned [0,255].
				1408	Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1409	break;
				1410	}
				1411
				1412	switch (Inst.getOpcode()) {
				1413	case ARM::LDC_OFFSET:
				1414	case ARM::LDC_PRE:
				1415	case ARM::LDC_POST:
				1416	case ARM::LDC_OPTION:
				1417	case ARM::LDCL_OFFSET:
				1418	case ARM::LDCL_PRE:
				1419	case ARM::LDCL_POST:
				1420	case ARM::LDCL_OPTION:
				1421	case ARM::STC_OFFSET:
				1422	case ARM::STC_PRE:
				1423	case ARM::STC_POST:
				1424	case ARM::STC_OPTION:
				1425	case ARM::STCL_OFFSET:
				1426	case ARM::STCL_PRE:
				1427	case ARM::STCL_POST:
				1428	case ARM::STCL_OPTION:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1429	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1430	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1431	break;
				1432	default:
				1433	break;
				1434	}
				1435
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1436	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1437	}
				1438
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1439	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1440	DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	1441	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1442	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1443
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1444	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1445	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				1446	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				1447	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				1448	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1449	unsigned reg = fieldFromInstruction(Insn, 25, 1);
				1450	unsigned P = fieldFromInstruction(Insn, 24, 1);
				1451	unsigned W = fieldFromInstruction(Insn, 21, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1452
				1453	// On stores, the writeback operand precedes Rt.
				1454	switch (Inst.getOpcode()) {
				1455	case ARM::STR_POST_IMM:
				1456	case ARM::STR_POST_REG:
Owen Anderson	3a850f2	2011-08-11 20:47:56 +0000	[diff] [blame]	1457	case ARM::STRB_POST_IMM:
				1458	case ARM::STRB_POST_REG:
Jim Grosbach	e259421	2011-08-11 22:18:00 +0000	[diff] [blame]	1459	case ARM::STRT_POST_REG:
				1460	case ARM::STRT_POST_IMM:
Jim Grosbach	2a50260	2011-08-11 20:04:56 +0000	[diff] [blame]	1461	case ARM::STRBT_POST_REG:
				1462	case ARM::STRBT_POST_IMM:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1463	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1464	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1465	break;
				1466	default:
				1467	break;
				1468	}
				1469
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1470	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				1471	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1472
				1473	// On loads, the writeback operand comes after Rt.
				1474	switch (Inst.getOpcode()) {
				1475	case ARM::LDR_POST_IMM:
				1476	case ARM::LDR_POST_REG:
Owen Anderson	3a850f2	2011-08-11 20:47:56 +0000	[diff] [blame]	1477	case ARM::LDRB_POST_IMM:
				1478	case ARM::LDRB_POST_REG:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1479	case ARM::LDRBT_POST_REG:
				1480	case ARM::LDRBT_POST_IMM:
Jim Grosbach	d5d6359	2011-08-10 23:43:54 +0000	[diff] [blame]	1481	case ARM::LDRT_POST_REG:
				1482	case ARM::LDRT_POST_IMM:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1483	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1484	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1485	break;
				1486	default:
				1487	break;
				1488	}
				1489
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1490	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1491	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1492
				1493	ARM_AM::AddrOpc Op = ARM_AM::add;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1494	if (!fieldFromInstruction(Insn, 23, 1))
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1495	Op = ARM_AM::sub;
				1496
				1497	bool writeback = (P == 0) \|\| (W == 1);
				1498	unsigned idx_mode = 0;
				1499	if (P && writeback)
				1500	idx_mode = ARMII::IndexModePre;
				1501	else if (!P && writeback)
				1502	idx_mode = ARMII::IndexModePost;
				1503
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1504	if (writeback && (Rn == 15 \|\| Rn == Rt))
				1505	S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson	3477f2c	2011-08-11 19:00:18 +0000	[diff] [blame]	1506
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1507	if (reg) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1508	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1509	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1510	ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1511	switch( fieldFromInstruction(Insn, 5, 2)) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1512	case 0:
				1513	Opc = ARM_AM::lsl;
				1514	break;
				1515	case 1:
				1516	Opc = ARM_AM::lsr;
				1517	break;
				1518	case 2:
				1519	Opc = ARM_AM::asr;
				1520	break;
				1521	case 3:
				1522	Opc = ARM_AM::ror;
				1523	break;
				1524	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1525	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1526	}
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1527	unsigned amt = fieldFromInstruction(Insn, 7, 5);
Tim Northover	0c97e76	2012-09-22 11:18:12 +0000	[diff] [blame]	1528	if (Opc == ARM_AM::ror && amt == 0)
				1529	Opc = ARM_AM::rrx;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1530	unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
				1531
				1532	Inst.addOperand(MCOperand::CreateImm(imm));
				1533	} else {
				1534	Inst.addOperand(MCOperand::CreateReg(0));
				1535	unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
				1536	Inst.addOperand(MCOperand::CreateImm(tmp));
				1537	}
				1538
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1539	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1540	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1541
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1542	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1543	}
				1544
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1545	static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1546	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1547	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1548
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1549	unsigned Rn = fieldFromInstruction(Val, 13, 4);
				1550	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				1551	unsigned type = fieldFromInstruction(Val, 5, 2);
				1552	unsigned imm = fieldFromInstruction(Val, 7, 5);
				1553	unsigned U = fieldFromInstruction(Val, 12, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1554
Owen Anderson	d151b09	2011-08-09 21:38:14 +0000	[diff] [blame]	1555	ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1556	switch (type) {
				1557	case 0:
				1558	ShOp = ARM_AM::lsl;
				1559	break;
				1560	case 1:
				1561	ShOp = ARM_AM::lsr;
				1562	break;
				1563	case 2:
				1564	ShOp = ARM_AM::asr;
				1565	break;
				1566	case 3:
				1567	ShOp = ARM_AM::ror;
				1568	break;
				1569	}
				1570
Tim Northover	0c97e76	2012-09-22 11:18:12 +0000	[diff] [blame]	1571	if (ShOp == ARM_AM::ror && imm == 0)
				1572	ShOp = ARM_AM::rrx;
				1573
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1574	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1575	return MCDisassembler::Fail;
				1576	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1577	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1578	unsigned shift;
				1579	if (U)
				1580	shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
				1581	else
				1582	shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
				1583	Inst.addOperand(MCOperand::CreateImm(shift));
				1584
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1585	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1586	}
				1587
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1588	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1589	DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	1590	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1591	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1592
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1593	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				1594	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1595	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				1596	unsigned type = fieldFromInstruction(Insn, 22, 1);
				1597	unsigned imm = fieldFromInstruction(Insn, 8, 4);
				1598	unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
				1599	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1600	unsigned W = fieldFromInstruction(Insn, 21, 1);
				1601	unsigned P = fieldFromInstruction(Insn, 24, 1);
Silviu Baranga	4afd7d2	2012-03-22 14:14:49 +0000	[diff] [blame]	1602	unsigned Rt2 = Rt + 1;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1603
				1604	bool writeback = (W == 1) \| (P == 0);
Owen Anderson	1d5d2ca	2011-08-15 20:51:32 +0000	[diff] [blame]	1605
				1606	// For {LD,ST}RD, Rt must be even, else undefined.
				1607	switch (Inst.getOpcode()) {
				1608	case ARM::STRD:
				1609	case ARM::STRD_PRE:
				1610	case ARM::STRD_POST:
				1611	case ARM::LDRD:
				1612	case ARM::LDRD_PRE:
				1613	case ARM::LDRD_POST:
Silviu Baranga	4afd7d2	2012-03-22 14:14:49 +0000	[diff] [blame]	1614	if (Rt & 0x1) S = MCDisassembler::SoftFail;
				1615	break;
				1616	default:
				1617	break;
				1618	}
				1619	switch (Inst.getOpcode()) {
				1620	case ARM::STRD:
				1621	case ARM::STRD_PRE:
				1622	case ARM::STRD_POST:
				1623	if (P == 0 && W == 1)
				1624	S = MCDisassembler::SoftFail;
				1625
				1626	if (writeback && (Rn == 15 \|\| Rn == Rt \|\| Rn == Rt2))
				1627	S = MCDisassembler::SoftFail;
				1628	if (type && Rm == 15)
				1629	S = MCDisassembler::SoftFail;
				1630	if (Rt2 == 15)
				1631	S = MCDisassembler::SoftFail;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1632	if (!type && fieldFromInstruction(Insn, 8, 4))
Silviu Baranga	4afd7d2	2012-03-22 14:14:49 +0000	[diff] [blame]	1633	S = MCDisassembler::SoftFail;
				1634	break;
				1635	case ARM::STRH:
				1636	case ARM::STRH_PRE:
				1637	case ARM::STRH_POST:
				1638	if (Rt == 15)
				1639	S = MCDisassembler::SoftFail;
				1640	if (writeback && (Rn == 15 \|\| Rn == Rt))
				1641	S = MCDisassembler::SoftFail;
				1642	if (!type && Rm == 15)
				1643	S = MCDisassembler::SoftFail;
				1644	break;
				1645	case ARM::LDRD:
				1646	case ARM::LDRD_PRE:
				1647	case ARM::LDRD_POST:
				1648	if (type && Rn == 15){
				1649	if (Rt2 == 15)
				1650	S = MCDisassembler::SoftFail;
				1651	break;
				1652	}
				1653	if (P == 0 && W == 1)
				1654	S = MCDisassembler::SoftFail;
				1655	if (!type && (Rt2 == 15 \|\| Rm == 15 \|\| Rm == Rt \|\| Rm == Rt2))
				1656	S = MCDisassembler::SoftFail;
				1657	if (!type && writeback && Rn == 15)
				1658	S = MCDisassembler::SoftFail;
				1659	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				1660	S = MCDisassembler::SoftFail;
				1661	break;
				1662	case ARM::LDRH:
				1663	case ARM::LDRH_PRE:
				1664	case ARM::LDRH_POST:
				1665	if (type && Rn == 15){
				1666	if (Rt == 15)
				1667	S = MCDisassembler::SoftFail;
				1668	break;
				1669	}
				1670	if (Rt == 15)
				1671	S = MCDisassembler::SoftFail;
				1672	if (!type && Rm == 15)
				1673	S = MCDisassembler::SoftFail;
				1674	if (!type && writeback && (Rn == 15 \|\| Rn == Rt))
				1675	S = MCDisassembler::SoftFail;
				1676	break;
				1677	case ARM::LDRSH:
				1678	case ARM::LDRSH_PRE:
				1679	case ARM::LDRSH_POST:
				1680	case ARM::LDRSB:
				1681	case ARM::LDRSB_PRE:
				1682	case ARM::LDRSB_POST:
				1683	if (type && Rn == 15){
				1684	if (Rt == 15)
				1685	S = MCDisassembler::SoftFail;
				1686	break;
				1687	}
				1688	if (type && (Rt == 15 \|\| (writeback && Rn == Rt)))
				1689	S = MCDisassembler::SoftFail;
				1690	if (!type && (Rt == 15 \|\| Rm == 15))
				1691	S = MCDisassembler::SoftFail;
				1692	if (!type && writeback && (Rn == 15 \|\| Rn == Rt))
				1693	S = MCDisassembler::SoftFail;
Owen Anderson	1d5d2ca	2011-08-15 20:51:32 +0000	[diff] [blame]	1694	break;
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1695	default:
				1696	break;
Owen Anderson	1d5d2ca	2011-08-15 20:51:32 +0000	[diff] [blame]	1697	}
				1698
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1699	if (writeback) { // Writeback
				1700	if (P)
				1701	U \|= ARMII::IndexModePre << 9;
				1702	else
				1703	U \|= ARMII::IndexModePost << 9;
				1704
				1705	// On stores, the writeback operand precedes Rt.
				1706	switch (Inst.getOpcode()) {
				1707	case ARM::STRD:
				1708	case ARM::STRD_PRE:
				1709	case ARM::STRD_POST:
Owen Anderson	60138ea	2011-08-12 20:02:50 +0000	[diff] [blame]	1710	case ARM::STRH:
				1711	case ARM::STRH_PRE:
				1712	case ARM::STRH_POST:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1713	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1714	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1715	break;
				1716	default:
				1717	break;
				1718	}
				1719	}
				1720
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1721	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				1722	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1723	switch (Inst.getOpcode()) {
				1724	case ARM::STRD:
				1725	case ARM::STRD_PRE:
				1726	case ARM::STRD_POST:
				1727	case ARM::LDRD:
				1728	case ARM::LDRD_PRE:
				1729	case ARM::LDRD_POST:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1730	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
				1731	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1732	break;
				1733	default:
				1734	break;
				1735	}
				1736
				1737	if (writeback) {
				1738	// On loads, the writeback operand comes after Rt.
				1739	switch (Inst.getOpcode()) {
				1740	case ARM::LDRD:
				1741	case ARM::LDRD_PRE:
				1742	case ARM::LDRD_POST:
Owen Anderson	2d1d7a1	2011-08-12 20:36:11 +0000	[diff] [blame]	1743	case ARM::LDRH:
				1744	case ARM::LDRH_PRE:
				1745	case ARM::LDRH_POST:
				1746	case ARM::LDRSH:
				1747	case ARM::LDRSH_PRE:
				1748	case ARM::LDRSH_POST:
				1749	case ARM::LDRSB:
				1750	case ARM::LDRSB_PRE:
				1751	case ARM::LDRSB_POST:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1752	case ARM::LDRHTr:
				1753	case ARM::LDRSBTr:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1754	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1755	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1756	break;
				1757	default:
				1758	break;
				1759	}
				1760	}
				1761
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1762	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1763	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1764
				1765	if (type) {
				1766	Inst.addOperand(MCOperand::CreateReg(0));
				1767	Inst.addOperand(MCOperand::CreateImm(U \| (imm << 4) \| Rm));
				1768	} else {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1769	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1770	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1771	Inst.addOperand(MCOperand::CreateImm(U));
				1772	}
				1773
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1774	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1775	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1776
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1777	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1778	}
				1779
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1780	static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1781	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1782	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1783
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1784	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1785	unsigned mode = fieldFromInstruction(Insn, 23, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1786
				1787	switch (mode) {
				1788	case 0:
				1789	mode = ARM_AM::da;
				1790	break;
				1791	case 1:
				1792	mode = ARM_AM::ia;
				1793	break;
				1794	case 2:
				1795	mode = ARM_AM::db;
				1796	break;
				1797	case 3:
				1798	mode = ARM_AM::ib;
				1799	break;
				1800	}
				1801
				1802	Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1803	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1804	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1805
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1806	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1807	}
				1808
Amaury de la Vieuville	631df63	2013-06-08 13:38:52 +0000	[diff] [blame]	1809	static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
				1810	uint64_t Address, const void *Decoder) {
				1811	DecodeStatus S = MCDisassembler::Success;
				1812
				1813	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				1814	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				1815	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1816	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1817
				1818	if (pred == 0xF)
				1819	return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
				1820
				1821	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
				1822	return MCDisassembler::Fail;
				1823	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1824	return MCDisassembler::Fail;
				1825	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				1826	return MCDisassembler::Fail;
				1827	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1828	return MCDisassembler::Fail;
				1829	return S;
				1830	}
				1831
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1832	static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1833	unsigned Insn,
				1834	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1835	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1836
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1837	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1838	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1839	unsigned reglist = fieldFromInstruction(Insn, 0, 16);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1840
				1841	if (pred == 0xF) {
Amaury de la Vieuville	68bcd02	2013-06-08 13:43:59 +0000	[diff] [blame]	1842	// Ambiguous with RFE and SRS
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1843	switch (Inst.getOpcode()) {
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1844	case ARM::LDMDA:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1845	Inst.setOpcode(ARM::RFEDA);
				1846	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1847	case ARM::LDMDA_UPD:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1848	Inst.setOpcode(ARM::RFEDA_UPD);
				1849	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1850	case ARM::LDMDB:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1851	Inst.setOpcode(ARM::RFEDB);
				1852	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1853	case ARM::LDMDB_UPD:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1854	Inst.setOpcode(ARM::RFEDB_UPD);
				1855	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1856	case ARM::LDMIA:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1857	Inst.setOpcode(ARM::RFEIA);
				1858	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1859	case ARM::LDMIA_UPD:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1860	Inst.setOpcode(ARM::RFEIA_UPD);
				1861	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1862	case ARM::LDMIB:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1863	Inst.setOpcode(ARM::RFEIB);
				1864	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1865	case ARM::LDMIB_UPD:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1866	Inst.setOpcode(ARM::RFEIB_UPD);
				1867	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1868	case ARM::STMDA:
				1869	Inst.setOpcode(ARM::SRSDA);
				1870	break;
				1871	case ARM::STMDA_UPD:
				1872	Inst.setOpcode(ARM::SRSDA_UPD);
				1873	break;
				1874	case ARM::STMDB:
				1875	Inst.setOpcode(ARM::SRSDB);
				1876	break;
				1877	case ARM::STMDB_UPD:
				1878	Inst.setOpcode(ARM::SRSDB_UPD);
				1879	break;
				1880	case ARM::STMIA:
				1881	Inst.setOpcode(ARM::SRSIA);
				1882	break;
				1883	case ARM::STMIA_UPD:
				1884	Inst.setOpcode(ARM::SRSIA_UPD);
				1885	break;
				1886	case ARM::STMIB:
				1887	Inst.setOpcode(ARM::SRSIB);
				1888	break;
				1889	case ARM::STMIB_UPD:
				1890	Inst.setOpcode(ARM::SRSIB_UPD);
				1891	break;
				1892	default:
Amaury de la Vieuville	68bcd02	2013-06-08 13:43:59 +0000	[diff] [blame]	1893	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1894	}
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1895
				1896	// For stores (which become SRS's, the only operand is the mode.
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1897	if (fieldFromInstruction(Insn, 20, 1) == 0) {
Amaury de la Vieuville	68bcd02	2013-06-08 13:43:59 +0000	[diff] [blame]	1898	// Check SRS encoding constraints
				1899	if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
				1900	fieldFromInstruction(Insn, 20, 1) == 0))
				1901	return MCDisassembler::Fail;
				1902
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1903	Inst.addOperand(
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1904	MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4)));
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1905	return S;
				1906	}
				1907
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1908	return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
				1909	}
				1910
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1911	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1912	return MCDisassembler::Fail;
				1913	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1914	return MCDisassembler::Fail; // Tied
				1915	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1916	return MCDisassembler::Fail;
				1917	if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
				1918	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1919
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1920	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1921	}
				1922
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1923	static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1924	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1925	unsigned imod = fieldFromInstruction(Insn, 18, 2);
				1926	unsigned M = fieldFromInstruction(Insn, 17, 1);
				1927	unsigned iflags = fieldFromInstruction(Insn, 6, 3);
				1928	unsigned mode = fieldFromInstruction(Insn, 0, 5);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1929
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1930	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	3d2e0e9d	2011-08-09 23:05:39 +0000	[diff] [blame]	1931
Amaury de la Vieuville	631df63	2013-06-08 13:38:52 +0000	[diff] [blame]	1932	// This decoder is called from multiple location that do not check
				1933	// the full encoding is valid before they do.
				1934	if (fieldFromInstruction(Insn, 5, 1) != 0 \|\|
				1935	fieldFromInstruction(Insn, 16, 1) != 0 \|\|
				1936	fieldFromInstruction(Insn, 20, 8) != 0x10)
				1937	return MCDisassembler::Fail;
				1938
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1939	// imod == '01' --> UNPREDICTABLE
				1940	// NOTE: Even though this is technically UNPREDICTABLE, we choose to
				1941	// return failure here. The '01' imod value is unprintable, so there's
				1942	// nothing useful we could do even if we returned UNPREDICTABLE.
				1943
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1944	if (imod == 1) return MCDisassembler::Fail;
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1945
				1946	if (imod && M) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1947	Inst.setOpcode(ARM::CPS3p);
				1948	Inst.addOperand(MCOperand::CreateImm(imod));
				1949	Inst.addOperand(MCOperand::CreateImm(iflags));
				1950	Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1951	} else if (imod && !M) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1952	Inst.setOpcode(ARM::CPS2p);
				1953	Inst.addOperand(MCOperand::CreateImm(imod));
				1954	Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1955	if (mode) S = MCDisassembler::SoftFail;
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1956	} else if (!imod && M) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1957	Inst.setOpcode(ARM::CPS1p);
				1958	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1959	if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson	5d2db89	2011-08-18 22:15:25 +0000	[diff] [blame]	1960	} else {
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1961	// imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson	5d2db89	2011-08-18 22:15:25 +0000	[diff] [blame]	1962	Inst.setOpcode(ARM::CPS1p);
				1963	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1964	S = MCDisassembler::SoftFail;
Owen Anderson	5d2db89	2011-08-18 22:15:25 +0000	[diff] [blame]	1965	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1966
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1967	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1968	}
				1969
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1970	static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	1971	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1972	unsigned imod = fieldFromInstruction(Insn, 9, 2);
				1973	unsigned M = fieldFromInstruction(Insn, 8, 1);
				1974	unsigned iflags = fieldFromInstruction(Insn, 5, 3);
				1975	unsigned mode = fieldFromInstruction(Insn, 0, 5);
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	1976
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1977	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	1978
				1979	// imod == '01' --> UNPREDICTABLE
				1980	// NOTE: Even though this is technically UNPREDICTABLE, we choose to
				1981	// return failure here. The '01' imod value is unprintable, so there's
				1982	// nothing useful we could do even if we returned UNPREDICTABLE.
				1983
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1984	if (imod == 1) return MCDisassembler::Fail;
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	1985
				1986	if (imod && M) {
				1987	Inst.setOpcode(ARM::t2CPS3p);
				1988	Inst.addOperand(MCOperand::CreateImm(imod));
				1989	Inst.addOperand(MCOperand::CreateImm(iflags));
				1990	Inst.addOperand(MCOperand::CreateImm(mode));
				1991	} else if (imod && !M) {
				1992	Inst.setOpcode(ARM::t2CPS2p);
				1993	Inst.addOperand(MCOperand::CreateImm(imod));
				1994	Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1995	if (mode) S = MCDisassembler::SoftFail;
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	1996	} else if (!imod && M) {
				1997	Inst.setOpcode(ARM::t2CPS1p);
				1998	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1999	if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2000	} else {
Quentin Colombet	a83d5e9	2013-04-26 17:54:54 +0000	[diff] [blame]	2001	// imod == '00' && M == '0' --> this is a HINT instruction
				2002	int imm = fieldFromInstruction(Insn, 0, 8);
				2003	// HINT are defined only for immediate in [0..4]
				2004	if(imm > 4) return MCDisassembler::Fail;
				2005	Inst.setOpcode(ARM::t2HINT);
				2006	Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2007	}
				2008
				2009	return S;
				2010	}
				2011
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2012	static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2013	uint64_t Address, const void *Decoder) {
				2014	DecodeStatus S = MCDisassembler::Success;
				2015
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2016	unsigned Rd = fieldFromInstruction(Insn, 8, 4);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2017	unsigned imm = 0;
				2018
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2019	imm \|= (fieldFromInstruction(Insn, 0, 8) << 0);
				2020	imm \|= (fieldFromInstruction(Insn, 12, 3) << 8);
				2021	imm \|= (fieldFromInstruction(Insn, 16, 4) << 12);
				2022	imm \|= (fieldFromInstruction(Insn, 26, 1) << 11);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2023
				2024	if (Inst.getOpcode() == ARM::t2MOVTi16)
				2025	if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
				2026	return MCDisassembler::Fail;
				2027	if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
				2028	return MCDisassembler::Fail;
				2029
				2030	if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
				2031	Inst.addOperand(MCOperand::CreateImm(imm));
				2032
				2033	return S;
				2034	}
				2035
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2036	static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2037	uint64_t Address, const void *Decoder) {
				2038	DecodeStatus S = MCDisassembler::Success;
				2039
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2040	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2041	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2042	unsigned imm = 0;
				2043
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2044	imm \|= (fieldFromInstruction(Insn, 0, 12) << 0);
				2045	imm \|= (fieldFromInstruction(Insn, 16, 4) << 12);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2046
				2047	if (Inst.getOpcode() == ARM::MOVTi16)
Tim Northover	a155ab2	2013-04-19 09:58:09 +0000	[diff] [blame]	2048	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2049	return MCDisassembler::Fail;
Tim Northover	a155ab2	2013-04-19 09:58:09 +0000	[diff] [blame]	2050
				2051	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2052	return MCDisassembler::Fail;
				2053
				2054	if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
				2055	Inst.addOperand(MCOperand::CreateImm(imm));
				2056
				2057	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2058	return MCDisassembler::Fail;
				2059
				2060	return S;
				2061	}
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2062
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2063	static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2064	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2065	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2066
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2067	unsigned Rd = fieldFromInstruction(Insn, 16, 4);
				2068	unsigned Rn = fieldFromInstruction(Insn, 0, 4);
				2069	unsigned Rm = fieldFromInstruction(Insn, 8, 4);
				2070	unsigned Ra = fieldFromInstruction(Insn, 12, 4);
				2071	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2072
				2073	if (pred == 0xF)
				2074	return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
				2075
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2076	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
				2077	return MCDisassembler::Fail;
				2078	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				2079	return MCDisassembler::Fail;
				2080	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				2081	return MCDisassembler::Fail;
				2082	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
				2083	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2084
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2085	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2086	return MCDisassembler::Fail;
Owen Anderson	2f7aa73	2011-08-11 22:05:38 +0000	[diff] [blame]	2087
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2088	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2089	}
				2090
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2091	static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2092	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2093	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2094
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2095	unsigned add = fieldFromInstruction(Val, 12, 1);
				2096	unsigned imm = fieldFromInstruction(Val, 0, 12);
				2097	unsigned Rn = fieldFromInstruction(Val, 13, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2098
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2099	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2100	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2101
				2102	if (!add) imm *= -1;
				2103	if (imm == 0 && !add) imm = INT32_MIN;
				2104	Inst.addOperand(MCOperand::CreateImm(imm));
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2105	if (Rn == 15)
				2106	tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2107
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2108	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2109	}
				2110
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2111	static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2112	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2113	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2114
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2115	unsigned Rn = fieldFromInstruction(Val, 9, 4);
				2116	unsigned U = fieldFromInstruction(Val, 8, 1);
				2117	unsigned imm = fieldFromInstruction(Val, 0, 8);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2118
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2119	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2120	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2121
				2122	if (U)
				2123	Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
				2124	else
				2125	Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
				2126
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2127	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2128	}
				2129
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2130	static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2131	uint64_t Address, const void *Decoder) {
				2132	return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
				2133	}
				2134
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2135	static DecodeStatus
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	2136	DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
				2137	uint64_t Address, const void *Decoder) {
Kevin Enderby	6fd9624	2012-10-29 23:27:20 +0000	[diff] [blame]	2138	DecodeStatus Status = MCDisassembler::Success;
				2139
				2140	// Note the J1 and J2 values are from the encoded instruction. So here
				2141	// change them to I1 and I2 values via as documented:
				2142	// I1 = NOT(J1 EOR S);
				2143	// I2 = NOT(J2 EOR S);
				2144	// and build the imm32 with one trailing zero as documented:
				2145	// imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
				2146	unsigned S = fieldFromInstruction(Insn, 26, 1);
				2147	unsigned J1 = fieldFromInstruction(Insn, 13, 1);
				2148	unsigned J2 = fieldFromInstruction(Insn, 11, 1);
				2149	unsigned I1 = !(J1 ^ S);
				2150	unsigned I2 = !(J2 ^ S);
				2151	unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
				2152	unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
				2153	unsigned tmp = (S << 23) \| (I1 << 22) \| (I2 << 21) \| (imm10 << 11) \| imm11;
Amaury de la Vieuville	bd2b610	2013-06-13 16:41:55 +0000	[diff] [blame]	2154	int imm32 = SignExtend32<25>(tmp << 1);
Kevin Enderby	6fd9624	2012-10-29 23:27:20 +0000	[diff] [blame]	2155	if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	2156	true, 4, Inst, Decoder))
Kevin Enderby	6fd9624	2012-10-29 23:27:20 +0000	[diff] [blame]	2157	Inst.addOperand(MCOperand::CreateImm(imm32));
				2158
				2159	return Status;
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	2160	}
				2161
				2162	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2163	DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	2164	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2165	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2166
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2167	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				2168	unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2169
				2170	if (pred == 0xF) {
				2171	Inst.setOpcode(ARM::BLXi);
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2172	imm \|= fieldFromInstruction(Insn, 24, 1) << 1;
Kevin Enderby	6fbcd8d	2012-02-23 18:18:17 +0000	[diff] [blame]	2173	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
				2174	true, 4, Inst, Decoder))
Benjamin Kramer	406dc17	2011-08-09 22:02:50 +0000	[diff] [blame]	2175	Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2176	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2177	}
				2178
Kevin Enderby	6fbcd8d	2012-02-23 18:18:17 +0000	[diff] [blame]	2179	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
				2180	true, 4, Inst, Decoder))
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2181	Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2182	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2183	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2184
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2185	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2186	}
				2187
				2188
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2189	static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2190	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2191	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2192
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2193	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				2194	unsigned align = fieldFromInstruction(Val, 4, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2195
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2196	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2197	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2198	if (!align)
				2199	Inst.addOperand(MCOperand::CreateImm(0));
				2200	else
				2201	Inst.addOperand(MCOperand::CreateImm(4 << align));
				2202
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2203	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2204	}
				2205
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2206	static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2207	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2208	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2209
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2210	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2211	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2212	unsigned wb = fieldFromInstruction(Insn, 16, 4);
				2213	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2214	Rn \|= fieldFromInstruction(Insn, 4, 2) << 4;
				2215	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2216
				2217	// First output register
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2218	switch (Inst.getOpcode()) {
Jim Grosbach	13a292c	2012-03-06 22:01:44 +0000	[diff] [blame]	2219	case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
				2220	case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
				2221	case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
				2222	case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
				2223	case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
				2224	case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
				2225	case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
				2226	case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
				2227	case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2228	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2229	return MCDisassembler::Fail;
				2230	break;
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	2231	case ARM::VLD2b16:
				2232	case ARM::VLD2b32:
				2233	case ARM::VLD2b8:
				2234	case ARM::VLD2b16wb_fixed:
				2235	case ARM::VLD2b16wb_register:
				2236	case ARM::VLD2b32wb_fixed:
				2237	case ARM::VLD2b32wb_register:
				2238	case ARM::VLD2b8wb_fixed:
				2239	case ARM::VLD2b8wb_register:
				2240	if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
				2241	return MCDisassembler::Fail;
				2242	break;
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2243	default:
				2244	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2245	return MCDisassembler::Fail;
				2246	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2247
				2248	// Second output register
				2249	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2250	case ARM::VLD3d8:
				2251	case ARM::VLD3d16:
				2252	case ARM::VLD3d32:
				2253	case ARM::VLD3d8_UPD:
				2254	case ARM::VLD3d16_UPD:
				2255	case ARM::VLD3d32_UPD:
				2256	case ARM::VLD4d8:
				2257	case ARM::VLD4d16:
				2258	case ARM::VLD4d32:
				2259	case ARM::VLD4d8_UPD:
				2260	case ARM::VLD4d16_UPD:
				2261	case ARM::VLD4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2262	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
				2263	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2264	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2265	case ARM::VLD3q8:
				2266	case ARM::VLD3q16:
				2267	case ARM::VLD3q32:
				2268	case ARM::VLD3q8_UPD:
				2269	case ARM::VLD3q16_UPD:
				2270	case ARM::VLD3q32_UPD:
				2271	case ARM::VLD4q8:
				2272	case ARM::VLD4q16:
				2273	case ARM::VLD4q32:
				2274	case ARM::VLD4q8_UPD:
				2275	case ARM::VLD4q16_UPD:
				2276	case ARM::VLD4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2277	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2278	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2279	default:
				2280	break;
				2281	}
				2282
				2283	// Third output register
				2284	switch(Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2285	case ARM::VLD3d8:
				2286	case ARM::VLD3d16:
				2287	case ARM::VLD3d32:
				2288	case ARM::VLD3d8_UPD:
				2289	case ARM::VLD3d16_UPD:
				2290	case ARM::VLD3d32_UPD:
				2291	case ARM::VLD4d8:
				2292	case ARM::VLD4d16:
				2293	case ARM::VLD4d32:
				2294	case ARM::VLD4d8_UPD:
				2295	case ARM::VLD4d16_UPD:
				2296	case ARM::VLD4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2297	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2298	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2299	break;
				2300	case ARM::VLD3q8:
				2301	case ARM::VLD3q16:
				2302	case ARM::VLD3q32:
				2303	case ARM::VLD3q8_UPD:
				2304	case ARM::VLD3q16_UPD:
				2305	case ARM::VLD3q32_UPD:
				2306	case ARM::VLD4q8:
				2307	case ARM::VLD4q16:
				2308	case ARM::VLD4q32:
				2309	case ARM::VLD4q8_UPD:
				2310	case ARM::VLD4q16_UPD:
				2311	case ARM::VLD4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2312	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
				2313	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2314	break;
				2315	default:
				2316	break;
				2317	}
				2318
				2319	// Fourth output register
				2320	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2321	case ARM::VLD4d8:
				2322	case ARM::VLD4d16:
				2323	case ARM::VLD4d32:
				2324	case ARM::VLD4d8_UPD:
				2325	case ARM::VLD4d16_UPD:
				2326	case ARM::VLD4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2327	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
				2328	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2329	break;
				2330	case ARM::VLD4q8:
				2331	case ARM::VLD4q16:
				2332	case ARM::VLD4q32:
				2333	case ARM::VLD4q8_UPD:
				2334	case ARM::VLD4q16_UPD:
				2335	case ARM::VLD4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2336	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
				2337	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2338	break;
				2339	default:
				2340	break;
				2341	}
				2342
				2343	// Writeback operand
				2344	switch (Inst.getOpcode()) {
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2345	case ARM::VLD1d8wb_fixed:
				2346	case ARM::VLD1d16wb_fixed:
				2347	case ARM::VLD1d32wb_fixed:
				2348	case ARM::VLD1d64wb_fixed:
				2349	case ARM::VLD1d8wb_register:
				2350	case ARM::VLD1d16wb_register:
				2351	case ARM::VLD1d32wb_register:
				2352	case ARM::VLD1d64wb_register:
				2353	case ARM::VLD1q8wb_fixed:
				2354	case ARM::VLD1q16wb_fixed:
				2355	case ARM::VLD1q32wb_fixed:
				2356	case ARM::VLD1q64wb_fixed:
				2357	case ARM::VLD1q8wb_register:
				2358	case ARM::VLD1q16wb_register:
				2359	case ARM::VLD1q32wb_register:
				2360	case ARM::VLD1q64wb_register:
Jim Grosbach	92fd05e	2011-10-24 23:26:05 +0000	[diff] [blame]	2361	case ARM::VLD1d8Twb_fixed:
				2362	case ARM::VLD1d8Twb_register:
				2363	case ARM::VLD1d16Twb_fixed:
				2364	case ARM::VLD1d16Twb_register:
				2365	case ARM::VLD1d32Twb_fixed:
				2366	case ARM::VLD1d32Twb_register:
				2367	case ARM::VLD1d64Twb_fixed:
				2368	case ARM::VLD1d64Twb_register:
Jim Grosbach	17ec1a1	2011-10-25 00:14:01 +0000	[diff] [blame]	2369	case ARM::VLD1d8Qwb_fixed:
				2370	case ARM::VLD1d8Qwb_register:
				2371	case ARM::VLD1d16Qwb_fixed:
				2372	case ARM::VLD1d16Qwb_register:
				2373	case ARM::VLD1d32Qwb_fixed:
				2374	case ARM::VLD1d32Qwb_register:
				2375	case ARM::VLD1d64Qwb_fixed:
				2376	case ARM::VLD1d64Qwb_register:
Jim Grosbach	d146a02	2011-12-09 21:28:25 +0000	[diff] [blame]	2377	case ARM::VLD2d8wb_fixed:
				2378	case ARM::VLD2d16wb_fixed:
				2379	case ARM::VLD2d32wb_fixed:
				2380	case ARM::VLD2q8wb_fixed:
				2381	case ARM::VLD2q16wb_fixed:
				2382	case ARM::VLD2q32wb_fixed:
				2383	case ARM::VLD2d8wb_register:
				2384	case ARM::VLD2d16wb_register:
				2385	case ARM::VLD2d32wb_register:
				2386	case ARM::VLD2q8wb_register:
				2387	case ARM::VLD2q16wb_register:
				2388	case ARM::VLD2q32wb_register:
				2389	case ARM::VLD2b8wb_fixed:
				2390	case ARM::VLD2b16wb_fixed:
				2391	case ARM::VLD2b32wb_fixed:
				2392	case ARM::VLD2b8wb_register:
				2393	case ARM::VLD2b16wb_register:
				2394	case ARM::VLD2b32wb_register:
Kevin Enderby	d2980cd	2012-04-11 00:25:40 +0000	[diff] [blame]	2395	Inst.addOperand(MCOperand::CreateImm(0));
				2396	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2397	case ARM::VLD3d8_UPD:
				2398	case ARM::VLD3d16_UPD:
				2399	case ARM::VLD3d32_UPD:
				2400	case ARM::VLD3q8_UPD:
				2401	case ARM::VLD3q16_UPD:
				2402	case ARM::VLD3q32_UPD:
				2403	case ARM::VLD4d8_UPD:
				2404	case ARM::VLD4d16_UPD:
				2405	case ARM::VLD4d32_UPD:
				2406	case ARM::VLD4q8_UPD:
				2407	case ARM::VLD4q16_UPD:
				2408	case ARM::VLD4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2409	if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
				2410	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2411	break;
				2412	default:
				2413	break;
				2414	}
				2415
				2416	// AddrMode6 Base (register+alignment)
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2417	if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
				2418	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2419
				2420	// AddrMode6 Offset (register)
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2421	switch (Inst.getOpcode()) {
				2422	default:
				2423	// The below have been updated to have explicit am6offset split
				2424	// between fixed and register offset. For those instructions not
				2425	// yet updated, we need to add an additional reg0 operand for the
				2426	// fixed variant.
				2427	//
				2428	// The fixed offset encodes as Rm == 0xd, so we check for that.
				2429	if (Rm == 0xd) {
				2430	Inst.addOperand(MCOperand::CreateReg(0));
				2431	break;
				2432	}
				2433	// Fall through to handle the register offset variant.
				2434	case ARM::VLD1d8wb_fixed:
				2435	case ARM::VLD1d16wb_fixed:
				2436	case ARM::VLD1d32wb_fixed:
				2437	case ARM::VLD1d64wb_fixed:
Owen Anderson	8a6ebd0	2011-10-27 22:53:10 +0000	[diff] [blame]	2438	case ARM::VLD1d8Twb_fixed:
				2439	case ARM::VLD1d16Twb_fixed:
				2440	case ARM::VLD1d32Twb_fixed:
				2441	case ARM::VLD1d64Twb_fixed:
Owen Anderson	40703f4	2011-10-31 17:17:32 +0000	[diff] [blame]	2442	case ARM::VLD1d8Qwb_fixed:
				2443	case ARM::VLD1d16Qwb_fixed:
				2444	case ARM::VLD1d32Qwb_fixed:
				2445	case ARM::VLD1d64Qwb_fixed:
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2446	case ARM::VLD1d8wb_register:
				2447	case ARM::VLD1d16wb_register:
				2448	case ARM::VLD1d32wb_register:
				2449	case ARM::VLD1d64wb_register:
				2450	case ARM::VLD1q8wb_fixed:
				2451	case ARM::VLD1q16wb_fixed:
				2452	case ARM::VLD1q32wb_fixed:
				2453	case ARM::VLD1q64wb_fixed:
				2454	case ARM::VLD1q8wb_register:
				2455	case ARM::VLD1q16wb_register:
				2456	case ARM::VLD1q32wb_register:
				2457	case ARM::VLD1q64wb_register:
				2458	// The fixed offset post-increment encodes Rm == 0xd. The no-writeback
				2459	// variant encodes Rm == 0xf. Anything else is a register offset post-
				2460	// increment and we need to add the register operand to the instruction.
				2461	if (Rm != 0xD && Rm != 0xF &&
				2462	!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2463	return MCDisassembler::Fail;
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2464	break;
Kevin Enderby	d2980cd	2012-04-11 00:25:40 +0000	[diff] [blame]	2465	case ARM::VLD2d8wb_fixed:
				2466	case ARM::VLD2d16wb_fixed:
				2467	case ARM::VLD2d32wb_fixed:
				2468	case ARM::VLD2b8wb_fixed:
				2469	case ARM::VLD2b16wb_fixed:
				2470	case ARM::VLD2b32wb_fixed:
				2471	case ARM::VLD2q8wb_fixed:
				2472	case ARM::VLD2q16wb_fixed:
				2473	case ARM::VLD2q32wb_fixed:
				2474	break;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2475	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2476
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2477	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2478	}
				2479
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2480	static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
				2481	uint64_t Address, const void *Decoder) {
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2482	unsigned type = fieldFromInstruction(Insn, 8, 4);
				2483	unsigned align = fieldFromInstruction(Insn, 4, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2484	if (type == 6 && (align & 2)) return MCDisassembler::Fail;
				2485	if (type == 7 && (align & 2)) return MCDisassembler::Fail;
				2486	if (type == 10 && align == 3) return MCDisassembler::Fail;
				2487
				2488	unsigned load = fieldFromInstruction(Insn, 21, 1);
				2489	return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
				2490	: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2491	}
				2492
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2493	static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
				2494	uint64_t Address, const void *Decoder) {
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2495	unsigned size = fieldFromInstruction(Insn, 6, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2496	if (size == 3) return MCDisassembler::Fail;
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2497
				2498	unsigned type = fieldFromInstruction(Insn, 8, 4);
				2499	unsigned align = fieldFromInstruction(Insn, 4, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2500	if (type == 8 && align == 3) return MCDisassembler::Fail;
				2501	if (type == 9 && align == 3) return MCDisassembler::Fail;
				2502
				2503	unsigned load = fieldFromInstruction(Insn, 21, 1);
				2504	return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
				2505	: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2506	}
				2507
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2508	static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
				2509	uint64_t Address, const void *Decoder) {
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2510	unsigned size = fieldFromInstruction(Insn, 6, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2511	if (size == 3) return MCDisassembler::Fail;
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2512
				2513	unsigned align = fieldFromInstruction(Insn, 4, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2514	if (align & 2) return MCDisassembler::Fail;
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2515
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2516	unsigned load = fieldFromInstruction(Insn, 21, 1);
				2517	return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
				2518	: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2519	}
				2520
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2521	static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
				2522	uint64_t Address, const void *Decoder) {
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2523	unsigned size = fieldFromInstruction(Insn, 6, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2524	if (size == 3) return MCDisassembler::Fail;
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2525
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2526	unsigned load = fieldFromInstruction(Insn, 21, 1);
				2527	return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
				2528	: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2529	}
				2530
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2531	static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2532	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2533	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2534
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2535	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2536	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2537	unsigned wb = fieldFromInstruction(Insn, 16, 4);
				2538	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2539	Rn \|= fieldFromInstruction(Insn, 4, 2) << 4;
				2540	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2541
				2542	// Writeback Operand
				2543	switch (Inst.getOpcode()) {
Jim Grosbach	05df460	2011-10-31 21:50:31 +0000	[diff] [blame]	2544	case ARM::VST1d8wb_fixed:
				2545	case ARM::VST1d16wb_fixed:
				2546	case ARM::VST1d32wb_fixed:
				2547	case ARM::VST1d64wb_fixed:
				2548	case ARM::VST1d8wb_register:
				2549	case ARM::VST1d16wb_register:
				2550	case ARM::VST1d32wb_register:
				2551	case ARM::VST1d64wb_register:
				2552	case ARM::VST1q8wb_fixed:
				2553	case ARM::VST1q16wb_fixed:
				2554	case ARM::VST1q32wb_fixed:
				2555	case ARM::VST1q64wb_fixed:
				2556	case ARM::VST1q8wb_register:
				2557	case ARM::VST1q16wb_register:
				2558	case ARM::VST1q32wb_register:
				2559	case ARM::VST1q64wb_register:
Jim Grosbach	98d032f	2011-11-29 22:38:04 +0000	[diff] [blame]	2560	case ARM::VST1d8Twb_fixed:
				2561	case ARM::VST1d16Twb_fixed:
				2562	case ARM::VST1d32Twb_fixed:
				2563	case ARM::VST1d64Twb_fixed:
				2564	case ARM::VST1d8Twb_register:
				2565	case ARM::VST1d16Twb_register:
				2566	case ARM::VST1d32Twb_register:
				2567	case ARM::VST1d64Twb_register:
Jim Grosbach	5ee209c	2011-11-29 22:58:48 +0000	[diff] [blame]	2568	case ARM::VST1d8Qwb_fixed:
				2569	case ARM::VST1d16Qwb_fixed:
				2570	case ARM::VST1d32Qwb_fixed:
				2571	case ARM::VST1d64Qwb_fixed:
				2572	case ARM::VST1d8Qwb_register:
				2573	case ARM::VST1d16Qwb_register:
				2574	case ARM::VST1d32Qwb_register:
				2575	case ARM::VST1d64Qwb_register:
Jim Grosbach	88ac761	2011-12-14 21:32:11 +0000	[diff] [blame]	2576	case ARM::VST2d8wb_fixed:
				2577	case ARM::VST2d16wb_fixed:
				2578	case ARM::VST2d32wb_fixed:
				2579	case ARM::VST2d8wb_register:
				2580	case ARM::VST2d16wb_register:
				2581	case ARM::VST2d32wb_register:
				2582	case ARM::VST2q8wb_fixed:
				2583	case ARM::VST2q16wb_fixed:
				2584	case ARM::VST2q32wb_fixed:
				2585	case ARM::VST2q8wb_register:
				2586	case ARM::VST2q16wb_register:
				2587	case ARM::VST2q32wb_register:
				2588	case ARM::VST2b8wb_fixed:
				2589	case ARM::VST2b16wb_fixed:
				2590	case ARM::VST2b32wb_fixed:
				2591	case ARM::VST2b8wb_register:
				2592	case ARM::VST2b16wb_register:
				2593	case ARM::VST2b32wb_register:
Kevin Enderby	72f18bb	2012-04-11 22:40:17 +0000	[diff] [blame]	2594	if (Rm == 0xF)
				2595	return MCDisassembler::Fail;
Kevin Enderby	7e7d5ee	2012-03-21 20:54:32 +0000	[diff] [blame]	2596	Inst.addOperand(MCOperand::CreateImm(0));
				2597	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2598	case ARM::VST3d8_UPD:
				2599	case ARM::VST3d16_UPD:
				2600	case ARM::VST3d32_UPD:
				2601	case ARM::VST3q8_UPD:
				2602	case ARM::VST3q16_UPD:
				2603	case ARM::VST3q32_UPD:
				2604	case ARM::VST4d8_UPD:
				2605	case ARM::VST4d16_UPD:
				2606	case ARM::VST4d32_UPD:
				2607	case ARM::VST4q8_UPD:
				2608	case ARM::VST4q16_UPD:
				2609	case ARM::VST4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2610	if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
				2611	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2612	break;
				2613	default:
				2614	break;
				2615	}
				2616
				2617	// AddrMode6 Base (register+alignment)
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2618	if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
				2619	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2620
				2621	// AddrMode6 Offset (register)
Owen Anderson	69e54a7	2011-11-01 22:18:13 +0000	[diff] [blame]	2622	switch (Inst.getOpcode()) {
				2623	default:
				2624	if (Rm == 0xD)
				2625	Inst.addOperand(MCOperand::CreateReg(0));
				2626	else if (Rm != 0xF) {
				2627	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2628	return MCDisassembler::Fail;
				2629	}
				2630	break;
				2631	case ARM::VST1d8wb_fixed:
				2632	case ARM::VST1d16wb_fixed:
				2633	case ARM::VST1d32wb_fixed:
				2634	case ARM::VST1d64wb_fixed:
				2635	case ARM::VST1q8wb_fixed:
				2636	case ARM::VST1q16wb_fixed:
				2637	case ARM::VST1q32wb_fixed:
				2638	case ARM::VST1q64wb_fixed:
Kevin Enderby	7e7d5ee	2012-03-21 20:54:32 +0000	[diff] [blame]	2639	case ARM::VST1d8Twb_fixed:
				2640	case ARM::VST1d16Twb_fixed:
				2641	case ARM::VST1d32Twb_fixed:
				2642	case ARM::VST1d64Twb_fixed:
				2643	case ARM::VST1d8Qwb_fixed:
				2644	case ARM::VST1d16Qwb_fixed:
				2645	case ARM::VST1d32Qwb_fixed:
				2646	case ARM::VST1d64Qwb_fixed:
				2647	case ARM::VST2d8wb_fixed:
				2648	case ARM::VST2d16wb_fixed:
				2649	case ARM::VST2d32wb_fixed:
				2650	case ARM::VST2q8wb_fixed:
				2651	case ARM::VST2q16wb_fixed:
				2652	case ARM::VST2q32wb_fixed:
				2653	case ARM::VST2b8wb_fixed:
				2654	case ARM::VST2b16wb_fixed:
				2655	case ARM::VST2b32wb_fixed:
Owen Anderson	69e54a7	2011-11-01 22:18:13 +0000	[diff] [blame]	2656	break;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2657	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2658
Owen Anderson	69e54a7	2011-11-01 22:18:13 +0000	[diff] [blame]	2659
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2660	// First input register
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2661	switch (Inst.getOpcode()) {
				2662	case ARM::VST1q16:
				2663	case ARM::VST1q32:
				2664	case ARM::VST1q64:
				2665	case ARM::VST1q8:
				2666	case ARM::VST1q16wb_fixed:
				2667	case ARM::VST1q16wb_register:
				2668	case ARM::VST1q32wb_fixed:
				2669	case ARM::VST1q32wb_register:
				2670	case ARM::VST1q64wb_fixed:
				2671	case ARM::VST1q64wb_register:
				2672	case ARM::VST1q8wb_fixed:
				2673	case ARM::VST1q8wb_register:
				2674	case ARM::VST2d16:
				2675	case ARM::VST2d32:
				2676	case ARM::VST2d8:
				2677	case ARM::VST2d16wb_fixed:
				2678	case ARM::VST2d16wb_register:
				2679	case ARM::VST2d32wb_fixed:
				2680	case ARM::VST2d32wb_register:
				2681	case ARM::VST2d8wb_fixed:
				2682	case ARM::VST2d8wb_register:
				2683	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2684	return MCDisassembler::Fail;
				2685	break;
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	2686	case ARM::VST2b16:
				2687	case ARM::VST2b32:
				2688	case ARM::VST2b8:
				2689	case ARM::VST2b16wb_fixed:
				2690	case ARM::VST2b16wb_register:
				2691	case ARM::VST2b32wb_fixed:
				2692	case ARM::VST2b32wb_register:
				2693	case ARM::VST2b8wb_fixed:
				2694	case ARM::VST2b8wb_register:
				2695	if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
				2696	return MCDisassembler::Fail;
				2697	break;
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2698	default:
				2699	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2700	return MCDisassembler::Fail;
				2701	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2702
				2703	// Second input register
				2704	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2705	case ARM::VST3d8:
				2706	case ARM::VST3d16:
				2707	case ARM::VST3d32:
				2708	case ARM::VST3d8_UPD:
				2709	case ARM::VST3d16_UPD:
				2710	case ARM::VST3d32_UPD:
				2711	case ARM::VST4d8:
				2712	case ARM::VST4d16:
				2713	case ARM::VST4d32:
				2714	case ARM::VST4d8_UPD:
				2715	case ARM::VST4d16_UPD:
				2716	case ARM::VST4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2717	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
				2718	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2719	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2720	case ARM::VST3q8:
				2721	case ARM::VST3q16:
				2722	case ARM::VST3q32:
				2723	case ARM::VST3q8_UPD:
				2724	case ARM::VST3q16_UPD:
				2725	case ARM::VST3q32_UPD:
				2726	case ARM::VST4q8:
				2727	case ARM::VST4q16:
				2728	case ARM::VST4q32:
				2729	case ARM::VST4q8_UPD:
				2730	case ARM::VST4q16_UPD:
				2731	case ARM::VST4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2732	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2733	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2734	break;
				2735	default:
				2736	break;
				2737	}
				2738
				2739	// Third input register
				2740	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2741	case ARM::VST3d8:
				2742	case ARM::VST3d16:
				2743	case ARM::VST3d32:
				2744	case ARM::VST3d8_UPD:
				2745	case ARM::VST3d16_UPD:
				2746	case ARM::VST3d32_UPD:
				2747	case ARM::VST4d8:
				2748	case ARM::VST4d16:
				2749	case ARM::VST4d32:
				2750	case ARM::VST4d8_UPD:
				2751	case ARM::VST4d16_UPD:
				2752	case ARM::VST4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2753	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2754	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2755	break;
				2756	case ARM::VST3q8:
				2757	case ARM::VST3q16:
				2758	case ARM::VST3q32:
				2759	case ARM::VST3q8_UPD:
				2760	case ARM::VST3q16_UPD:
				2761	case ARM::VST3q32_UPD:
				2762	case ARM::VST4q8:
				2763	case ARM::VST4q16:
				2764	case ARM::VST4q32:
				2765	case ARM::VST4q8_UPD:
				2766	case ARM::VST4q16_UPD:
				2767	case ARM::VST4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2768	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
				2769	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2770	break;
				2771	default:
				2772	break;
				2773	}
				2774
				2775	// Fourth input register
				2776	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2777	case ARM::VST4d8:
				2778	case ARM::VST4d16:
				2779	case ARM::VST4d32:
				2780	case ARM::VST4d8_UPD:
				2781	case ARM::VST4d16_UPD:
				2782	case ARM::VST4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2783	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
				2784	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2785	break;
				2786	case ARM::VST4q8:
				2787	case ARM::VST4q16:
				2788	case ARM::VST4q32:
				2789	case ARM::VST4q8_UPD:
				2790	case ARM::VST4q16_UPD:
				2791	case ARM::VST4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2792	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
				2793	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2794	break;
				2795	default:
				2796	break;
				2797	}
				2798
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2799	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2800	}
				2801
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2802	static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2803	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2804	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2805
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2806	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2807	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2808	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2809	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2810	unsigned align = fieldFromInstruction(Insn, 4, 1);
				2811	unsigned size = fieldFromInstruction(Insn, 6, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2812
Tim Northover	00e071a	2012-09-06 15:27:12 +0000	[diff] [blame]	2813	if (size == 0 && align == 1)
				2814	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2815	align *= (1 << size);
				2816
Jim Grosbach	13a292c	2012-03-06 22:01:44 +0000	[diff] [blame]	2817	switch (Inst.getOpcode()) {
				2818	case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
				2819	case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
				2820	case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
				2821	case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
				2822	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2823	return MCDisassembler::Fail;
				2824	break;
				2825	default:
				2826	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2827	return MCDisassembler::Fail;
				2828	break;
				2829	}
Owen Anderson	ac92e77	2011-08-22 18:22:06 +0000	[diff] [blame]	2830	if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2831	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2832	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2833	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2834
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2835	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2836	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2837	Inst.addOperand(MCOperand::CreateImm(align));
				2838
Jim Grosbach	a68c9a8	2011-11-30 19:35:44 +0000	[diff] [blame]	2839	// The fixed offset post-increment encodes Rm == 0xd. The no-writeback
				2840	// variant encodes Rm == 0xf. Anything else is a register offset post-
				2841	// increment and we need to add the register operand to the instruction.
				2842	if (Rm != 0xD && Rm != 0xF &&
				2843	!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2844	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2845
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2846	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2847	}
				2848
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2849	static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2850	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2851	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2852
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2853	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2854	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2855	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2856	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2857	unsigned align = fieldFromInstruction(Insn, 4, 1);
				2858	unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2859	align = 2size;
				2860
Jim Grosbach	13a292c	2012-03-06 22:01:44 +0000	[diff] [blame]	2861	switch (Inst.getOpcode()) {
				2862	case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
				2863	case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
				2864	case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
				2865	case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
				2866	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2867	return MCDisassembler::Fail;
				2868	break;
Jim Grosbach	ed428bc	2012-03-06 23:10:38 +0000	[diff] [blame]	2869	case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
				2870	case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
				2871	case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
				2872	case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
				2873	if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
				2874	return MCDisassembler::Fail;
				2875	break;
Jim Grosbach	13a292c	2012-03-06 22:01:44 +0000	[diff] [blame]	2876	default:
				2877	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2878	return MCDisassembler::Fail;
				2879	break;
				2880	}
Kevin Enderby	520eb3b	2012-03-06 18:33:12 +0000	[diff] [blame]	2881
				2882	if (Rm != 0xF)
				2883	Inst.addOperand(MCOperand::CreateImm(0));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2884
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2885	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2886	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2887	Inst.addOperand(MCOperand::CreateImm(align));
				2888
Kevin Enderby	29ae538	2012-04-17 00:49:27 +0000	[diff] [blame]	2889	if (Rm != 0xD && Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2890	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2891	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2892	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2893
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2894	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2895	}
				2896
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2897	static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2898	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2899	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2900
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2901	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2902	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2903	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2904	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2905	unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2906
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2907	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2908	return MCDisassembler::Fail;
				2909	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
				2910	return MCDisassembler::Fail;
				2911	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
				2912	return MCDisassembler::Fail;
Owen Anderson	ac92e77	2011-08-22 18:22:06 +0000	[diff] [blame]	2913	if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2914	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2915	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2916	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2917
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2918	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2919	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2920	Inst.addOperand(MCOperand::CreateImm(0));
				2921
				2922	if (Rm == 0xD)
				2923	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2924	else if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2925	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2926	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2927	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2928
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2929	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2930	}
				2931
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2932	static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2933	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2934	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2935
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2936	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2937	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2938	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2939	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2940	unsigned size = fieldFromInstruction(Insn, 6, 2);
				2941	unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
				2942	unsigned align = fieldFromInstruction(Insn, 4, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2943
				2944	if (size == 0x3) {
Tim Northover	00e071a	2012-09-06 15:27:12 +0000	[diff] [blame]	2945	if (align == 0)
				2946	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2947	size = 4;
				2948	align = 16;
				2949	} else {
				2950	if (size == 2) {
				2951	size = 1 << size;
				2952	align *= 8;
				2953	} else {
				2954	size = 1 << size;
				2955	align = 4size;
				2956	}
				2957	}
				2958
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2959	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2960	return MCDisassembler::Fail;
				2961	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
				2962	return MCDisassembler::Fail;
				2963	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
				2964	return MCDisassembler::Fail;
				2965	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
				2966	return MCDisassembler::Fail;
Owen Anderson	ac92e77	2011-08-22 18:22:06 +0000	[diff] [blame]	2967	if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2968	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2969	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2970	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2971
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2972	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2973	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2974	Inst.addOperand(MCOperand::CreateImm(align));
				2975
				2976	if (Rm == 0xD)
				2977	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2978	else if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2979	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2980	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2981	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2982
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2983	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2984	}
				2985
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2986	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2987	DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	2988	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2989	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2990
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2991	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2992	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2993	unsigned imm = fieldFromInstruction(Insn, 0, 4);
				2994	imm \|= fieldFromInstruction(Insn, 16, 3) << 4;
				2995	imm \|= fieldFromInstruction(Insn, 24, 1) << 7;
				2996	imm \|= fieldFromInstruction(Insn, 8, 4) << 8;
				2997	imm \|= fieldFromInstruction(Insn, 5, 1) << 12;
				2998	unsigned Q = fieldFromInstruction(Insn, 6, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2999
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3000	if (Q) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3001	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				3002	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3003	} else {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3004	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3005	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3006	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3007
				3008	Inst.addOperand(MCOperand::CreateImm(imm));
				3009
				3010	switch (Inst.getOpcode()) {
				3011	case ARM::VORRiv4i16:
				3012	case ARM::VORRiv2i32:
				3013	case ARM::VBICiv4i16:
				3014	case ARM::VBICiv2i32:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3015	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3016	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3017	break;
				3018	case ARM::VORRiv8i16:
				3019	case ARM::VORRiv4i32:
				3020	case ARM::VBICiv8i16:
				3021	case ARM::VBICiv4i32:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3022	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				3023	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3024	break;
				3025	default:
				3026	break;
				3027	}
				3028
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3029	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3030	}
				3031
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3032	static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3033	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3034	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3035
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3036	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3037	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3038	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3039	Rm \|= fieldFromInstruction(Insn, 5, 1) << 4;
				3040	unsigned size = fieldFromInstruction(Insn, 18, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3041
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3042	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				3043	return MCDisassembler::Fail;
				3044	if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
				3045	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3046	Inst.addOperand(MCOperand::CreateImm(8 << size));
				3047
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3048	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3049	}
				3050
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3051	static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3052	uint64_t Address, const void *Decoder) {
				3053	Inst.addOperand(MCOperand::CreateImm(8 - Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3054	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3055	}
				3056
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3057	static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3058	uint64_t Address, const void *Decoder) {
				3059	Inst.addOperand(MCOperand::CreateImm(16 - Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3060	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3061	}
				3062
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3063	static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3064	uint64_t Address, const void *Decoder) {
				3065	Inst.addOperand(MCOperand::CreateImm(32 - Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3066	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3067	}
				3068
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3069	static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3070	uint64_t Address, const void *Decoder) {
				3071	Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3072	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3073	}
				3074
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3075	static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3076	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3077	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3078
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3079	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3080	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3081	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3082	Rn \|= fieldFromInstruction(Insn, 7, 1) << 4;
				3083	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3084	Rm \|= fieldFromInstruction(Insn, 5, 1) << 4;
				3085	unsigned op = fieldFromInstruction(Insn, 6, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3086
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3087	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3088	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3089	if (op) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3090	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3091	return MCDisassembler::Fail; // Writeback
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3092	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3093
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	3094	switch (Inst.getOpcode()) {
				3095	case ARM::VTBL2:
				3096	case ARM::VTBX2:
				3097	if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
				3098	return MCDisassembler::Fail;
				3099	break;
				3100	default:
				3101	if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
				3102	return MCDisassembler::Fail;
				3103	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3104
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3105	if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
				3106	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3107
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3108	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3109	}
				3110
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3111	static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3112	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3113	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3114
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3115	unsigned dst = fieldFromInstruction(Insn, 8, 3);
				3116	unsigned imm = fieldFromInstruction(Insn, 0, 8);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3117
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3118	if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
				3119	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3120
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3121	switch(Inst.getOpcode()) {
Owen Anderson	5658b49	2011-08-26 19:39:26 +0000	[diff] [blame]	3122	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3123	return MCDisassembler::Fail;
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3124	case ARM::tADR:
Owen Anderson	240d20a	2011-08-26 21:47:57 +0000	[diff] [blame]	3125	break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3126	case ARM::tADDrSPi:
				3127	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				3128	break;
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3129	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3130
				3131	Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3132	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3133	}
				3134
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3135	static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3136	uint64_t Address, const void *Decoder) {
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	3137	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
				3138	true, 2, Inst, Decoder))
				3139	Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3140	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3141	}
				3142
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3143	static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3144	uint64_t Address, const void *Decoder) {
Kevin Enderby	cabbae6	2012-05-04 22:09:52 +0000	[diff] [blame]	3145	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	3146	true, 4, Inst, Decoder))
				3147	Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3148	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3149	}
				3150
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3151	static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3152	uint64_t Address, const void *Decoder) {
Gordon Keiser	772cf46	2013-03-28 19:22:28 +0000	[diff] [blame]	3153	if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	3154	true, 2, Inst, Decoder))
Gordon Keiser	772cf46	2013-03-28 19:22:28 +0000	[diff] [blame]	3155	Inst.addOperand(MCOperand::CreateImm(Val << 1));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3156	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3157	}
				3158
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3159	static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3160	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3161	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3162
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3163	unsigned Rn = fieldFromInstruction(Val, 0, 3);
				3164	unsigned Rm = fieldFromInstruction(Val, 3, 3);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3165
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3166	if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3167	return MCDisassembler::Fail;
				3168	if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3169	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3170
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3171	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3172	}
				3173
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3174	static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3175	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3176	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3177
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3178	unsigned Rn = fieldFromInstruction(Val, 0, 3);
				3179	unsigned imm = fieldFromInstruction(Val, 3, 5);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3180
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3181	if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3182	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3183	Inst.addOperand(MCOperand::CreateImm(imm));
				3184
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3185	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3186	}
				3187
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3188	static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3189	uint64_t Address, const void *Decoder) {
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	3190	unsigned imm = Val << 2;
				3191
				3192	Inst.addOperand(MCOperand::CreateImm(imm));
				3193	tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3194
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3195	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3196	}
				3197
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3198	static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3199	uint64_t Address, const void *Decoder) {
				3200	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson	b498132	2011-08-22 17:56:58 +0000	[diff] [blame]	3201	Inst.addOperand(MCOperand::CreateImm(Val));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3202
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3203	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3204	}
				3205
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3206	static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3207	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3208	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3209
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3210	unsigned Rn = fieldFromInstruction(Val, 6, 4);
				3211	unsigned Rm = fieldFromInstruction(Val, 2, 4);
				3212	unsigned imm = fieldFromInstruction(Val, 0, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3213
Amaury de la Vieuville	e2bb1d1	2013-06-18 08:02:56 +0000	[diff] [blame]	3214	// Thumb stores cannot use PC as dest register.
				3215	switch (Inst.getOpcode()) {
				3216	case ARM::t2STRHs:
				3217	case ARM::t2STRBs:
				3218	case ARM::t2STRs:
				3219	if (Rn == 15)
				3220	return MCDisassembler::Fail;
				3221	default:
				3222	break;
				3223	}
				3224
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3225	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3226	return MCDisassembler::Fail;
				3227	if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3228	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3229	Inst.addOperand(MCOperand::CreateImm(imm));
				3230
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3231	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3232	}
				3233
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3234	static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3235	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3236	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3237
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3238	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3239	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3240
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3241	if (Rn == 15) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3242	switch (Inst.getOpcode()) {
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3243	case ARM::t2LDRBs:
				3244	Inst.setOpcode(ARM::t2LDRBpci);
				3245	break;
				3246	case ARM::t2LDRHs:
				3247	Inst.setOpcode(ARM::t2LDRHpci);
				3248	break;
				3249	case ARM::t2LDRSHs:
				3250	Inst.setOpcode(ARM::t2LDRSHpci);
				3251	break;
				3252	case ARM::t2LDRSBs:
				3253	Inst.setOpcode(ARM::t2LDRSBpci);
				3254	break;
				3255	case ARM::t2LDRs:
				3256	Inst.setOpcode(ARM::t2LDRpci);
				3257	break;
				3258	case ARM::t2PLDs:
				3259	Inst.setOpcode(ARM::t2PLDpci);
				3260	break;
				3261	case ARM::t2PLIs:
				3262	Inst.setOpcode(ARM::t2PLIpci);
				3263	break;
				3264	default:
				3265	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3266	}
				3267
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3268	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3269	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3270
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3271	if (Rt == 15) {
				3272	switch (Inst.getOpcode()) {
				3273	case ARM::t2LDRSHs:
				3274	return MCDisassembler::Fail;
				3275	case ARM::t2LDRHs:
				3276	// FIXME: this instruction is only available with MP extensions,
				3277	// this should be checked first but we don't have access to the
				3278	// feature bits here.
				3279	Inst.setOpcode(ARM::t2PLDWs);
				3280	break;
				3281	default:
				3282	break;
				3283	}
				3284	}
				3285
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3286	switch (Inst.getOpcode()) {
				3287	case ARM::t2PLDs:
				3288	case ARM::t2PLDWs:
				3289	case ARM::t2PLIs:
				3290	break;
				3291	default:
				3292	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3293	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3294	}
				3295
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3296	unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
				3297	addrmode \|= fieldFromInstruction(Insn, 0, 4) << 2;
				3298	addrmode \|= fieldFromInstruction(Insn, 16, 4) << 6;
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3299	if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
				3300	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3301
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3302	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3303	}
				3304
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3305	static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
				3306	uint64_t Address, const void* Decoder) {
				3307	DecodeStatus S = MCDisassembler::Success;
				3308
				3309	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3310	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3311	unsigned U = fieldFromInstruction(Insn, 9, 1);
				3312	unsigned imm = fieldFromInstruction(Insn, 0, 8);
				3313	imm \|= (U << 8);
				3314	imm \|= (Rn << 9);
				3315
				3316	if (Rn == 15) {
				3317	switch (Inst.getOpcode()) {
				3318	case ARM::t2LDRi8:
				3319	Inst.setOpcode(ARM::t2LDRpci);
				3320	break;
				3321	case ARM::t2LDRBi8:
				3322	Inst.setOpcode(ARM::t2LDRBpci);
				3323	break;
				3324	case ARM::t2LDRSBi8:
				3325	Inst.setOpcode(ARM::t2LDRSBpci);
				3326	break;
				3327	case ARM::t2LDRHi8:
				3328	Inst.setOpcode(ARM::t2LDRHpci);
				3329	break;
				3330	case ARM::t2LDRSHi8:
				3331	Inst.setOpcode(ARM::t2LDRSHpci);
				3332	break;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3333	case ARM::t2PLDi8:
				3334	Inst.setOpcode(ARM::t2PLDpci);
				3335	break;
				3336	case ARM::t2PLIi8:
				3337	Inst.setOpcode(ARM::t2PLIpci);
				3338	break;
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3339	default:
				3340	return MCDisassembler::Fail;
				3341	}
				3342	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3343	}
				3344
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3345	if (Rt == 15) {
				3346	switch (Inst.getOpcode()) {
				3347	case ARM::t2LDRSHi8:
				3348	return MCDisassembler::Fail;
				3349	default:
				3350	break;
				3351	}
				3352	}
				3353
				3354	switch (Inst.getOpcode()) {
				3355	case ARM::t2PLDi8:
				3356	case ARM::t2PLIi8:
				3357	break;
				3358	default:
				3359	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3360	return MCDisassembler::Fail;
				3361	}
				3362
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3363	if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
				3364	return MCDisassembler::Fail;
				3365	return S;
				3366	}
				3367
				3368	static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
				3369	uint64_t Address, const void* Decoder) {
				3370	DecodeStatus S = MCDisassembler::Success;
				3371
				3372	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3373	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3374	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				3375	imm \|= (Rn << 13);
				3376
				3377	if (Rn == 15) {
				3378	switch (Inst.getOpcode()) {
				3379	case ARM::t2LDRi12:
				3380	Inst.setOpcode(ARM::t2LDRpci);
				3381	break;
				3382	case ARM::t2LDRHi12:
				3383	Inst.setOpcode(ARM::t2LDRHpci);
				3384	break;
				3385	case ARM::t2LDRSHi12:
				3386	Inst.setOpcode(ARM::t2LDRSHpci);
				3387	break;
				3388	case ARM::t2LDRBi12:
				3389	Inst.setOpcode(ARM::t2LDRBpci);
				3390	break;
				3391	case ARM::t2LDRSBi12:
				3392	Inst.setOpcode(ARM::t2LDRSBpci);
				3393	break;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3394	case ARM::t2PLDi12:
				3395	Inst.setOpcode(ARM::t2PLDpci);
				3396	break;
				3397	case ARM::t2PLIi12:
				3398	Inst.setOpcode(ARM::t2PLIpci);
				3399	break;
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3400	default:
				3401	return MCDisassembler::Fail;
				3402	}
				3403	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3404	}
				3405
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3406	if (Rt == 15) {
				3407	switch (Inst.getOpcode()) {
				3408	case ARM::t2LDRSHi12:
				3409	return MCDisassembler::Fail;
				3410	case ARM::t2LDRHi12:
				3411	Inst.setOpcode(ARM::t2PLDi12);
				3412	break;
				3413	default:
				3414	break;
				3415	}
				3416	}
				3417
				3418	switch (Inst.getOpcode()) {
				3419	case ARM::t2PLDi12:
				3420	case ARM::t2PLIi12:
				3421	break;
				3422	default:
				3423	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3424	return MCDisassembler::Fail;
				3425	}
				3426
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3427	if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
				3428	return MCDisassembler::Fail;
				3429	return S;
				3430	}
				3431
				3432	static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
				3433	uint64_t Address, const void* Decoder) {
				3434	DecodeStatus S = MCDisassembler::Success;
				3435
				3436	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3437	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3438	unsigned imm = fieldFromInstruction(Insn, 0, 8);
				3439	imm \|= (Rn << 9);
				3440
				3441	if (Rn == 15) {
				3442	switch (Inst.getOpcode()) {
				3443	case ARM::t2LDRT:
				3444	Inst.setOpcode(ARM::t2LDRpci);
				3445	break;
				3446	case ARM::t2LDRBT:
				3447	Inst.setOpcode(ARM::t2LDRBpci);
				3448	break;
				3449	case ARM::t2LDRHT:
				3450	Inst.setOpcode(ARM::t2LDRHpci);
				3451	break;
				3452	case ARM::t2LDRSBT:
				3453	Inst.setOpcode(ARM::t2LDRSBpci);
				3454	break;
				3455	case ARM::t2LDRSHT:
				3456	Inst.setOpcode(ARM::t2LDRSHpci);
				3457	break;
				3458	default:
				3459	return MCDisassembler::Fail;
				3460	}
				3461	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3462	}
				3463
				3464	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3465	return MCDisassembler::Fail;
				3466	if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
				3467	return MCDisassembler::Fail;
				3468	return S;
				3469	}
				3470
				3471	static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
				3472	uint64_t Address, const void* Decoder) {
				3473	DecodeStatus S = MCDisassembler::Success;
				3474
				3475	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3476	unsigned U = fieldFromInstruction(Insn, 23, 1);
				3477	int imm = fieldFromInstruction(Insn, 0, 12);
				3478
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3479	if (Rt == 15) {
				3480	switch (Inst.getOpcode()) {
				3481	case ARM::t2LDRBpci:
				3482	case ARM::t2LDRHpci:
				3483	Inst.setOpcode(ARM::t2PLDpci);
				3484	break;
				3485	case ARM::t2LDRSBpci:
				3486	Inst.setOpcode(ARM::t2PLIpci);
				3487	break;
				3488	case ARM::t2LDRSHpci:
				3489	return MCDisassembler::Fail;
				3490	default:
				3491	break;
				3492	}
				3493	}
				3494
				3495	switch(Inst.getOpcode()) {
				3496	case ARM::t2PLDpci:
				3497	case ARM::t2PLIpci:
				3498	break;
				3499	default:
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3500	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3501	return MCDisassembler::Fail;
				3502	}
				3503
				3504	if (!U) {
				3505	// Special case for #-0.
				3506	if (imm == 0)
				3507	imm = INT32_MIN;
				3508	else
				3509	imm = -imm;
				3510	}
				3511	Inst.addOperand(MCOperand::CreateImm(imm));
				3512
				3513	return S;
				3514	}
				3515
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3516	static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3517	uint64_t Address, const void *Decoder) {
Jiangning Liu	6a43bf7	2012-08-02 08:29:50 +0000	[diff] [blame]	3518	if (Val == 0)
				3519	Inst.addOperand(MCOperand::CreateImm(INT32_MIN));
				3520	else {
				3521	int imm = Val & 0xFF;
				3522
				3523	if (!(Val & 0x100)) imm *= -1;
Richard Smith	228e6d4	2012-08-24 23:29:28 +0000	[diff] [blame]	3524	Inst.addOperand(MCOperand::CreateImm(imm * 4));
Jiangning Liu	6a43bf7	2012-08-02 08:29:50 +0000	[diff] [blame]	3525	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3526
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3527	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3528	}
				3529
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3530	static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3531	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3532	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3533
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3534	unsigned Rn = fieldFromInstruction(Val, 9, 4);
				3535	unsigned imm = fieldFromInstruction(Val, 0, 9);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3536
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3537	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3538	return MCDisassembler::Fail;
				3539	if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
				3540	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3541
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3542	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3543	}
				3544
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3545	static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbach	a05627e	2011-09-09 18:37:27 +0000	[diff] [blame]	3546	uint64_t Address, const void *Decoder) {
				3547	DecodeStatus S = MCDisassembler::Success;
				3548
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3549	unsigned Rn = fieldFromInstruction(Val, 8, 4);
				3550	unsigned imm = fieldFromInstruction(Val, 0, 8);
Jim Grosbach	a05627e	2011-09-09 18:37:27 +0000	[diff] [blame]	3551
				3552	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				3553	return MCDisassembler::Fail;
				3554
				3555	Inst.addOperand(MCOperand::CreateImm(imm));
				3556
				3557	return S;
				3558	}
				3559
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3560	static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3561	uint64_t Address, const void *Decoder) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3562	int imm = Val & 0xFF;
Owen Anderson	fe82365	2011-09-16 21:08:33 +0000	[diff] [blame]	3563	if (Val == 0)
				3564	imm = INT32_MIN;
				3565	else if (!(Val & 0x100))
				3566	imm *= -1;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3567	Inst.addOperand(MCOperand::CreateImm(imm));
				3568
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3569	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3570	}
				3571
				3572
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3573	static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3574	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3575	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3576
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3577	unsigned Rn = fieldFromInstruction(Val, 9, 4);
				3578	unsigned imm = fieldFromInstruction(Val, 0, 9);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3579
Amaury de la Vieuville	e2bb1d1	2013-06-18 08:02:56 +0000	[diff] [blame]	3580	// Thumb stores cannot use PC as dest register.
				3581	switch (Inst.getOpcode()) {
				3582	case ARM::t2STRT:
				3583	case ARM::t2STRBT:
				3584	case ARM::t2STRHT:
				3585	case ARM::t2STRi8:
				3586	case ARM::t2STRHi8:
				3587	case ARM::t2STRBi8:
				3588	if (Rn == 15)
				3589	return MCDisassembler::Fail;
				3590	break;
				3591	default:
				3592	break;
				3593	}
				3594
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3595	// Some instructions always use an additive offset.
				3596	switch (Inst.getOpcode()) {
				3597	case ARM::t2LDRT:
				3598	case ARM::t2LDRBT:
				3599	case ARM::t2LDRHT:
				3600	case ARM::t2LDRSBT:
				3601	case ARM::t2LDRSHT:
Owen Anderson	ddfcec9	2011-09-19 18:07:10 +0000	[diff] [blame]	3602	case ARM::t2STRT:
				3603	case ARM::t2STRBT:
				3604	case ARM::t2STRHT:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3605	imm \|= 0x100;
				3606	break;
				3607	default:
				3608	break;
				3609	}
				3610
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3611	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3612	return MCDisassembler::Fail;
				3613	if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
				3614	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3615
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3616	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3617	}
				3618
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3619	static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3620	uint64_t Address, const void *Decoder) {
				3621	DecodeStatus S = MCDisassembler::Success;
				3622
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3623	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3624	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3625	unsigned addr = fieldFromInstruction(Insn, 0, 8);
				3626	addr \|= fieldFromInstruction(Insn, 9, 1) << 8;
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3627	addr \|= Rn << 9;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3628	unsigned load = fieldFromInstruction(Insn, 20, 1);
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3629
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3630	if (Rn == 15) {
				3631	switch (Inst.getOpcode()) {
				3632	case ARM::t2LDR_PRE:
				3633	case ARM::t2LDR_POST:
				3634	Inst.setOpcode(ARM::t2LDRpci);
				3635	break;
				3636	case ARM::t2LDRB_PRE:
				3637	case ARM::t2LDRB_POST:
				3638	Inst.setOpcode(ARM::t2LDRBpci);
				3639	break;
				3640	case ARM::t2LDRH_PRE:
				3641	case ARM::t2LDRH_POST:
				3642	Inst.setOpcode(ARM::t2LDRHpci);
				3643	break;
				3644	case ARM::t2LDRSB_PRE:
				3645	case ARM::t2LDRSB_POST:
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3646	if (Rt == 15)
				3647	Inst.setOpcode(ARM::t2PLIpci);
				3648	else
				3649	Inst.setOpcode(ARM::t2LDRSBpci);
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3650	break;
				3651	case ARM::t2LDRSH_PRE:
				3652	case ARM::t2LDRSH_POST:
				3653	Inst.setOpcode(ARM::t2LDRSHpci);
				3654	break;
				3655	default:
				3656	return MCDisassembler::Fail;
				3657	}
				3658	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3659	}
				3660
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3661	if (!load) {
				3662	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3663	return MCDisassembler::Fail;
				3664	}
				3665
Joe Abbey	f686be4	2013-03-26 13:58:53 +0000	[diff] [blame]	3666	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3667	return MCDisassembler::Fail;
				3668
				3669	if (load) {
				3670	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3671	return MCDisassembler::Fail;
				3672	}
				3673
				3674	if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
				3675	return MCDisassembler::Fail;
				3676
				3677	return S;
				3678	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3679
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3680	static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3681	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3682	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3683
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3684	unsigned Rn = fieldFromInstruction(Val, 13, 4);
				3685	unsigned imm = fieldFromInstruction(Val, 0, 12);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3686
Amaury de la Vieuville	e2bb1d1	2013-06-18 08:02:56 +0000	[diff] [blame]	3687	// Thumb stores cannot use PC as dest register.
				3688	switch (Inst.getOpcode()) {
				3689	case ARM::t2STRi12:
				3690	case ARM::t2STRBi12:
				3691	case ARM::t2STRHi12:
				3692	if (Rn == 15)
				3693	return MCDisassembler::Fail;
				3694	default:
				3695	break;
				3696	}
				3697
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3698	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3699	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3700	Inst.addOperand(MCOperand::CreateImm(imm));
				3701
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3702	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3703	}
				3704
				3705
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3706	static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3707	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3708	unsigned imm = fieldFromInstruction(Insn, 0, 7);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3709
				3710	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				3711	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				3712	Inst.addOperand(MCOperand::CreateImm(imm));
				3713
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3714	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3715	}
				3716
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3717	static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3718	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3719	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3720
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3721	if (Inst.getOpcode() == ARM::tADDrSP) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3722	unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
				3723	Rdm \|= fieldFromInstruction(Insn, 7, 1) << 3;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3724
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3725	if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
				3726	return MCDisassembler::Fail;
Jim Grosbach	9d8f6f3	2012-04-27 23:51:33 +0000	[diff] [blame]	3727	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3728	if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
				3729	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3730	} else if (Inst.getOpcode() == ARM::tADDspr) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3731	unsigned Rm = fieldFromInstruction(Insn, 3, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3732
				3733	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				3734	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3735	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3736	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3737	}
				3738
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3739	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3740	}
				3741
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3742	static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3743	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3744	unsigned imod = fieldFromInstruction(Insn, 4, 1) \| 0x2;
				3745	unsigned flags = fieldFromInstruction(Insn, 0, 3);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3746
				3747	Inst.addOperand(MCOperand::CreateImm(imod));
				3748	Inst.addOperand(MCOperand::CreateImm(flags));
				3749
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3750	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3751	}
				3752
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3753	static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3754	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3755	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3756	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3757	unsigned add = fieldFromInstruction(Insn, 4, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3758
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	3759	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3760	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3761	Inst.addOperand(MCOperand::CreateImm(add));
				3762
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3763	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3764	}
				3765
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3766	static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3767	uint64_t Address, const void *Decoder) {
NAKAMURA Takumi	70c1aa0	2012-05-22 21:47:02 +0000	[diff] [blame]	3768	// Val is passed in as S:J1:J2:imm10H:imm10L:'0'
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3769	// Note only one trailing zero not two. Also the J1 and J2 values are from
				3770	// the encoded instruction. So here change to I1 and I2 values via:
				3771	// I1 = NOT(J1 EOR S);
				3772	// I2 = NOT(J2 EOR S);
				3773	// and build the imm32 with two trailing zeros as documented:
NAKAMURA Takumi	70c1aa0	2012-05-22 21:47:02 +0000	[diff] [blame]	3774	// imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3775	unsigned S = (Val >> 23) & 1;
				3776	unsigned J1 = (Val >> 22) & 1;
				3777	unsigned J2 = (Val >> 21) & 1;
				3778	unsigned I1 = !(J1 ^ S);
				3779	unsigned I2 = !(J2 ^ S);
				3780	unsigned tmp = (Val & ~0x600000) \| (I1 << 22) \| (I2 << 21);
				3781	int imm32 = SignExtend32<25>(tmp << 1);
				3782
Jim Grosbach	79ebc51	2011-10-20 17:28:20 +0000	[diff] [blame]	3783	if (!tryAddingSymbolicOperand(Address,
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3784	(Address & ~2u) + imm32 + 4,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	3785	true, 4, Inst, Decoder))
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3786	Inst.addOperand(MCOperand::CreateImm(imm32));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3787	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3788	}
				3789
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3790	static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3791	uint64_t Address, const void *Decoder) {
				3792	if (Val == 0xA \|\| Val == 0xB)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3793	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3794
				3795	Inst.addOperand(MCOperand::CreateImm(Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3796	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3797	}
				3798
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3799	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3800	DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
Jim Grosbach	05541f4	2011-09-19 22:21:13 +0000	[diff] [blame]	3801	uint64_t Address, const void *Decoder) {
				3802	DecodeStatus S = MCDisassembler::Success;
				3803
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3804	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3805	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Jim Grosbach	05541f4	2011-09-19 22:21:13 +0000	[diff] [blame]	3806
				3807	if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
				3808	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3809	return MCDisassembler::Fail;
				3810	if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3811	return MCDisassembler::Fail;
				3812	return S;
				3813	}
				3814
				3815	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3816	DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	3817	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3818	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3819
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3820	unsigned pred = fieldFromInstruction(Insn, 22, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3821	if (pred == 0xE \|\| pred == 0xF) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3822	unsigned opc = fieldFromInstruction(Insn, 4, 28);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3823	switch (opc) {
				3824	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3825	return MCDisassembler::Fail;
Owen Anderson	4af0aa9	2011-08-31 22:00:41 +0000	[diff] [blame]	3826	case 0xf3bf8f4:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3827	Inst.setOpcode(ARM::t2DSB);
				3828	break;
Owen Anderson	4af0aa9	2011-08-31 22:00:41 +0000	[diff] [blame]	3829	case 0xf3bf8f5:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3830	Inst.setOpcode(ARM::t2DMB);
				3831	break;
Owen Anderson	4af0aa9	2011-08-31 22:00:41 +0000	[diff] [blame]	3832	case 0xf3bf8f6:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3833	Inst.setOpcode(ARM::t2ISB);
Owen Anderson	cd5612d	2011-09-07 17:55:19 +0000	[diff] [blame]	3834	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3835	}
				3836
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3837	unsigned imm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	3838	return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3839	}
				3840
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3841	unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
				3842	brtarget \|= fieldFromInstruction(Insn, 11, 1) << 19;
				3843	brtarget \|= fieldFromInstruction(Insn, 13, 1) << 18;
				3844	brtarget \|= fieldFromInstruction(Insn, 16, 6) << 12;
				3845	brtarget \|= fieldFromInstruction(Insn, 26, 1) << 20;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3846
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3847	if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
				3848	return MCDisassembler::Fail;
				3849	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3850	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3851
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3852	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3853	}
				3854
				3855	// Decode a shifted immediate operand. These basically consist
				3856	// of an 8-bit value, and a 4-bit directive that specifies either
				3857	// a splat operation or a rotation.
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3858	static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3859	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3860	unsigned ctrl = fieldFromInstruction(Val, 10, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3861	if (ctrl == 0) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3862	unsigned byte = fieldFromInstruction(Val, 8, 2);
				3863	unsigned imm = fieldFromInstruction(Val, 0, 8);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3864	switch (byte) {
				3865	case 0:
				3866	Inst.addOperand(MCOperand::CreateImm(imm));
				3867	break;
				3868	case 1:
				3869	Inst.addOperand(MCOperand::CreateImm((imm << 16) \| imm));
				3870	break;
				3871	case 2:
				3872	Inst.addOperand(MCOperand::CreateImm((imm << 24) \| (imm << 8)));
				3873	break;
				3874	case 3:
				3875	Inst.addOperand(MCOperand::CreateImm((imm << 24) \| (imm << 16) \|
				3876	(imm << 8) \| imm));
				3877	break;
				3878	}
				3879	} else {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3880	unsigned unrot = fieldFromInstruction(Val, 0, 7) \| 0x80;
				3881	unsigned rot = fieldFromInstruction(Val, 7, 5);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3882	unsigned imm = (unrot >> rot) \| (unrot << ((32-rot)&31));
				3883	Inst.addOperand(MCOperand::CreateImm(imm));
				3884	}
				3885
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3886	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3887	}
				3888
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3889	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3890	DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	3891	uint64_t Address, const void *Decoder){
Richard Barton	f1ef87d	2012-06-06 09:12:53 +0000	[diff] [blame]	3892	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	3893	true, 2, Inst, Decoder))
Richard Barton	f1ef87d	2012-06-06 09:12:53 +0000	[diff] [blame]	3894	Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1)));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3895	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3896	}
				3897
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3898	static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3899	uint64_t Address, const void *Decoder){
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3900	// Val is passed in as S:J1:J2:imm10:imm11
				3901	// Note no trailing zero after imm11. Also the J1 and J2 values are from
				3902	// the encoded instruction. So here change to I1 and I2 values via:
				3903	// I1 = NOT(J1 EOR S);
				3904	// I2 = NOT(J2 EOR S);
				3905	// and build the imm32 with one trailing zero as documented:
NAKAMURA Takumi	70c1aa0	2012-05-22 21:47:02 +0000	[diff] [blame]	3906	// imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3907	unsigned S = (Val >> 23) & 1;
				3908	unsigned J1 = (Val >> 22) & 1;
				3909	unsigned J2 = (Val >> 21) & 1;
				3910	unsigned I1 = !(J1 ^ S);
				3911	unsigned I2 = !(J2 ^ S);
				3912	unsigned tmp = (Val & ~0x600000) \| (I1 << 22) \| (I2 << 21);
				3913	int imm32 = SignExtend32<25>(tmp << 1);
				3914
				3915	if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
Kevin Enderby	6fbcd8d	2012-02-23 18:18:17 +0000	[diff] [blame]	3916	true, 4, Inst, Decoder))
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3917	Inst.addOperand(MCOperand::CreateImm(imm32));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3918	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3919	}
				3920
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3921	static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	3922	uint64_t Address, const void *Decoder) {
Jiangning Liu	288e1af	2012-08-02 08:21:27 +0000	[diff] [blame]	3923	if (Val & ~0xf)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3924	return MCDisassembler::Fail;
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	3925
				3926	Inst.addOperand(MCOperand::CreateImm(Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3927	return MCDisassembler::Success;
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	3928	}
				3929
Amaury de la Vieuville	43cb13a	2013-06-10 14:17:08 +0000	[diff] [blame]	3930	static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
				3931	uint64_t Address, const void *Decoder) {
				3932	if (Val & ~0xf)
				3933	return MCDisassembler::Fail;
				3934
				3935	Inst.addOperand(MCOperand::CreateImm(Val));
				3936	return MCDisassembler::Success;
				3937	}
				3938
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3939	static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	3940	uint64_t Address, const void *Decoder) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3941	if (!Val) return MCDisassembler::Fail;
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	3942	Inst.addOperand(MCOperand::CreateImm(Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3943	return MCDisassembler::Success;
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	3944	}
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	3945
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3946	static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	3947	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3948	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3949
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3950	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3951	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3952	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	3953
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	3954	if (Rn == 0xF)
				3955	S = MCDisassembler::SoftFail;
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	3956
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	3957	if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3958	return MCDisassembler::Fail;
				3959	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3960	return MCDisassembler::Fail;
				3961	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3962	return MCDisassembler::Fail;
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	3963
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3964	return S;
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	3965	}
				3966
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3967	static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	3968	uint64_t Address, const void *Decoder){
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3969	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3970
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3971	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3972	unsigned Rt = fieldFromInstruction(Insn, 0, 4);
				3973	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3974	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	3975
Tim Northover	27ff504	2013-04-19 15:44:32 +0000	[diff] [blame]	3976	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3977	return MCDisassembler::Fail;
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	3978
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	3979	if (Rn == 0xF \|\| Rd == Rn \|\| Rd == Rt \|\| Rd == Rt+1)
				3980	S = MCDisassembler::SoftFail;
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	3981
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	3982	if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3983	return MCDisassembler::Fail;
				3984	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3985	return MCDisassembler::Fail;
				3986	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3987	return MCDisassembler::Fail;
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	3988
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3989	return S;
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	3990	}
				3991
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3992	static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	3993	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3994	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	3995
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3996	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3997	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3998	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				3999	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				4000	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				4001	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4002
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4003	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4004
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4005	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4006	return MCDisassembler::Fail;
				4007	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4008	return MCDisassembler::Fail;
				4009	if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
				4010	return MCDisassembler::Fail;
				4011	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4012	return MCDisassembler::Fail;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4013
				4014	return S;
				4015	}
				4016
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4017	static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4018	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4019	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4020
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4021	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4022	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4023	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				4024	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				4025	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				4026	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				4027	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4028
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4029	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
				4030	if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4031
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4032	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4033	return MCDisassembler::Fail;
				4034	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4035	return MCDisassembler::Fail;
				4036	if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
				4037	return MCDisassembler::Fail;
				4038	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4039	return MCDisassembler::Fail;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4040
				4041	return S;
				4042	}
				4043
				4044
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4045	static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4046	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4047	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4048
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4049	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4050	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4051	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				4052	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				4053	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				4054	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4055
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4056	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4057
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4058	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4059	return MCDisassembler::Fail;
				4060	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4061	return MCDisassembler::Fail;
				4062	if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
				4063	return MCDisassembler::Fail;
				4064	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4065	return MCDisassembler::Fail;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4066
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4067	return S;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4068	}
				4069
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4070	static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4071	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4072	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4073
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4074	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4075	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4076	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				4077	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				4078	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				4079	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4080
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4081	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4082
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4083	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4084	return MCDisassembler::Fail;
				4085	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4086	return MCDisassembler::Fail;
				4087	if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
				4088	return MCDisassembler::Fail;
				4089	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4090	return MCDisassembler::Fail;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4091
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4092	return S;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4093	}
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4094
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4095	static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4096	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4097	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4098
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4099	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4100	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4101	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4102	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4103	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4104
				4105	unsigned align = 0;
				4106	unsigned index = 0;
				4107	switch (size) {
				4108	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4109	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4110	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4111	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4112	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4113	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4114	break;
				4115	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4116	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4117	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4118	index = fieldFromInstruction(Insn, 6, 2);
				4119	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4120	align = 2;
				4121	break;
				4122	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4123	if (fieldFromInstruction(Insn, 6, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4124	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4125	index = fieldFromInstruction(Insn, 7, 1);
Tim Northover	fb3cdd8	2012-09-06 15:17:49 +0000	[diff] [blame]	4126
				4127	switch (fieldFromInstruction(Insn, 4, 2)) {
				4128	case 0 :
				4129	align = 0; break;
				4130	case 3:
				4131	align = 4; break;
				4132	default:
				4133	return MCDisassembler::Fail;
				4134	}
				4135	break;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4136	}
				4137
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4138	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4139	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4140	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4141	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4142	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4143	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4144	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4145	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4146	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4147	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4148	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4149	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4150	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4151	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4152	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4153	}
				4154
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4155	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4156	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4157	Inst.addOperand(MCOperand::CreateImm(index));
				4158
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4159	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4160	}
				4161
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4162	static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4163	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4164	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4165
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4166	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4167	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4168	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4169	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4170	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4171
				4172	unsigned align = 0;
				4173	unsigned index = 0;
				4174	switch (size) {
				4175	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4176	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4177	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4178	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4179	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4180	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4181	break;
				4182	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4183	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4184	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4185	index = fieldFromInstruction(Insn, 6, 2);
				4186	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4187	align = 2;
				4188	break;
				4189	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4190	if (fieldFromInstruction(Insn, 6, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4191	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4192	index = fieldFromInstruction(Insn, 7, 1);
Tim Northover	fb3cdd8	2012-09-06 15:17:49 +0000	[diff] [blame]	4193
				4194	switch (fieldFromInstruction(Insn, 4, 2)) {
				4195	case 0:
				4196	align = 0; break;
				4197	case 3:
				4198	align = 4; break;
				4199	default:
				4200	return MCDisassembler::Fail;
				4201	}
				4202	break;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4203	}
				4204
				4205	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4206	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4207	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4208	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4209	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4210	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4211	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4212	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4213	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4214	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4215	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4216	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4217	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4218	}
				4219
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4220	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4221	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4222	Inst.addOperand(MCOperand::CreateImm(index));
				4223
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4224	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4225	}
				4226
				4227
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4228	static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4229	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4230	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4231
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4232	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4233	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4234	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4235	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4236	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4237
				4238	unsigned align = 0;
				4239	unsigned index = 0;
				4240	unsigned inc = 1;
				4241	switch (size) {
				4242	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4243	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4244	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4245	index = fieldFromInstruction(Insn, 5, 3);
				4246	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4247	align = 2;
				4248	break;
				4249	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4250	index = fieldFromInstruction(Insn, 6, 2);
				4251	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4252	align = 4;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4253	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4254	inc = 2;
				4255	break;
				4256	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4257	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4258	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4259	index = fieldFromInstruction(Insn, 7, 1);
				4260	if (fieldFromInstruction(Insn, 4, 1) != 0)
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4261	align = 8;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4262	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4263	inc = 2;
				4264	break;
				4265	}
				4266
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4267	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4268	return MCDisassembler::Fail;
				4269	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4270	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4271	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4272	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4273	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4274	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4275	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4276	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4277	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4278	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4279	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4280	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4281	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4282	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4283	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4284	}
				4285
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4286	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4287	return MCDisassembler::Fail;
				4288	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4289	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4290	Inst.addOperand(MCOperand::CreateImm(index));
				4291
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4292	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4293	}
				4294
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4295	static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4296	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4297	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4298
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4299	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4300	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4301	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4302	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4303	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4304
				4305	unsigned align = 0;
				4306	unsigned index = 0;
				4307	unsigned inc = 1;
				4308	switch (size) {
				4309	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4310	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4311	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4312	index = fieldFromInstruction(Insn, 5, 3);
				4313	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4314	align = 2;
				4315	break;
				4316	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4317	index = fieldFromInstruction(Insn, 6, 2);
				4318	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4319	align = 4;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4320	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4321	inc = 2;
				4322	break;
				4323	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4324	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4325	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4326	index = fieldFromInstruction(Insn, 7, 1);
				4327	if (fieldFromInstruction(Insn, 4, 1) != 0)
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4328	align = 8;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4329	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4330	inc = 2;
				4331	break;
				4332	}
				4333
				4334	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4335	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4336	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4337	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4338	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4339	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4340	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4341	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4342	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4343	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4344	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4345	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4346	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4347	}
				4348
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4349	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4350	return MCDisassembler::Fail;
				4351	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4352	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4353	Inst.addOperand(MCOperand::CreateImm(index));
				4354
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4355	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4356	}
				4357
				4358
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4359	static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4360	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4361	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4362
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4363	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4364	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4365	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4366	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4367	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4368
				4369	unsigned align = 0;
				4370	unsigned index = 0;
				4371	unsigned inc = 1;
				4372	switch (size) {
				4373	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4374	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4375	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4376	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4377	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4378	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4379	break;
				4380	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4381	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4382	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4383	index = fieldFromInstruction(Insn, 6, 2);
				4384	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4385	inc = 2;
				4386	break;
				4387	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4388	if (fieldFromInstruction(Insn, 4, 2))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4389	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4390	index = fieldFromInstruction(Insn, 7, 1);
				4391	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4392	inc = 2;
				4393	break;
				4394	}
				4395
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4396	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4397	return MCDisassembler::Fail;
				4398	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4399	return MCDisassembler::Fail;
				4400	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4401	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4402
				4403	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4404	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4405	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4406	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4407	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4408	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4409	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	4410	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4411	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4412	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4413	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4414	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4415	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4416	}
				4417
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4418	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4419	return MCDisassembler::Fail;
				4420	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4421	return MCDisassembler::Fail;
				4422	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4423	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4424	Inst.addOperand(MCOperand::CreateImm(index));
				4425
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4426	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4427	}
				4428
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4429	static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4430	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4431	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4432
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4433	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4434	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4435	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4436	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4437	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4438
				4439	unsigned align = 0;
				4440	unsigned index = 0;
				4441	unsigned inc = 1;
				4442	switch (size) {
				4443	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4444	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4445	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4446	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4447	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4448	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4449	break;
				4450	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4451	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4452	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4453	index = fieldFromInstruction(Insn, 6, 2);
				4454	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4455	inc = 2;
				4456	break;
				4457	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4458	if (fieldFromInstruction(Insn, 4, 2))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4459	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4460	index = fieldFromInstruction(Insn, 7, 1);
				4461	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4462	inc = 2;
				4463	break;
				4464	}
				4465
				4466	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4467	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4468	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4469	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4470	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4471	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4472	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4473	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4474	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4475	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4476	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4477	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4478	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4479	}
				4480
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4481	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4482	return MCDisassembler::Fail;
				4483	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4484	return MCDisassembler::Fail;
				4485	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4486	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4487	Inst.addOperand(MCOperand::CreateImm(index));
				4488
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4489	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4490	}
				4491
				4492
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4493	static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4494	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4495	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4496
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4497	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4498	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4499	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4500	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4501	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4502
				4503	unsigned align = 0;
				4504	unsigned index = 0;
				4505	unsigned inc = 1;
				4506	switch (size) {
				4507	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4508	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4509	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4510	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4511	align = 4;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4512	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4513	break;
				4514	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4515	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4516	align = 8;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4517	index = fieldFromInstruction(Insn, 6, 2);
				4518	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4519	inc = 2;
				4520	break;
				4521	case 2:
Tim Northover	fb3cdd8	2012-09-06 15:17:49 +0000	[diff] [blame]	4522	switch (fieldFromInstruction(Insn, 4, 2)) {
				4523	case 0:
				4524	align = 0; break;
				4525	case 3:
				4526	return MCDisassembler::Fail;
				4527	default:
				4528	align = 4 << fieldFromInstruction(Insn, 4, 2); break;
				4529	}
				4530
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4531	index = fieldFromInstruction(Insn, 7, 1);
				4532	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4533	inc = 2;
				4534	break;
				4535	}
				4536
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4537	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4538	return MCDisassembler::Fail;
				4539	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4540	return MCDisassembler::Fail;
				4541	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4542	return MCDisassembler::Fail;
				4543	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				4544	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4545
				4546	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4547	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4548	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4549	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4550	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4551	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4552	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4553	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4554	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4555	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4556	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4557	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4558	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4559	}
				4560
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4561	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4562	return MCDisassembler::Fail;
				4563	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4564	return MCDisassembler::Fail;
				4565	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4566	return MCDisassembler::Fail;
				4567	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				4568	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4569	Inst.addOperand(MCOperand::CreateImm(index));
				4570
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4571	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4572	}
				4573
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4574	static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4575	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4576	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4577
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4578	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4579	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4580	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4581	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4582	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4583
				4584	unsigned align = 0;
				4585	unsigned index = 0;
				4586	unsigned inc = 1;
				4587	switch (size) {
				4588	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4589	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4590	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4591	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4592	align = 4;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4593	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4594	break;
				4595	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4596	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4597	align = 8;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4598	index = fieldFromInstruction(Insn, 6, 2);
				4599	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4600	inc = 2;
				4601	break;
				4602	case 2:
Tim Northover	fb3cdd8	2012-09-06 15:17:49 +0000	[diff] [blame]	4603	switch (fieldFromInstruction(Insn, 4, 2)) {
				4604	case 0:
				4605	align = 0; break;
				4606	case 3:
				4607	return MCDisassembler::Fail;
				4608	default:
				4609	align = 4 << fieldFromInstruction(Insn, 4, 2); break;
				4610	}
				4611
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4612	index = fieldFromInstruction(Insn, 7, 1);
				4613	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4614	inc = 2;
				4615	break;
				4616	}
				4617
				4618	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4619	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4620	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4621	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4622	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4623	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4624	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4625	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4626	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4627	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4628	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4629	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4630	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4631	}
				4632
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4633	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4634	return MCDisassembler::Fail;
				4635	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4636	return MCDisassembler::Fail;
				4637	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4638	return MCDisassembler::Fail;
				4639	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				4640	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4641	Inst.addOperand(MCOperand::CreateImm(index));
				4642
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4643	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4644	}
				4645
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4646	static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4647	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4648	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4649	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4650	unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
				4651	unsigned Rm = fieldFromInstruction(Insn, 5, 1);
				4652	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				4653	Rm \|= fieldFromInstruction(Insn, 0, 4) << 1;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4654
				4655	if (Rt == 0xF \|\| Rt2 == 0xF \|\| Rm == 0x1F)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4656	S = MCDisassembler::SoftFail;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4657
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4658	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
				4659	return MCDisassembler::Fail;
				4660	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
				4661	return MCDisassembler::Fail;
				4662	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
				4663	return MCDisassembler::Fail;
				4664	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
				4665	return MCDisassembler::Fail;
				4666	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4667	return MCDisassembler::Fail;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4668
				4669	return S;
				4670	}
				4671
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4672	static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4673	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4674	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4675	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4676	unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
				4677	unsigned Rm = fieldFromInstruction(Insn, 5, 1);
				4678	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				4679	Rm \|= fieldFromInstruction(Insn, 0, 4) << 1;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4680
				4681	if (Rt == 0xF \|\| Rt2 == 0xF \|\| Rm == 0x1F)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4682	S = MCDisassembler::SoftFail;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4683
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4684	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
				4685	return MCDisassembler::Fail;
				4686	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
				4687	return MCDisassembler::Fail;
				4688	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
				4689	return MCDisassembler::Fail;
				4690	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
				4691	return MCDisassembler::Fail;
				4692	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4693	return MCDisassembler::Fail;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4694
				4695	return S;
				4696	}
Owen Anderson	eb1367b	2011-08-22 23:44:04 +0000	[diff] [blame]	4697
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4698	static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	4699	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4700	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4701	unsigned pred = fieldFromInstruction(Insn, 4, 4);
				4702	unsigned mask = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	4703
				4704	if (pred == 0xF) {
				4705	pred = 0xE;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4706	S = MCDisassembler::SoftFail;
Owen Anderson	5230041	2011-08-24 17:21:43 +0000	[diff] [blame]	4707	}
				4708
Amaury de la Vieuville	2f0ac8d	2013-06-24 09:11:45 +0000	[diff] [blame]	4709	if (mask == 0x0)
				4710	return MCDisassembler::Fail;
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	4711
				4712	Inst.addOperand(MCOperand::CreateImm(pred));
				4713	Inst.addOperand(MCOperand::CreateImm(mask));
Owen Anderson	37612a3	2011-08-24 22:40:22 +0000	[diff] [blame]	4714	return S;
				4715	}
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	4716
				4717	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4718	DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	4719	uint64_t Address, const void *Decoder) {
				4720	DecodeStatus S = MCDisassembler::Success;
				4721
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4722	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4723	unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
				4724	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4725	unsigned addr = fieldFromInstruction(Insn, 0, 8);
				4726	unsigned W = fieldFromInstruction(Insn, 21, 1);
				4727	unsigned U = fieldFromInstruction(Insn, 23, 1);
				4728	unsigned P = fieldFromInstruction(Insn, 24, 1);
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	4729	bool writeback = (W == 1) \| (P == 0);
				4730
				4731	addr \|= (U << 8) \| (Rn << 9);
				4732
				4733	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				4734	Check(S, MCDisassembler::SoftFail);
				4735	if (Rt == Rt2)
				4736	Check(S, MCDisassembler::SoftFail);
				4737
				4738	// Rt
				4739	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4740	return MCDisassembler::Fail;
				4741	// Rt2
				4742	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
				4743	return MCDisassembler::Fail;
				4744	// Writeback operand
				4745	if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4746	return MCDisassembler::Fail;
				4747	// addr
				4748	if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
				4749	return MCDisassembler::Fail;
				4750
				4751	return S;
				4752	}
				4753
				4754	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4755	DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	4756	uint64_t Address, const void *Decoder) {
				4757	DecodeStatus S = MCDisassembler::Success;
				4758
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4759	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4760	unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
				4761	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4762	unsigned addr = fieldFromInstruction(Insn, 0, 8);
				4763	unsigned W = fieldFromInstruction(Insn, 21, 1);
				4764	unsigned U = fieldFromInstruction(Insn, 23, 1);
				4765	unsigned P = fieldFromInstruction(Insn, 24, 1);
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	4766	bool writeback = (W == 1) \| (P == 0);
				4767
				4768	addr \|= (U << 8) \| (Rn << 9);
				4769
				4770	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				4771	Check(S, MCDisassembler::SoftFail);
				4772
				4773	// Writeback operand
				4774	if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4775	return MCDisassembler::Fail;
				4776	// Rt
				4777	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4778	return MCDisassembler::Fail;
				4779	// Rt2
				4780	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
				4781	return MCDisassembler::Fail;
				4782	// addr
				4783	if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
				4784	return MCDisassembler::Fail;
				4785
				4786	return S;
				4787	}
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	4788
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4789	static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	4790	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4791	unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
				4792	unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	4793	if (sign1 != sign2) return MCDisassembler::Fail;
				4794
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4795	unsigned Val = fieldFromInstruction(Insn, 0, 8);
				4796	Val \|= fieldFromInstruction(Insn, 12, 3) << 8;
				4797	Val \|= fieldFromInstruction(Insn, 26, 1) << 11;
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	4798	Val \|= sign1 << 12;
				4799	Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
				4800
				4801	return MCDisassembler::Success;
				4802	}
				4803
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4804	static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
Owen Anderson	f01e2de	2011-09-26 21:06:22 +0000	[diff] [blame]	4805	uint64_t Address,
				4806	const void *Decoder) {
				4807	DecodeStatus S = MCDisassembler::Success;
				4808
				4809	// Shift of "asr #32" is not allowed in Thumb2 mode.
				4810	if (Val == 0x20) S = MCDisassembler::SoftFail;
				4811	Inst.addOperand(MCOperand::CreateImm(Val));
				4812	return S;
				4813	}
				4814
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4815	static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Anderson	dde461c	2011-10-28 18:02:13 +0000	[diff] [blame]	4816	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4817	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4818	unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
				4819	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4820	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	dde461c	2011-10-28 18:02:13 +0000	[diff] [blame]	4821
				4822	if (pred == 0xF)
				4823	return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
				4824
				4825	DecodeStatus S = MCDisassembler::Success;
Silviu Baranga	ca45af9	2012-04-18 14:18:57 +0000	[diff] [blame]	4826
				4827	if (Rt == Rn \|\| Rn == Rt2)
				4828	S = MCDisassembler::SoftFail;
				4829
Owen Anderson	dde461c	2011-10-28 18:02:13 +0000	[diff] [blame]	4830	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				4831	return MCDisassembler::Fail;
				4832	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
				4833	return MCDisassembler::Fail;
				4834	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				4835	return MCDisassembler::Fail;
				4836	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4837	return MCDisassembler::Fail;
				4838
				4839	return S;
				4840	}
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	4841
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4842	static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	4843	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4844	unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
				4845	Vd \|= (fieldFromInstruction(Insn, 22, 1) << 4);
				4846	unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
				4847	Vm \|= (fieldFromInstruction(Insn, 5, 1) << 4);
				4848	unsigned imm = fieldFromInstruction(Insn, 16, 6);
				4849	unsigned cmode = fieldFromInstruction(Insn, 8, 4);
Amaury de la Vieuville	f4ec0c85	2013-06-08 13:54:05 +0000	[diff] [blame]	4850	unsigned op = fieldFromInstruction(Insn, 5, 1);
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	4851
				4852	DecodeStatus S = MCDisassembler::Success;
				4853
				4854	// VMOVv2f32 is ambiguous with these decodings.
Owen Anderson	05060f0	2011-11-15 20:30:41 +0000	[diff] [blame]	4855	if (!(imm & 0x38) && cmode == 0xF) {
Amaury de la Vieuville	f4ec0c85	2013-06-08 13:54:05 +0000	[diff] [blame]	4856	if (op == 1) return MCDisassembler::Fail;
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	4857	Inst.setOpcode(ARM::VMOVv2f32);
				4858	return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
				4859	}
				4860
Amaury de la Vieuville	ea7bb57	2013-06-08 13:29:11 +0000	[diff] [blame]	4861	if (!(imm & 0x20)) return MCDisassembler::Fail;
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	4862
				4863	if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
				4864	return MCDisassembler::Fail;
				4865	if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
				4866	return MCDisassembler::Fail;
				4867	Inst.addOperand(MCOperand::CreateImm(64 - imm));
				4868
				4869	return S;
				4870	}
				4871
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4872	static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	4873	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4874	unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
				4875	Vd \|= (fieldFromInstruction(Insn, 22, 1) << 4);
				4876	unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
				4877	Vm \|= (fieldFromInstruction(Insn, 5, 1) << 4);
				4878	unsigned imm = fieldFromInstruction(Insn, 16, 6);
				4879	unsigned cmode = fieldFromInstruction(Insn, 8, 4);
Amaury de la Vieuville	f4ec0c85	2013-06-08 13:54:05 +0000	[diff] [blame]	4880	unsigned op = fieldFromInstruction(Insn, 5, 1);
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	4881
				4882	DecodeStatus S = MCDisassembler::Success;
				4883
				4884	// VMOVv4f32 is ambiguous with these decodings.
				4885	if (!(imm & 0x38) && cmode == 0xF) {
Amaury de la Vieuville	f4ec0c85	2013-06-08 13:54:05 +0000	[diff] [blame]	4886	if (op == 1) return MCDisassembler::Fail;
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	4887	Inst.setOpcode(ARM::VMOVv4f32);
				4888	return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
				4889	}
				4890
Amaury de la Vieuville	ea7bb57	2013-06-08 13:29:11 +0000	[diff] [blame]	4891	if (!(imm & 0x20)) return MCDisassembler::Fail;
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	4892
				4893	if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
				4894	return MCDisassembler::Fail;
				4895	if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
				4896	return MCDisassembler::Fail;
				4897	Inst.addOperand(MCOperand::CreateImm(64 - imm));
				4898
				4899	return S;
				4900	}
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	4901
Quentin Colombet	6f03f62	2013-04-17 18:46:12 +0000	[diff] [blame]	4902	static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address,
				4903	const void *Decoder)
				4904	{
				4905	unsigned Imm = fieldFromInstruction(Insn, 0, 3);
				4906	if (Imm > 4) return MCDisassembler::Fail;
				4907	Inst.addOperand(MCOperand::CreateImm(Imm));
				4908	return MCDisassembler::Success;
				4909	}
				4910
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4911	static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	4912	uint64_t Address, const void *Decoder) {
				4913	DecodeStatus S = MCDisassembler::Success;
				4914
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4915	unsigned Rn = fieldFromInstruction(Val, 16, 4);
				4916	unsigned Rt = fieldFromInstruction(Val, 12, 4);
				4917	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				4918	Rm \|= (fieldFromInstruction(Val, 23, 1) << 4);
				4919	unsigned Cond = fieldFromInstruction(Val, 28, 4);
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	4920
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4921	if (fieldFromInstruction(Val, 8, 4) != 0 \|\| Rn == Rt)
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	4922	S = MCDisassembler::SoftFail;
				4923
				4924	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				4925	return MCDisassembler::Fail;
				4926	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				4927	return MCDisassembler::Fail;
				4928	if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
				4929	return MCDisassembler::Fail;
				4930	if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
				4931	return MCDisassembler::Fail;
				4932	if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
				4933	return MCDisassembler::Fail;
				4934
				4935	return S;
				4936	}
				4937
Silviu Baranga	41f1fcd	2012-04-18 13:12:50 +0000	[diff] [blame]	4938	static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
				4939	uint64_t Address, const void *Decoder) {
				4940
				4941	DecodeStatus S = MCDisassembler::Success;
				4942
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4943	unsigned CRm = fieldFromInstruction(Val, 0, 4);
				4944	unsigned opc1 = fieldFromInstruction(Val, 4, 4);
				4945	unsigned cop = fieldFromInstruction(Val, 8, 4);
				4946	unsigned Rt = fieldFromInstruction(Val, 12, 4);
				4947	unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
Silviu Baranga	41f1fcd	2012-04-18 13:12:50 +0000	[diff] [blame]	4948
				4949	if ((cop & ~0x1) == 0xa)
				4950	return MCDisassembler::Fail;
				4951
				4952	if (Rt == Rt2)
				4953	S = MCDisassembler::SoftFail;
				4954
				4955	Inst.addOperand(MCOperand::CreateImm(cop));
				4956	Inst.addOperand(MCOperand::CreateImm(opc1));
				4957	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				4958	return MCDisassembler::Fail;
				4959	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
				4960	return MCDisassembler::Fail;
				4961	Inst.addOperand(MCOperand::CreateImm(CRm));
				4962
				4963	return S;
				4964	}
				4965