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Andrea Di Biagio821f6502018-04-10 14:55:14 +00001//===--------------------- DispatchStatistics.cpp ---------------------*- C++
2//-*-===//
3//
4// The LLVM Compiler Infrastructure
5//
6// This file is distributed under the University of Illinois Open Source
7// License. See LICENSE.TXT for details.
8//
9//===----------------------------------------------------------------------===//
10/// \file
11///
12/// This file implements the DispatchStatistics interface.
13///
14//===----------------------------------------------------------------------===//
15
16#include "DispatchStatistics.h"
17#include "llvm/Support/Format.h"
18
19using namespace llvm;
20
21namespace mca {
22
Andrea Di Biagio074ff7c2018-04-11 12:31:44 +000023void DispatchStatistics::onStallEvent(const HWStallEvent &Event) {
24 if (Event.Type < HWStallEvent::LastGenericEvent)
25 HWStalls[Event.Type]++;
26}
27
Andrea Di Biagio821f6502018-04-10 14:55:14 +000028void DispatchStatistics::onInstructionEvent(const HWInstructionEvent &Event) {
29 if (Event.Type == HWInstructionEvent::Dispatched)
30 ++NumDispatched;
31}
32
33void DispatchStatistics::printDispatchHistogram(llvm::raw_ostream &OS) const {
34 std::string Buffer;
35 raw_string_ostream TempStream(Buffer);
36 TempStream << "\n\nDispatch Logic - "
37 << "number of cycles where we saw N instructions dispatched:\n";
38 TempStream << "[# dispatched], [# cycles]\n";
39 for (const std::pair<unsigned, unsigned> &Entry : DispatchGroupSizePerCycle) {
40 TempStream << " " << Entry.first << ", " << Entry.second
41 << " ("
42 << format("%.1f", ((double)Entry.second / NumCycles) * 100.0)
43 << "%)\n";
44 }
45
46 TempStream.flush();
47 OS << Buffer;
48}
49
50void DispatchStatistics::printDispatchStalls(raw_ostream &OS) const {
51 std::string Buffer;
52 raw_string_ostream TempStream(Buffer);
53 TempStream << "\n\nDynamic Dispatch Stall Cycles:\n";
54 TempStream << "RAT - Register unavailable: "
55 << HWStalls[HWStallEvent::RegisterFileStall];
56 TempStream << "\nRCU - Retire tokens unavailable: "
57 << HWStalls[HWStallEvent::RetireControlUnitStall];
58 TempStream << "\nSCHEDQ - Scheduler full: "
59 << HWStalls[HWStallEvent::SchedulerQueueFull];
60 TempStream << "\nLQ - Load queue full: "
61 << HWStalls[HWStallEvent::LoadQueueFull];
62 TempStream << "\nSQ - Store queue full: "
63 << HWStalls[HWStallEvent::StoreQueueFull];
64 TempStream << "\nGROUP - Static restrictions on the dispatch group: "
65 << HWStalls[HWStallEvent::DispatchGroupStall];
66 TempStream << '\n';
67 TempStream.flush();
68 OS << Buffer;
69}
70
71} // namespace mca