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gerrit-public.fairphone.software / toolchain / llvm-project / e493f177eeee84a9c6000ca7c92499233490f1d1 / . / llvm / lib / Target / AArch64 / Disassembler / AArch64Disassembler.cpp
blob: f522ca59a9a0248729408cdd3acc661c8dd580ae [file] [log] [blame]
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1//===- AArch64Disassembler.cpp - Disassembler for AArch64 -------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10//
11//===----------------------------------------------------------------------===//
12
13#include "AArch64Disassembler.h"
14#include "AArch64ExternalSymbolizer.h"
15#include "AArch64Subtarget.h"
16#include "MCTargetDesc/AArch64AddressingModes.h"
17#include "Utils/AArch64BaseInfo.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]18#include "llvm/MC/MCFixedLenDisassembler.h"
Benjamin Kramer1f8930e2014-07-25 11:42:14 +0000[diff] [blame]19#include "llvm/MC/MCInst.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]20#include "llvm/Support/Debug.h"
Benjamin Kramer1f8930e2014-07-25 11:42:14 +0000[diff] [blame]21#include "llvm/Support/ErrorHandling.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]22#include "llvm/Support/MemoryObject.h"
23#include "llvm/Support/TargetRegistry.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]24
25using namespace llvm;
26
27#define DEBUG_TYPE "aarch64-disassembler"
28
29// Pull DecodeStatus and its enum values into the global namespace.
30typedef llvm::MCDisassembler::DecodeStatus DecodeStatus;
31
32// Forward declare these because the autogenerated code will reference them.
33// Definitions are further down.
34static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst,
35 unsigned RegNo, uint64_t Address,
36 const void *Decoder);
37static DecodeStatus DecodeFPR128_loRegisterClass(llvm::MCInst &Inst,
38 unsigned RegNo,
39 uint64_t Address,
40 const void *Decoder);
41static DecodeStatus DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
42 uint64_t Address,
43 const void *Decoder);
44static DecodeStatus DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
45 uint64_t Address,
46 const void *Decoder);
47static DecodeStatus DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
48 uint64_t Address,
49 const void *Decoder);
50static DecodeStatus DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
51 uint64_t Address,
52 const void *Decoder);
53static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
54 uint64_t Address,
55 const void *Decoder);
56static DecodeStatus DecodeGPR64spRegisterClass(llvm::MCInst &Inst,
57 unsigned RegNo, uint64_t Address,
58 const void *Decoder);
59static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
60 uint64_t Address,
61 const void *Decoder);
62static DecodeStatus DecodeGPR32spRegisterClass(llvm::MCInst &Inst,
63 unsigned RegNo, uint64_t Address,
64 const void *Decoder);
65static DecodeStatus DecodeQQRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
66 uint64_t Address,
67 const void *Decoder);
68static DecodeStatus DecodeQQQRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
69 uint64_t Address,
70 const void *Decoder);
71static DecodeStatus DecodeQQQQRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
72 uint64_t Address,
73 const void *Decoder);
74static DecodeStatus DecodeDDRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
75 uint64_t Address,
76 const void *Decoder);
77static DecodeStatus DecodeDDDRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
78 uint64_t Address,
79 const void *Decoder);
80static DecodeStatus DecodeDDDDRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
81 uint64_t Address,
82 const void *Decoder);
83
84static DecodeStatus DecodeFixedPointScaleImm32(llvm::MCInst &Inst, unsigned Imm,
85 uint64_t Address,
86 const void *Decoder);
87static DecodeStatus DecodeFixedPointScaleImm64(llvm::MCInst &Inst, unsigned Imm,
88 uint64_t Address,
89 const void *Decoder);
90static DecodeStatus DecodePCRelLabel19(llvm::MCInst &Inst, unsigned Imm,
91 uint64_t Address, const void *Decoder);
92static DecodeStatus DecodeMemExtend(llvm::MCInst &Inst, unsigned Imm,
93 uint64_t Address, const void *Decoder);
94static DecodeStatus DecodeMRSSystemRegister(llvm::MCInst &Inst, unsigned Imm,
95 uint64_t Address, const void *Decoder);
96static DecodeStatus DecodeMSRSystemRegister(llvm::MCInst &Inst, unsigned Imm,
97 uint64_t Address, const void *Decoder);
98static DecodeStatus DecodeThreeAddrSRegInstruction(llvm::MCInst &Inst,
99 uint32_t insn,
100 uint64_t Address,
101 const void *Decoder);
102static DecodeStatus DecodeMoveImmInstruction(llvm::MCInst &Inst, uint32_t insn,
103 uint64_t Address,
104 const void *Decoder);
105static DecodeStatus DecodeUnsignedLdStInstruction(llvm::MCInst &Inst,
106 uint32_t insn,
107 uint64_t Address,
108 const void *Decoder);
109static DecodeStatus DecodeSignedLdStInstruction(llvm::MCInst &Inst,
110 uint32_t insn, uint64_t Address,
111 const void *Decoder);
112static DecodeStatus DecodeExclusiveLdStInstruction(llvm::MCInst &Inst,
113 uint32_t insn,
114 uint64_t Address,
115 const void *Decoder);
116static DecodeStatus DecodePairLdStInstruction(llvm::MCInst &Inst, uint32_t insn,
117 uint64_t Address,
118 const void *Decoder);
119static DecodeStatus DecodeAddSubERegInstruction(llvm::MCInst &Inst,
120 uint32_t insn, uint64_t Address,
121 const void *Decoder);
122static DecodeStatus DecodeLogicalImmInstruction(llvm::MCInst &Inst,
123 uint32_t insn, uint64_t Address,
124 const void *Decoder);
125static DecodeStatus DecodeModImmInstruction(llvm::MCInst &Inst, uint32_t insn,
126 uint64_t Address,
127 const void *Decoder);
128static DecodeStatus DecodeModImmTiedInstruction(llvm::MCInst &Inst,
129 uint32_t insn, uint64_t Address,
130 const void *Decoder);
131static DecodeStatus DecodeAdrInstruction(llvm::MCInst &Inst, uint32_t insn,
132 uint64_t Address, const void *Decoder);
133static DecodeStatus DecodeBaseAddSubImm(llvm::MCInst &Inst, uint32_t insn,
134 uint64_t Address, const void *Decoder);
135static DecodeStatus DecodeUnconditionalBranch(llvm::MCInst &Inst, uint32_t insn,
136 uint64_t Address,
137 const void *Decoder);
138static DecodeStatus DecodeSystemPStateInstruction(llvm::MCInst &Inst,
139 uint32_t insn,
140 uint64_t Address,
141 const void *Decoder);
142static DecodeStatus DecodeTestAndBranch(llvm::MCInst &Inst, uint32_t insn,
143 uint64_t Address, const void *Decoder);
144
145static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn,
146 uint64_t Address,
147 const void *Decoder);
148static DecodeStatus DecodeVecShiftR64Imm(llvm::MCInst &Inst, unsigned Imm,
149 uint64_t Addr, const void *Decoder);
150static DecodeStatus DecodeVecShiftR64ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
151 uint64_t Addr,
152 const void *Decoder);
153static DecodeStatus DecodeVecShiftR32Imm(llvm::MCInst &Inst, unsigned Imm,
154 uint64_t Addr, const void *Decoder);
155static DecodeStatus DecodeVecShiftR32ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
156 uint64_t Addr,
157 const void *Decoder);
158static DecodeStatus DecodeVecShiftR16Imm(llvm::MCInst &Inst, unsigned Imm,
159 uint64_t Addr, const void *Decoder);
160static DecodeStatus DecodeVecShiftR16ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
161 uint64_t Addr,
162 const void *Decoder);
163static DecodeStatus DecodeVecShiftR8Imm(llvm::MCInst &Inst, unsigned Imm,
164 uint64_t Addr, const void *Decoder);
165static DecodeStatus DecodeVecShiftL64Imm(llvm::MCInst &Inst, unsigned Imm,
166 uint64_t Addr, const void *Decoder);
167static DecodeStatus DecodeVecShiftL32Imm(llvm::MCInst &Inst, unsigned Imm,
168 uint64_t Addr, const void *Decoder);
169static DecodeStatus DecodeVecShiftL16Imm(llvm::MCInst &Inst, unsigned Imm,
170 uint64_t Addr, const void *Decoder);
171static DecodeStatus DecodeVecShiftL8Imm(llvm::MCInst &Inst, unsigned Imm,
172 uint64_t Addr, const void *Decoder);
173
174static bool Check(DecodeStatus &Out, DecodeStatus In) {
175 switch (In) {
176 case MCDisassembler::Success:
177 // Out stays the same.
178 return true;
179 case MCDisassembler::SoftFail:
180 Out = In;
181 return true;
182 case MCDisassembler::Fail:
183 Out = In;
184 return false;
185 }
186 llvm_unreachable("Invalid DecodeStatus!");
187}
188
189#include "AArch64GenDisassemblerTables.inc"
190#include "AArch64GenInstrInfo.inc"
191
192#define Success llvm::MCDisassembler::Success
193#define Fail llvm::MCDisassembler::Fail
194#define SoftFail llvm::MCDisassembler::SoftFail
195
196static MCDisassembler *createAArch64Disassembler(const Target &T,
197 const MCSubtargetInfo &STI,
198 MCContext &Ctx) {
199 return new AArch64Disassembler(STI, Ctx);
200}
201
202DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
203 const MemoryObject &Region,
204 uint64_t Address,
205 raw_ostream &os,
206 raw_ostream &cs) const {
207 CommentStream = &cs;
208
209 uint8_t bytes[4];
210
211 Size = 0;
212 // We want to read exactly 4 bytes of data.
213 if (Region.readBytes(Address, 4, (uint8_t *)bytes) == -1)
214 return Fail;
215 Size = 4;
216
217 // Encoded as a small-endian 32-bit word in the stream.
218 uint32_t insn =
219 (bytes[3] << 24) | (bytes[2] << 16) | (bytes[1] << 8) | (bytes[0] << 0);
220
221 // Calling the auto-generated decoder function.
222 return decodeInstruction(DecoderTable32, MI, insn, Address, this, STI);
223}
224
225static MCSymbolizer *
226createAArch64ExternalSymbolizer(StringRef TT, LLVMOpInfoCallback GetOpInfo,
227 LLVMSymbolLookupCallback SymbolLookUp,
228 void *DisInfo, MCContext *Ctx,
229 MCRelocationInfo *RelInfo) {
230 return new llvm::AArch64ExternalSymbolizer(
231 *Ctx,
232 std::unique_ptr<MCRelocationInfo>(RelInfo),
233 GetOpInfo, SymbolLookUp, DisInfo);
234}
235
236extern "C" void LLVMInitializeAArch64Disassembler() {
237 TargetRegistry::RegisterMCDisassembler(TheAArch64leTarget,
238 createAArch64Disassembler);
239 TargetRegistry::RegisterMCDisassembler(TheAArch64beTarget,
240 createAArch64Disassembler);
241 TargetRegistry::RegisterMCSymbolizer(TheAArch64leTarget,
242 createAArch64ExternalSymbolizer);
243 TargetRegistry::RegisterMCSymbolizer(TheAArch64beTarget,
244 createAArch64ExternalSymbolizer);
245
Tim Northover35910d72014-07-23 12:58:11 +0000[diff] [blame]246 TargetRegistry::RegisterMCDisassembler(TheARM64Target,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]247 createAArch64Disassembler);
Tim Northover35910d72014-07-23 12:58:11 +0000[diff] [blame]248 TargetRegistry::RegisterMCSymbolizer(TheARM64Target,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]249 createAArch64ExternalSymbolizer);
250}
251
252static const unsigned FPR128DecoderTable[] = {
253 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
254 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
255 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
256 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
257 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
258 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
259 AArch64::Q30, AArch64::Q31
260};
261
262static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo,
263 uint64_t Addr,
264 const void *Decoder) {
265 if (RegNo > 31)
266 return Fail;
267
268 unsigned Register = FPR128DecoderTable[RegNo];
269 Inst.addOperand(MCOperand::CreateReg(Register));
270 return Success;
271}
272
273static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo,
274 uint64_t Addr,
275 const void *Decoder) {
276 if (RegNo > 15)
277 return Fail;
278 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder);
279}
280
281static const unsigned FPR64DecoderTable[] = {
282 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4,
283 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9,
284 AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14,
285 AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19,
286 AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24,
287 AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29,
288 AArch64::D30, AArch64::D31
289};
290
291static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
292 uint64_t Addr,
293 const void *Decoder) {
294 if (RegNo > 31)
295 return Fail;
296
297 unsigned Register = FPR64DecoderTable[RegNo];
298 Inst.addOperand(MCOperand::CreateReg(Register));
299 return Success;
300}
301
302static const unsigned FPR32DecoderTable[] = {
303 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4,
304 AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9,
305 AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14,
306 AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19,
307 AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24,
308 AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29,
309 AArch64::S30, AArch64::S31
310};
311
312static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
313 uint64_t Addr,
314 const void *Decoder) {
315 if (RegNo > 31)
316 return Fail;
317
318 unsigned Register = FPR32DecoderTable[RegNo];
319 Inst.addOperand(MCOperand::CreateReg(Register));
320 return Success;
321}
322
323static const unsigned FPR16DecoderTable[] = {
324 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4,
325 AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9,
326 AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14,
327 AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19,
328 AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24,
329 AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29,
330 AArch64::H30, AArch64::H31
331};
332
333static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
334 uint64_t Addr,
335 const void *Decoder) {
336 if (RegNo > 31)
337 return Fail;
338
339 unsigned Register = FPR16DecoderTable[RegNo];
340 Inst.addOperand(MCOperand::CreateReg(Register));
341 return Success;
342}
343
344static const unsigned FPR8DecoderTable[] = {
345 AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4,
346 AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9,
347 AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14,
348 AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19,
349 AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24,
350 AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29,
351 AArch64::B30, AArch64::B31
352};
353
354static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
355 uint64_t Addr,
356 const void *Decoder) {
357 if (RegNo > 31)
358 return Fail;
359
360 unsigned Register = FPR8DecoderTable[RegNo];
361 Inst.addOperand(MCOperand::CreateReg(Register));
362 return Success;
363}
364
365static const unsigned GPR64DecoderTable[] = {
366 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4,
367 AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9,
368 AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14,
369 AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19,
370 AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24,
371 AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP,
372 AArch64::LR, AArch64::XZR
373};
374
375static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
376 uint64_t Addr,
377 const void *Decoder) {
378 if (RegNo > 31)
379 return Fail;
380
381 unsigned Register = GPR64DecoderTable[RegNo];
382 Inst.addOperand(MCOperand::CreateReg(Register));
383 return Success;
384}
385
386static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo,
387 uint64_t Addr,
388 const void *Decoder) {
389 if (RegNo > 31)
390 return Fail;
391 unsigned Register = GPR64DecoderTable[RegNo];
392 if (Register == AArch64::XZR)
393 Register = AArch64::SP;
394 Inst.addOperand(MCOperand::CreateReg(Register));
395 return Success;
396}
397
398static const unsigned GPR32DecoderTable[] = {
399 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4,
400 AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9,
401 AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14,
402 AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19,
403 AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24,
404 AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29,
405 AArch64::W30, AArch64::WZR
406};
407
408static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
409 uint64_t Addr,
410 const void *Decoder) {
411 if (RegNo > 31)
412 return Fail;
413
414 unsigned Register = GPR32DecoderTable[RegNo];
415 Inst.addOperand(MCOperand::CreateReg(Register));
416 return Success;
417}
418
419static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo,
420 uint64_t Addr,
421 const void *Decoder) {
422 if (RegNo > 31)
423 return Fail;
424
425 unsigned Register = GPR32DecoderTable[RegNo];
426 if (Register == AArch64::WZR)
427 Register = AArch64::WSP;
428 Inst.addOperand(MCOperand::CreateReg(Register));
429 return Success;
430}
431
432static const unsigned VectorDecoderTable[] = {
433 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
434 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
435 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
436 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
437 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
438 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
439 AArch64::Q30, AArch64::Q31
440};
441
442static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo,
443 uint64_t Addr,
444 const void *Decoder) {
445 if (RegNo > 31)
446 return Fail;
447
448 unsigned Register = VectorDecoderTable[RegNo];
449 Inst.addOperand(MCOperand::CreateReg(Register));
450 return Success;
451}
452
453static const unsigned QQDecoderTable[] = {
454 AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4,
455 AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8,
456 AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12,
457 AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16,
458 AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20,
459 AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24,
460 AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28,
461 AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0
462};
463
464static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
465 uint64_t Addr, const void *Decoder) {
466 if (RegNo > 31)
467 return Fail;
468 unsigned Register = QQDecoderTable[RegNo];
469 Inst.addOperand(MCOperand::CreateReg(Register));
470 return Success;
471}
472
473static const unsigned QQQDecoderTable[] = {
474 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4,
475 AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7,
476 AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10,
477 AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13,
478 AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16,
479 AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19,
480 AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22,
481 AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25,
482 AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28,
483 AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31,
484 AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1
485};
486
487static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
488 uint64_t Addr, const void *Decoder) {
489 if (RegNo > 31)
490 return Fail;
491 unsigned Register = QQQDecoderTable[RegNo];
492 Inst.addOperand(MCOperand::CreateReg(Register));
493 return Success;
494}
495
496static const unsigned QQQQDecoderTable[] = {
497 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5,
498 AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8,
499 AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11,
500 AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14,
501 AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17,
502 AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20,
503 AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23,
504 AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26,
505 AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29,
506 AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0,
507 AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2
508};
509
510static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
511 uint64_t Addr,
512 const void *Decoder) {
513 if (RegNo > 31)
514 return Fail;
515 unsigned Register = QQQQDecoderTable[RegNo];
516 Inst.addOperand(MCOperand::CreateReg(Register));
517 return Success;
518}
519
520static const unsigned DDDecoderTable[] = {
521 AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4,
522 AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8,
523 AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12,
524 AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16,
525 AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20,
526 AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24,
527 AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28,
528 AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0
529};
530
531static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
532 uint64_t Addr, const void *Decoder) {
533 if (RegNo > 31)
534 return Fail;
535 unsigned Register = DDDecoderTable[RegNo];
536 Inst.addOperand(MCOperand::CreateReg(Register));
537 return Success;
538}
539
540static const unsigned DDDDecoderTable[] = {
541 AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4,
542 AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7,
543 AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10,
544 AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13,
545 AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16,
546 AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19,
547 AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22,
548 AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25,
549 AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28,
550 AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31,
551 AArch64::D30_D31_D0, AArch64::D31_D0_D1
552};
553
554static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
555 uint64_t Addr, const void *Decoder) {
556 if (RegNo > 31)
557 return Fail;
558 unsigned Register = DDDDecoderTable[RegNo];
559 Inst.addOperand(MCOperand::CreateReg(Register));
560 return Success;
561}
562
563static const unsigned DDDDDecoderTable[] = {
564 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5,
565 AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8,
566 AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11,
567 AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14,
568 AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17,
569 AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20,
570 AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23,
571 AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26,
572 AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29,
573 AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0,
574 AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2
575};
576
577static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
578 uint64_t Addr,
579 const void *Decoder) {
580 if (RegNo > 31)
581 return Fail;
582 unsigned Register = DDDDDecoderTable[RegNo];
583 Inst.addOperand(MCOperand::CreateReg(Register));
584 return Success;
585}
586
587static DecodeStatus DecodeFixedPointScaleImm32(llvm::MCInst &Inst, unsigned Imm,
588 uint64_t Addr,
589 const void *Decoder) {
590 // scale{5} is asserted as 1 in tblgen.
Tom Coxon2c13e712014-09-30 16:23:16 +0000[diff] [blame]591 Imm |= 0x20;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]592 Inst.addOperand(MCOperand::CreateImm(64 - Imm));
593 return Success;
594}
595
596static DecodeStatus DecodeFixedPointScaleImm64(llvm::MCInst &Inst, unsigned Imm,
597 uint64_t Addr,
598 const void *Decoder) {
599 Inst.addOperand(MCOperand::CreateImm(64 - Imm));
600 return Success;
601}
602
603static DecodeStatus DecodePCRelLabel19(llvm::MCInst &Inst, unsigned Imm,
604 uint64_t Addr, const void *Decoder) {
605 int64_t ImmVal = Imm;
606 const AArch64Disassembler *Dis =
607 static_cast<const AArch64Disassembler *>(Decoder);
608
609 // Sign-extend 19-bit immediate.
610 if (ImmVal & (1 << (19 - 1)))
611 ImmVal |= ~((1LL << 19) - 1);
612
Alexey Samsonov729b12e2014-09-02 16:19:41 +0000[diff] [blame]613 if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]614 Inst.getOpcode() != AArch64::LDRXl, 0, 4))
615 Inst.addOperand(MCOperand::CreateImm(ImmVal));
616 return Success;
617}
618
619static DecodeStatus DecodeMemExtend(llvm::MCInst &Inst, unsigned Imm,
620 uint64_t Address, const void *Decoder) {
621 Inst.addOperand(MCOperand::CreateImm((Imm >> 1) & 1));
622 Inst.addOperand(MCOperand::CreateImm(Imm & 1));
623 return Success;
624}
625
626static DecodeStatus DecodeMRSSystemRegister(llvm::MCInst &Inst, unsigned Imm,
627 uint64_t Address,
628 const void *Decoder) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]629 Inst.addOperand(MCOperand::CreateImm(Imm));
630
Tom Coxone493f172014-10-01 10:13:59 +0000[diff] [blame^]631 // Every system register in the encoding space is valid with the syntax
632 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds.
633 return Success;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]634}
635
636static DecodeStatus DecodeMSRSystemRegister(llvm::MCInst &Inst, unsigned Imm,
637 uint64_t Address,
638 const void *Decoder) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]639 Inst.addOperand(MCOperand::CreateImm(Imm));
640
Tom Coxone493f172014-10-01 10:13:59 +0000[diff] [blame^]641 return Success;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]642}
643
644static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn,
645 uint64_t Address,
646 const void *Decoder) {
647 // This decoder exists to add the dummy Lane operand to the MCInst, which must
648 // be 1 in assembly but has no other real manifestation.
649 unsigned Rd = fieldFromInstruction(Insn, 0, 5);
650 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
651 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
652
653 if (IsToVec) {
654 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
655 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
656 } else {
657 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
658 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
659 }
660
661 // Add the lane
662 Inst.addOperand(MCOperand::CreateImm(1));
663
664 return Success;
665}
666
667static DecodeStatus DecodeVecShiftRImm(llvm::MCInst &Inst, unsigned Imm,
668 unsigned Add) {
669 Inst.addOperand(MCOperand::CreateImm(Add - Imm));
670 return Success;
671}
672
673static DecodeStatus DecodeVecShiftLImm(llvm::MCInst &Inst, unsigned Imm,
674 unsigned Add) {
675 Inst.addOperand(MCOperand::CreateImm((Imm + Add) & (Add - 1)));
676 return Success;
677}
678
679static DecodeStatus DecodeVecShiftR64Imm(llvm::MCInst &Inst, unsigned Imm,
680 uint64_t Addr, const void *Decoder) {
681 return DecodeVecShiftRImm(Inst, Imm, 64);
682}
683
684static DecodeStatus DecodeVecShiftR64ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
685 uint64_t Addr,
686 const void *Decoder) {
687 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64);
688}
689
690static DecodeStatus DecodeVecShiftR32Imm(llvm::MCInst &Inst, unsigned Imm,
691 uint64_t Addr, const void *Decoder) {
692 return DecodeVecShiftRImm(Inst, Imm, 32);
693}
694
695static DecodeStatus DecodeVecShiftR32ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
696 uint64_t Addr,
697 const void *Decoder) {
698 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32);
699}
700
701static DecodeStatus DecodeVecShiftR16Imm(llvm::MCInst &Inst, unsigned Imm,
702 uint64_t Addr, const void *Decoder) {
703 return DecodeVecShiftRImm(Inst, Imm, 16);
704}
705
706static DecodeStatus DecodeVecShiftR16ImmNarrow(llvm::MCInst &Inst, unsigned Imm,
707 uint64_t Addr,
708 const void *Decoder) {
709 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16);
710}
711
712static DecodeStatus DecodeVecShiftR8Imm(llvm::MCInst &Inst, unsigned Imm,
713 uint64_t Addr, const void *Decoder) {
714 return DecodeVecShiftRImm(Inst, Imm, 8);
715}
716
717static DecodeStatus DecodeVecShiftL64Imm(llvm::MCInst &Inst, unsigned Imm,
718 uint64_t Addr, const void *Decoder) {
719 return DecodeVecShiftLImm(Inst, Imm, 64);
720}
721
722static DecodeStatus DecodeVecShiftL32Imm(llvm::MCInst &Inst, unsigned Imm,
723 uint64_t Addr, const void *Decoder) {
724 return DecodeVecShiftLImm(Inst, Imm, 32);
725}
726
727static DecodeStatus DecodeVecShiftL16Imm(llvm::MCInst &Inst, unsigned Imm,
728 uint64_t Addr, const void *Decoder) {
729 return DecodeVecShiftLImm(Inst, Imm, 16);
730}
731
732static DecodeStatus DecodeVecShiftL8Imm(llvm::MCInst &Inst, unsigned Imm,
733 uint64_t Addr, const void *Decoder) {
734 return DecodeVecShiftLImm(Inst, Imm, 8);
735}
736
737static DecodeStatus DecodeThreeAddrSRegInstruction(llvm::MCInst &Inst,
738 uint32_t insn, uint64_t Addr,
739 const void *Decoder) {
740 unsigned Rd = fieldFromInstruction(insn, 0, 5);
741 unsigned Rn = fieldFromInstruction(insn, 5, 5);
742 unsigned Rm = fieldFromInstruction(insn, 16, 5);
743 unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
744 unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
745 unsigned shift = (shiftHi << 6) | shiftLo;
746 switch (Inst.getOpcode()) {
747 default:
748 return Fail;
749 case AArch64::ADDWrs:
750 case AArch64::ADDSWrs:
751 case AArch64::SUBWrs:
752 case AArch64::SUBSWrs:
753 // if shift == '11' then ReservedValue()
754 if (shiftHi == 0x3)
755 return Fail;
756 // Deliberate fallthrough
757 case AArch64::ANDWrs:
758 case AArch64::ANDSWrs:
759 case AArch64::BICWrs:
760 case AArch64::BICSWrs:
761 case AArch64::ORRWrs:
762 case AArch64::ORNWrs:
763 case AArch64::EORWrs:
764 case AArch64::EONWrs: {
765 // if sf == '0' and imm6<5> == '1' then ReservedValue()
766 if (shiftLo >> 5 == 1)
767 return Fail;
768 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
769 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
770 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
771 break;
772 }
773 case AArch64::ADDXrs:
774 case AArch64::ADDSXrs:
775 case AArch64::SUBXrs:
776 case AArch64::SUBSXrs:
777 // if shift == '11' then ReservedValue()
778 if (shiftHi == 0x3)
779 return Fail;
780 // Deliberate fallthrough
781 case AArch64::ANDXrs:
782 case AArch64::ANDSXrs:
783 case AArch64::BICXrs:
784 case AArch64::BICSXrs:
785 case AArch64::ORRXrs:
786 case AArch64::ORNXrs:
787 case AArch64::EORXrs:
788 case AArch64::EONXrs:
789 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
790 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
791 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
792 break;
793 }
794
795 Inst.addOperand(MCOperand::CreateImm(shift));
796 return Success;
797}
798
799static DecodeStatus DecodeMoveImmInstruction(llvm::MCInst &Inst, uint32_t insn,
800 uint64_t Addr,
801 const void *Decoder) {
802 unsigned Rd = fieldFromInstruction(insn, 0, 5);
803 unsigned imm = fieldFromInstruction(insn, 5, 16);
804 unsigned shift = fieldFromInstruction(insn, 21, 2);
805 shift <<= 4;
806 switch (Inst.getOpcode()) {
807 default:
808 return Fail;
809 case AArch64::MOVZWi:
810 case AArch64::MOVNWi:
811 case AArch64::MOVKWi:
812 if (shift & (1U << 5))
813 return Fail;
814 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
815 break;
816 case AArch64::MOVZXi:
817 case AArch64::MOVNXi:
818 case AArch64::MOVKXi:
819 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
820 break;
821 }
822
823 if (Inst.getOpcode() == AArch64::MOVKWi ||
824 Inst.getOpcode() == AArch64::MOVKXi)
825 Inst.addOperand(Inst.getOperand(0));
826
827 Inst.addOperand(MCOperand::CreateImm(imm));
828 Inst.addOperand(MCOperand::CreateImm(shift));
829 return Success;
830}
831
832static DecodeStatus DecodeUnsignedLdStInstruction(llvm::MCInst &Inst,
833 uint32_t insn, uint64_t Addr,
834 const void *Decoder) {
835 unsigned Rt = fieldFromInstruction(insn, 0, 5);
836 unsigned Rn = fieldFromInstruction(insn, 5, 5);
837 unsigned offset = fieldFromInstruction(insn, 10, 12);
838 const AArch64Disassembler *Dis =
839 static_cast<const AArch64Disassembler *>(Decoder);
840
841 switch (Inst.getOpcode()) {
842 default:
843 return Fail;
844 case AArch64::PRFMui:
845 // Rt is an immediate in prefetch.
846 Inst.addOperand(MCOperand::CreateImm(Rt));
847 break;
848 case AArch64::STRBBui:
849 case AArch64::LDRBBui:
850 case AArch64::LDRSBWui:
851 case AArch64::STRHHui:
852 case AArch64::LDRHHui:
853 case AArch64::LDRSHWui:
854 case AArch64::STRWui:
855 case AArch64::LDRWui:
856 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
857 break;
858 case AArch64::LDRSBXui:
859 case AArch64::LDRSHXui:
860 case AArch64::LDRSWui:
861 case AArch64::STRXui:
862 case AArch64::LDRXui:
863 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
864 break;
865 case AArch64::LDRQui:
866 case AArch64::STRQui:
867 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
868 break;
869 case AArch64::LDRDui:
870 case AArch64::STRDui:
871 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
872 break;
873 case AArch64::LDRSui:
874 case AArch64::STRSui:
875 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
876 break;
877 case AArch64::LDRHui:
878 case AArch64::STRHui:
879 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
880 break;
881 case AArch64::LDRBui:
882 case AArch64::STRBui:
883 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
884 break;
885 }
886
887 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
888 if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4))
889 Inst.addOperand(MCOperand::CreateImm(offset));
890 return Success;
891}
892
893static DecodeStatus DecodeSignedLdStInstruction(llvm::MCInst &Inst,
894 uint32_t insn, uint64_t Addr,
895 const void *Decoder) {
896 unsigned Rt = fieldFromInstruction(insn, 0, 5);
897 unsigned Rn = fieldFromInstruction(insn, 5, 5);
898 int64_t offset = fieldFromInstruction(insn, 12, 9);
899
900 // offset is a 9-bit signed immediate, so sign extend it to
901 // fill the unsigned.
902 if (offset & (1 << (9 - 1)))
903 offset |= ~((1LL << 9) - 1);
904
905 // First operand is always the writeback to the address register, if needed.
906 switch (Inst.getOpcode()) {
907 default:
908 break;
909 case AArch64::LDRSBWpre:
910 case AArch64::LDRSHWpre:
911 case AArch64::STRBBpre:
912 case AArch64::LDRBBpre:
913 case AArch64::STRHHpre:
914 case AArch64::LDRHHpre:
915 case AArch64::STRWpre:
916 case AArch64::LDRWpre:
917 case AArch64::LDRSBWpost:
918 case AArch64::LDRSHWpost:
919 case AArch64::STRBBpost:
920 case AArch64::LDRBBpost:
921 case AArch64::STRHHpost:
922 case AArch64::LDRHHpost:
923 case AArch64::STRWpost:
924 case AArch64::LDRWpost:
925 case AArch64::LDRSBXpre:
926 case AArch64::LDRSHXpre:
927 case AArch64::STRXpre:
928 case AArch64::LDRSWpre:
929 case AArch64::LDRXpre:
930 case AArch64::LDRSBXpost:
931 case AArch64::LDRSHXpost:
932 case AArch64::STRXpost:
933 case AArch64::LDRSWpost:
934 case AArch64::LDRXpost:
935 case AArch64::LDRQpre:
936 case AArch64::STRQpre:
937 case AArch64::LDRQpost:
938 case AArch64::STRQpost:
939 case AArch64::LDRDpre:
940 case AArch64::STRDpre:
941 case AArch64::LDRDpost:
942 case AArch64::STRDpost:
943 case AArch64::LDRSpre:
944 case AArch64::STRSpre:
945 case AArch64::LDRSpost:
946 case AArch64::STRSpost:
947 case AArch64::LDRHpre:
948 case AArch64::STRHpre:
949 case AArch64::LDRHpost:
950 case AArch64::STRHpost:
951 case AArch64::LDRBpre:
952 case AArch64::STRBpre:
953 case AArch64::LDRBpost:
954 case AArch64::STRBpost:
955 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
956 break;
957 }
958
959 switch (Inst.getOpcode()) {
960 default:
961 return Fail;
962 case AArch64::PRFUMi:
963 // Rt is an immediate in prefetch.
964 Inst.addOperand(MCOperand::CreateImm(Rt));
965 break;
966 case AArch64::STURBBi:
967 case AArch64::LDURBBi:
968 case AArch64::LDURSBWi:
969 case AArch64::STURHHi:
970 case AArch64::LDURHHi:
971 case AArch64::LDURSHWi:
972 case AArch64::STURWi:
973 case AArch64::LDURWi:
974 case AArch64::LDTRSBWi:
975 case AArch64::LDTRSHWi:
976 case AArch64::STTRWi:
977 case AArch64::LDTRWi:
978 case AArch64::STTRHi:
979 case AArch64::LDTRHi:
980 case AArch64::LDTRBi:
981 case AArch64::STTRBi:
982 case AArch64::LDRSBWpre:
983 case AArch64::LDRSHWpre:
984 case AArch64::STRBBpre:
985 case AArch64::LDRBBpre:
986 case AArch64::STRHHpre:
987 case AArch64::LDRHHpre:
988 case AArch64::STRWpre:
989 case AArch64::LDRWpre:
990 case AArch64::LDRSBWpost:
991 case AArch64::LDRSHWpost:
992 case AArch64::STRBBpost:
993 case AArch64::LDRBBpost:
994 case AArch64::STRHHpost:
995 case AArch64::LDRHHpost:
996 case AArch64::STRWpost:
997 case AArch64::LDRWpost:
998 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
999 break;
1000 case AArch64::LDURSBXi:
1001 case AArch64::LDURSHXi:
1002 case AArch64::LDURSWi:
1003 case AArch64::STURXi:
1004 case AArch64::LDURXi:
1005 case AArch64::LDTRSBXi:
1006 case AArch64::LDTRSHXi:
1007 case AArch64::LDTRSWi:
1008 case AArch64::STTRXi:
1009 case AArch64::LDTRXi:
1010 case AArch64::LDRSBXpre:
1011 case AArch64::LDRSHXpre:
1012 case AArch64::STRXpre:
1013 case AArch64::LDRSWpre:
1014 case AArch64::LDRXpre:
1015 case AArch64::LDRSBXpost:
1016 case AArch64::LDRSHXpost:
1017 case AArch64::STRXpost:
1018 case AArch64::LDRSWpost:
1019 case AArch64::LDRXpost:
1020 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1021 break;
1022 case AArch64::LDURQi:
1023 case AArch64::STURQi:
1024 case AArch64::LDRQpre:
1025 case AArch64::STRQpre:
1026 case AArch64::LDRQpost:
1027 case AArch64::STRQpost:
1028 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1029 break;
1030 case AArch64::LDURDi:
1031 case AArch64::STURDi:
1032 case AArch64::LDRDpre:
1033 case AArch64::STRDpre:
1034 case AArch64::LDRDpost:
1035 case AArch64::STRDpost:
1036 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1037 break;
1038 case AArch64::LDURSi:
1039 case AArch64::STURSi:
1040 case AArch64::LDRSpre:
1041 case AArch64::STRSpre:
1042 case AArch64::LDRSpost:
1043 case AArch64::STRSpost:
1044 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1045 break;
1046 case AArch64::LDURHi:
1047 case AArch64::STURHi:
1048 case AArch64::LDRHpre:
1049 case AArch64::STRHpre:
1050 case AArch64::LDRHpost:
1051 case AArch64::STRHpost:
1052 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1053 break;
1054 case AArch64::LDURBi:
1055 case AArch64::STURBi:
1056 case AArch64::LDRBpre:
1057 case AArch64::STRBpre:
1058 case AArch64::LDRBpost:
1059 case AArch64::STRBpost:
1060 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1061 break;
1062 }
1063
1064 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1065 Inst.addOperand(MCOperand::CreateImm(offset));
1066
1067 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1068 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
1069 bool IsFP = fieldFromInstruction(insn, 26, 1);
1070
1071 // Cannot write back to a transfer register (but xzr != sp).
1072 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
1073 return SoftFail;
1074
1075 return Success;
1076}
1077
1078static DecodeStatus DecodeExclusiveLdStInstruction(llvm::MCInst &Inst,
1079 uint32_t insn, uint64_t Addr,
1080 const void *Decoder) {
1081 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1082 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1083 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1084 unsigned Rs = fieldFromInstruction(insn, 16, 5);
1085
1086 unsigned Opcode = Inst.getOpcode();
1087 switch (Opcode) {
1088 default:
1089 return Fail;
1090 case AArch64::STLXRW:
1091 case AArch64::STLXRB:
1092 case AArch64::STLXRH:
1093 case AArch64::STXRW:
1094 case AArch64::STXRB:
1095 case AArch64::STXRH:
1096 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1097 // FALLTHROUGH
1098 case AArch64::LDARW:
1099 case AArch64::LDARB:
1100 case AArch64::LDARH:
1101 case AArch64::LDAXRW:
1102 case AArch64::LDAXRB:
1103 case AArch64::LDAXRH:
1104 case AArch64::LDXRW:
1105 case AArch64::LDXRB:
1106 case AArch64::LDXRH:
1107 case AArch64::STLRW:
1108 case AArch64::STLRB:
1109 case AArch64::STLRH:
1110 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1111 break;
1112 case AArch64::STLXRX:
1113 case AArch64::STXRX:
1114 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1115 // FALLTHROUGH
1116 case AArch64::LDARX:
1117 case AArch64::LDAXRX:
1118 case AArch64::LDXRX:
1119 case AArch64::STLRX:
1120 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1121 break;
1122 case AArch64::STLXPW:
1123 case AArch64::STXPW:
1124 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1125 // FALLTHROUGH
1126 case AArch64::LDAXPW:
1127 case AArch64::LDXPW:
1128 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1129 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1130 break;
1131 case AArch64::STLXPX:
1132 case AArch64::STXPX:
1133 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1134 // FALLTHROUGH
1135 case AArch64::LDAXPX:
1136 case AArch64::LDXPX:
1137 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1138 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1139 break;
1140 }
1141
1142 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1143
1144 // You shouldn't load to the same register twice in an instruction...
1145 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW ||
1146 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) &&
1147 Rt == Rt2)
1148 return SoftFail;
1149
1150 return Success;
1151}
1152
1153static DecodeStatus DecodePairLdStInstruction(llvm::MCInst &Inst, uint32_t insn,
1154 uint64_t Addr,
1155 const void *Decoder) {
1156 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1157 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1158 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1159 int64_t offset = fieldFromInstruction(insn, 15, 7);
1160 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1161
1162 // offset is a 7-bit signed immediate, so sign extend it to
1163 // fill the unsigned.
1164 if (offset & (1 << (7 - 1)))
1165 offset |= ~((1LL << 7) - 1);
1166
1167 unsigned Opcode = Inst.getOpcode();
1168 bool NeedsDisjointWritebackTransfer = false;
1169
1170 // First operand is always writeback of base register.
1171 switch (Opcode) {
1172 default:
1173 break;
1174 case AArch64::LDPXpost:
1175 case AArch64::STPXpost:
1176 case AArch64::LDPSWpost:
1177 case AArch64::LDPXpre:
1178 case AArch64::STPXpre:
1179 case AArch64::LDPSWpre:
1180 case AArch64::LDPWpost:
1181 case AArch64::STPWpost:
1182 case AArch64::LDPWpre:
1183 case AArch64::STPWpre:
1184 case AArch64::LDPQpost:
1185 case AArch64::STPQpost:
1186 case AArch64::LDPQpre:
1187 case AArch64::STPQpre:
1188 case AArch64::LDPDpost:
1189 case AArch64::STPDpost:
1190 case AArch64::LDPDpre:
1191 case AArch64::STPDpre:
1192 case AArch64::LDPSpost:
1193 case AArch64::STPSpost:
1194 case AArch64::LDPSpre:
1195 case AArch64::STPSpre:
1196 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1197 break;
1198 }
1199
1200 switch (Opcode) {
1201 default:
1202 return Fail;
1203 case AArch64::LDPXpost:
1204 case AArch64::STPXpost:
1205 case AArch64::LDPSWpost:
1206 case AArch64::LDPXpre:
1207 case AArch64::STPXpre:
1208 case AArch64::LDPSWpre:
1209 NeedsDisjointWritebackTransfer = true;
1210 // Fallthrough
1211 case AArch64::LDNPXi:
1212 case AArch64::STNPXi:
1213 case AArch64::LDPXi:
1214 case AArch64::STPXi:
1215 case AArch64::LDPSWi:
1216 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1217 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1218 break;
1219 case AArch64::LDPWpost:
1220 case AArch64::STPWpost:
1221 case AArch64::LDPWpre:
1222 case AArch64::STPWpre:
1223 NeedsDisjointWritebackTransfer = true;
1224 // Fallthrough
1225 case AArch64::LDNPWi:
1226 case AArch64::STNPWi:
1227 case AArch64::LDPWi:
1228 case AArch64::STPWi:
1229 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1230 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1231 break;
1232 case AArch64::LDNPQi:
1233 case AArch64::STNPQi:
1234 case AArch64::LDPQpost:
1235 case AArch64::STPQpost:
1236 case AArch64::LDPQi:
1237 case AArch64::STPQi:
1238 case AArch64::LDPQpre:
1239 case AArch64::STPQpre:
1240 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1241 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder);
1242 break;
1243 case AArch64::LDNPDi:
1244 case AArch64::STNPDi:
1245 case AArch64::LDPDpost:
1246 case AArch64::STPDpost:
1247 case AArch64::LDPDi:
1248 case AArch64::STPDi:
1249 case AArch64::LDPDpre:
1250 case AArch64::STPDpre:
1251 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1252 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1253 break;
1254 case AArch64::LDNPSi:
1255 case AArch64::STNPSi:
1256 case AArch64::LDPSpost:
1257 case AArch64::STPSpost:
1258 case AArch64::LDPSi:
1259 case AArch64::STPSi:
1260 case AArch64::LDPSpre:
1261 case AArch64::STPSpre:
1262 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1263 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1264 break;
1265 }
1266
1267 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1268 Inst.addOperand(MCOperand::CreateImm(offset));
1269
1270 // You shouldn't load to the same register twice in an instruction...
1271 if (IsLoad && Rt == Rt2)
1272 return SoftFail;
1273
1274 // ... or do any operation that writes-back to a transfer register. But note
1275 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
1276 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
1277 return SoftFail;
1278
1279 return Success;
1280}
1281
1282static DecodeStatus DecodeAddSubERegInstruction(llvm::MCInst &Inst,
1283 uint32_t insn, uint64_t Addr,
1284 const void *Decoder) {
1285 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1286 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1287 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1288 unsigned extend = fieldFromInstruction(insn, 10, 6);
1289
1290 unsigned shift = extend & 0x7;
1291 if (shift > 4)
1292 return Fail;
1293
1294 switch (Inst.getOpcode()) {
1295 default:
1296 return Fail;
1297 case AArch64::ADDWrx:
1298 case AArch64::SUBWrx:
1299 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1300 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1301 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1302 break;
1303 case AArch64::ADDSWrx:
1304 case AArch64::SUBSWrx:
1305 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1306 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1307 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1308 break;
1309 case AArch64::ADDXrx:
1310 case AArch64::SUBXrx:
1311 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1312 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1313 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1314 break;
1315 case AArch64::ADDSXrx:
1316 case AArch64::SUBSXrx:
1317 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1318 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1319 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1320 break;
1321 case AArch64::ADDXrx64:
1322 case AArch64::SUBXrx64:
1323 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1324 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1325 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1326 break;
1327 case AArch64::SUBSXrx64:
1328 case AArch64::ADDSXrx64:
1329 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1330 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1331 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1332 break;
1333 }
1334
1335 Inst.addOperand(MCOperand::CreateImm(extend));
1336 return Success;
1337}
1338
1339static DecodeStatus DecodeLogicalImmInstruction(llvm::MCInst &Inst,
1340 uint32_t insn, uint64_t Addr,
1341 const void *Decoder) {
1342 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1343 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1344 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1345 unsigned imm;
1346
1347 if (Datasize) {
1348 if (Inst.getOpcode() == AArch64::ANDSXri)
1349 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1350 else
1351 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1352 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
1353 imm = fieldFromInstruction(insn, 10, 13);
1354 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1355 return Fail;
1356 } else {
1357 if (Inst.getOpcode() == AArch64::ANDSWri)
1358 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1359 else
1360 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1361 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
1362 imm = fieldFromInstruction(insn, 10, 12);
1363 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32))
1364 return Fail;
1365 }
1366 Inst.addOperand(MCOperand::CreateImm(imm));
1367 return Success;
1368}
1369
1370static DecodeStatus DecodeModImmInstruction(llvm::MCInst &Inst, uint32_t insn,
1371 uint64_t Addr,
1372 const void *Decoder) {
1373 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1374 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1375 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1376 imm |= fieldFromInstruction(insn, 5, 5);
1377
1378 if (Inst.getOpcode() == AArch64::MOVID)
1379 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder);
1380 else
1381 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1382
1383 Inst.addOperand(MCOperand::CreateImm(imm));
1384
1385 switch (Inst.getOpcode()) {
1386 default:
1387 break;
1388 case AArch64::MOVIv4i16:
1389 case AArch64::MOVIv8i16:
1390 case AArch64::MVNIv4i16:
1391 case AArch64::MVNIv8i16:
1392 case AArch64::MOVIv2i32:
1393 case AArch64::MOVIv4i32:
1394 case AArch64::MVNIv2i32:
1395 case AArch64::MVNIv4i32:
1396 Inst.addOperand(MCOperand::CreateImm((cmode & 6) << 2));
1397 break;
1398 case AArch64::MOVIv2s_msl:
1399 case AArch64::MOVIv4s_msl:
1400 case AArch64::MVNIv2s_msl:
1401 case AArch64::MVNIv4s_msl:
1402 Inst.addOperand(MCOperand::CreateImm(cmode & 1 ? 0x110 : 0x108));
1403 break;
1404 }
1405
1406 return Success;
1407}
1408
1409static DecodeStatus DecodeModImmTiedInstruction(llvm::MCInst &Inst,
1410 uint32_t insn, uint64_t Addr,
1411 const void *Decoder) {
1412 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1413 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1414 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1415 imm |= fieldFromInstruction(insn, 5, 5);
1416
1417 // Tied operands added twice.
1418 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1419 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1420
1421 Inst.addOperand(MCOperand::CreateImm(imm));
1422 Inst.addOperand(MCOperand::CreateImm((cmode & 6) << 2));
1423
1424 return Success;
1425}
1426
1427static DecodeStatus DecodeAdrInstruction(llvm::MCInst &Inst, uint32_t insn,
1428 uint64_t Addr, const void *Decoder) {
1429 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1430 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
1431 imm |= fieldFromInstruction(insn, 29, 2);
1432 const AArch64Disassembler *Dis =
1433 static_cast<const AArch64Disassembler *>(Decoder);
1434
1435 // Sign-extend the 21-bit immediate.
1436 if (imm & (1 << (21 - 1)))
1437 imm |= ~((1LL << 21) - 1);
1438
1439 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1440 if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4))
1441 Inst.addOperand(MCOperand::CreateImm(imm));
1442
1443 return Success;
1444}
1445
1446static DecodeStatus DecodeBaseAddSubImm(llvm::MCInst &Inst, uint32_t insn,
1447 uint64_t Addr, const void *Decoder) {
1448 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1449 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1450 unsigned Imm = fieldFromInstruction(insn, 10, 14);
1451 unsigned S = fieldFromInstruction(insn, 29, 1);
1452 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1453
1454 unsigned ShifterVal = (Imm >> 12) & 3;
1455 unsigned ImmVal = Imm & 0xFFF;
1456 const AArch64Disassembler *Dis =
1457 static_cast<const AArch64Disassembler *>(Decoder);
1458
1459 if (ShifterVal != 0 && ShifterVal != 1)
1460 return Fail;
1461
1462 if (Datasize) {
1463 if (Rd == 31 && !S)
1464 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1465 else
1466 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1467 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1468 } else {
1469 if (Rd == 31 && !S)
1470 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1471 else
1472 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1473 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1474 }
1475
1476 if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4))
1477 Inst.addOperand(MCOperand::CreateImm(ImmVal));
1478 Inst.addOperand(MCOperand::CreateImm(12 * ShifterVal));
1479 return Success;
1480}
1481
1482static DecodeStatus DecodeUnconditionalBranch(llvm::MCInst &Inst, uint32_t insn,
1483 uint64_t Addr,
1484 const void *Decoder) {
1485 int64_t imm = fieldFromInstruction(insn, 0, 26);
1486 const AArch64Disassembler *Dis =
1487 static_cast<const AArch64Disassembler *>(Decoder);
1488
1489 // Sign-extend the 26-bit immediate.
1490 if (imm & (1 << (26 - 1)))
1491 imm |= ~((1LL << 26) - 1);
1492
Alexey Samsonov729b12e2014-09-02 16:19:41 +0000[diff] [blame]1493 if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4))
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1494 Inst.addOperand(MCOperand::CreateImm(imm));
1495
1496 return Success;
1497}
1498
1499static DecodeStatus DecodeSystemPStateInstruction(llvm::MCInst &Inst,
1500 uint32_t insn, uint64_t Addr,
1501 const void *Decoder) {
1502 uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1503 uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1504 uint64_t crm = fieldFromInstruction(insn, 8, 4);
1505
1506 uint64_t pstate_field = (op1 << 3) | op2;
1507
1508 Inst.addOperand(MCOperand::CreateImm(pstate_field));
1509 Inst.addOperand(MCOperand::CreateImm(crm));
1510
1511 bool ValidNamed;
1512 (void)AArch64PState::PStateMapper().toString(pstate_field, ValidNamed);
Tom Coxon2c13e712014-09-30 16:23:16 +0000[diff] [blame]1513
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1514 return ValidNamed ? Success : Fail;
1515}
1516
1517static DecodeStatus DecodeTestAndBranch(llvm::MCInst &Inst, uint32_t insn,
1518 uint64_t Addr, const void *Decoder) {
1519 uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1520 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
1521 bit |= fieldFromInstruction(insn, 19, 5);
1522 int64_t dst = fieldFromInstruction(insn, 5, 14);
1523 const AArch64Disassembler *Dis =
1524 static_cast<const AArch64Disassembler *>(Decoder);
1525
1526 // Sign-extend 14-bit immediate.
1527 if (dst & (1 << (14 - 1)))
1528 dst |= ~((1LL << 14) - 1);
1529
1530 if (fieldFromInstruction(insn, 31, 1) == 0)
1531 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1532 else
1533 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1534 Inst.addOperand(MCOperand::CreateImm(bit));
Alexey Samsonov729b12e2014-09-02 16:19:41 +0000[diff] [blame]1535 if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4))
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1536 Inst.addOperand(MCOperand::CreateImm(dst));
1537
1538 return Success;
1539}