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gerrit-public.fairphone.software / toolchain / llvm-project / e6ef099dcd0faa1c05cab75c2779c2fd2745d2a2 / . / llvm / lib / Target / AMDGPU / DSInstructions.td
blob: a9f64589fa5ee248e05e9aa3c8b2f2e9bf58c8a7 [file] [log] [blame]
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]1//===-- DSInstructions.td - DS Instruction Defintions ---------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10class DS_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]> :
11 InstSI <outs, ins, "", pattern>,
12 SIMCInstr <opName, SIEncodingFamily.NONE> {
13
14 let SubtargetPredicate = isGCN;
15
16 let LGKM_CNT = 1;
17 let DS = 1;
Matt Arsenault10c17ca2016-10-06 10:13:23 +0000[diff] [blame]18 let Size = 8;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]19 let UseNamedOperandTable = 1;
20 let Uses = [M0, EXEC];
21
22 // Most instruction load and store data, so set this as the default.
23 let mayLoad = 1;
24 let mayStore = 1;
25
26 let hasSideEffects = 0;
27 let SchedRW = [WriteLDS];
28
29 let isPseudo = 1;
30 let isCodeGenOnly = 1;
31
32 let AsmMatchConverter = "cvtDS";
33
34 string Mnemonic = opName;
35 string AsmOperands = asmOps;
36
37 // Well these bits a kind of hack because it would be more natural
38 // to test "outs" and "ins" dags for the presence of particular operands
39 bits<1> has_vdst = 1;
40 bits<1> has_addr = 1;
41 bits<1> has_data0 = 1;
42 bits<1> has_data1 = 1;
43
44 bits<1> has_offset = 1; // has "offset" that should be split to offset0,1
45 bits<1> has_offset0 = 1;
46 bits<1> has_offset1 = 1;
47
48 bits<1> has_gds = 1;
49 bits<1> gdsValue = 0; // if has_gds == 0 set gds to this value
50}
51
52class DS_Real <DS_Pseudo ds> :
53 InstSI <ds.OutOperandList, ds.InOperandList, ds.Mnemonic # " " # ds.AsmOperands, []>,
54 Enc64 {
55
56 let isPseudo = 0;
57 let isCodeGenOnly = 0;
58
59 // copy relevant pseudo op flags
60 let SubtargetPredicate = ds.SubtargetPredicate;
61 let AsmMatchConverter = ds.AsmMatchConverter;
62
63 // encoding fields
64 bits<8> vdst;
65 bits<1> gds;
66 bits<8> addr;
67 bits<8> data0;
68 bits<8> data1;
69 bits<8> offset0;
70 bits<8> offset1;
71
72 bits<16> offset;
73 let offset0 = !if(ds.has_offset, offset{7-0}, ?);
74 let offset1 = !if(ds.has_offset, offset{15-8}, ?);
75}
76
77
78// DS Pseudo instructions
79
80class DS_1A1D_NORET<string opName, RegisterClass rc = VGPR_32>
81: DS_Pseudo<opName,
82 (outs),
83 (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
84 "$addr, $data0$offset$gds">,
85 AtomicNoRet<opName, 0> {
86
87 let has_data1 = 0;
88 let has_vdst = 0;
89}
90
Matt Arsenaultf3dd8632016-11-01 00:55:14 +0000[diff] [blame]91class DS_1A2D_NORET<string opName, RegisterClass rc = VGPR_32>
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]92: DS_Pseudo<opName,
93 (outs),
94 (ins VGPR_32:$addr, rc:$data0, rc:$data1, offset:$offset, gds:$gds),
95 "$addr, $data0, $data1"#"$offset"#"$gds">,
96 AtomicNoRet<opName, 0> {
97
98 let has_vdst = 0;
99}
100
101class DS_1A2D_Off8_NORET <string opName, RegisterClass rc = VGPR_32>
102: DS_Pseudo<opName,
103 (outs),
104 (ins VGPR_32:$addr, rc:$data0, rc:$data1,
105 offset0:$offset0, offset1:$offset1, gds:$gds),
106 "$addr, $data0, $data1$offset0$offset1$gds"> {
107
108 let has_vdst = 0;
109 let has_offset = 0;
110 let AsmMatchConverter = "cvtDSOffset01";
111}
112
113class DS_1A1D_RET <string opName, RegisterClass rc = VGPR_32>
114: DS_Pseudo<opName,
115 (outs rc:$vdst),
116 (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
117 "$vdst, $addr, $data0$offset$gds"> {
118
119 let hasPostISelHook = 1;
120 let has_data1 = 0;
121}
122
123class DS_1A2D_RET<string opName,
Matt Arsenaultf3dd8632016-11-01 00:55:14 +0000[diff] [blame]124 RegisterClass rc = VGPR_32,
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]125 RegisterClass src = rc>
126: DS_Pseudo<opName,
127 (outs rc:$vdst),
128 (ins VGPR_32:$addr, src:$data0, src:$data1, offset:$offset, gds:$gds),
129 "$vdst, $addr, $data0, $data1$offset$gds"> {
130
131 let hasPostISelHook = 1;
132}
133
Dmitry Preobrazhensky7184c442017-04-12 14:29:45 +0000[diff] [blame]134class DS_1A2D_Off8_RET<string opName,
135 RegisterClass rc = VGPR_32,
136 RegisterClass src = rc>
137: DS_Pseudo<opName,
138 (outs rc:$vdst),
139 (ins VGPR_32:$addr, src:$data0, src:$data1, offset0:$offset0, offset1:$offset1, gds:$gds),
140 "$vdst, $addr, $data0, $data1$offset0$offset1$gds"> {
141
142 let has_offset = 0;
143 let AsmMatchConverter = "cvtDSOffset01";
144
145 let hasPostISelHook = 1;
146}
147
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]148class DS_1A_RET<string opName, RegisterClass rc = VGPR_32>
149: DS_Pseudo<opName,
150 (outs rc:$vdst),
Matt Arsenaultf3dd8632016-11-01 00:55:14 +0000[diff] [blame]151 (ins VGPR_32:$addr, offset:$offset, gds:$gds),
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]152 "$vdst, $addr$offset$gds"> {
153
154 let has_data0 = 0;
155 let has_data1 = 0;
156}
157
158class DS_1A_Off8_RET <string opName, RegisterClass rc = VGPR_32>
159: DS_Pseudo<opName,
160 (outs rc:$vdst),
161 (ins VGPR_32:$addr, offset0:$offset0, offset1:$offset1, gds:$gds),
162 "$vdst, $addr$offset0$offset1$gds"> {
163
164 let has_offset = 0;
165 let has_data0 = 0;
166 let has_data1 = 0;
167 let AsmMatchConverter = "cvtDSOffset01";
168}
169
170class DS_1A_RET_GDS <string opName> : DS_Pseudo<opName,
171 (outs VGPR_32:$vdst),
172 (ins VGPR_32:$addr, offset:$offset),
173 "$vdst, $addr$offset gds"> {
174
175 let has_data0 = 0;
176 let has_data1 = 0;
177 let has_gds = 0;
178 let gdsValue = 1;
Artem Tamazov43b61562017-02-03 12:47:30 +0000[diff] [blame]179 let AsmMatchConverter = "cvtDSGds";
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]180}
181
182class DS_0A_RET <string opName> : DS_Pseudo<opName,
183 (outs VGPR_32:$vdst),
184 (ins offset:$offset, gds:$gds),
185 "$vdst$offset$gds"> {
186
187 let mayLoad = 1;
188 let mayStore = 1;
189
190 let has_addr = 0;
191 let has_data0 = 0;
192 let has_data1 = 0;
193}
194
195class DS_1A <string opName> : DS_Pseudo<opName,
196 (outs),
197 (ins VGPR_32:$addr, offset:$offset, gds:$gds),
198 "$addr$offset$gds"> {
199
200 let mayLoad = 1;
201 let mayStore = 1;
202
203 let has_vdst = 0;
204 let has_data0 = 0;
205 let has_data1 = 0;
206}
207
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]208class DS_GWS <string opName, dag ins, string asmOps>
209: DS_Pseudo<opName, (outs), ins, asmOps> {
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]210
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]211 let has_vdst = 0;
212 let has_addr = 0;
213 let has_data0 = 0;
214 let has_data1 = 0;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]215
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]216 let has_gds = 0;
217 let gdsValue = 1;
218 let AsmMatchConverter = "cvtDSGds";
219}
220
221class DS_GWS_0D <string opName>
222: DS_GWS<opName,
223 (ins offset:$offset, gds:$gds), "$offset gds">;
224
225class DS_GWS_1D <string opName>
226: DS_GWS<opName,
227 (ins VGPR_32:$data0, offset:$offset, gds:$gds), "$data0$offset gds"> {
228
229 let has_data0 = 1;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]230}
231
Matt Arsenault78124982017-02-28 20:15:46 +0000[diff] [blame]232class DS_VOID <string opName> : DS_Pseudo<opName,
233 (outs), (ins), ""> {
234 let mayLoad = 0;
235 let mayStore = 0;
236 let hasSideEffects = 1;
237 let UseNamedOperandTable = 0;
238 let AsmMatchConverter = "";
239
240 let has_vdst = 0;
241 let has_addr = 0;
242 let has_data0 = 0;
243 let has_data1 = 0;
244 let has_offset = 0;
245 let has_offset0 = 0;
246 let has_offset1 = 0;
247 let has_gds = 0;
248}
249
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]250class DS_1A1D_PERMUTE <string opName, SDPatternOperator node = null_frag>
251: DS_Pseudo<opName,
252 (outs VGPR_32:$vdst),
253 (ins VGPR_32:$addr, VGPR_32:$data0, offset:$offset),
254 "$vdst, $addr, $data0$offset",
255 [(set i32:$vdst,
256 (node (DS1Addr1Offset i32:$addr, i16:$offset), i32:$data0))] > {
257
Kannan Narayananacb089e2017-04-12 03:25:12 +0000[diff] [blame]258 let LGKM_CNT = 0;
259
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]260 let mayLoad = 0;
261 let mayStore = 0;
262 let isConvergent = 1;
263
264 let has_data1 = 0;
265 let has_gds = 0;
266}
267
268def DS_ADD_U32 : DS_1A1D_NORET<"ds_add_u32">;
269def DS_SUB_U32 : DS_1A1D_NORET<"ds_sub_u32">;
270def DS_RSUB_U32 : DS_1A1D_NORET<"ds_rsub_u32">;
271def DS_INC_U32 : DS_1A1D_NORET<"ds_inc_u32">;
272def DS_DEC_U32 : DS_1A1D_NORET<"ds_dec_u32">;
273def DS_MIN_I32 : DS_1A1D_NORET<"ds_min_i32">;
274def DS_MAX_I32 : DS_1A1D_NORET<"ds_max_i32">;
275def DS_MIN_U32 : DS_1A1D_NORET<"ds_min_u32">;
276def DS_MAX_U32 : DS_1A1D_NORET<"ds_max_u32">;
277def DS_AND_B32 : DS_1A1D_NORET<"ds_and_b32">;
278def DS_OR_B32 : DS_1A1D_NORET<"ds_or_b32">;
279def DS_XOR_B32 : DS_1A1D_NORET<"ds_xor_b32">;
Artem Tamazov2e217b82016-09-21 16:35:44 +0000[diff] [blame]280def DS_ADD_F32 : DS_1A1D_NORET<"ds_add_f32">;
Artem Tamazov751985a2016-10-21 14:49:22 +0000[diff] [blame]281def DS_MIN_F32 : DS_1A1D_NORET<"ds_min_f32">;
282def DS_MAX_F32 : DS_1A1D_NORET<"ds_max_f32">;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]283
284let mayLoad = 0 in {
285def DS_WRITE_B8 : DS_1A1D_NORET<"ds_write_b8">;
286def DS_WRITE_B16 : DS_1A1D_NORET<"ds_write_b16">;
287def DS_WRITE_B32 : DS_1A1D_NORET<"ds_write_b32">;
288def DS_WRITE2_B32 : DS_1A2D_Off8_NORET<"ds_write2_b32">;
289def DS_WRITE2ST64_B32 : DS_1A2D_Off8_NORET<"ds_write2st64_b32">;
290}
291
292def DS_MSKOR_B32 : DS_1A2D_NORET<"ds_mskor_b32">;
293def DS_CMPST_B32 : DS_1A2D_NORET<"ds_cmpst_b32">;
294def DS_CMPST_F32 : DS_1A2D_NORET<"ds_cmpst_f32">;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]295
296def DS_ADD_U64 : DS_1A1D_NORET<"ds_add_u64", VReg_64>;
297def DS_SUB_U64 : DS_1A1D_NORET<"ds_sub_u64", VReg_64>;
298def DS_RSUB_U64 : DS_1A1D_NORET<"ds_rsub_u64", VReg_64>;
299def DS_INC_U64 : DS_1A1D_NORET<"ds_inc_u64", VReg_64>;
300def DS_DEC_U64 : DS_1A1D_NORET<"ds_dec_u64", VReg_64>;
301def DS_MIN_I64 : DS_1A1D_NORET<"ds_min_i64", VReg_64>;
302def DS_MAX_I64 : DS_1A1D_NORET<"ds_max_i64", VReg_64>;
303def DS_MIN_U64 : DS_1A1D_NORET<"ds_min_u64", VReg_64>;
304def DS_MAX_U64 : DS_1A1D_NORET<"ds_max_u64", VReg_64>;
305def DS_AND_B64 : DS_1A1D_NORET<"ds_and_b64", VReg_64>;
306def DS_OR_B64 : DS_1A1D_NORET<"ds_or_b64", VReg_64>;
307def DS_XOR_B64 : DS_1A1D_NORET<"ds_xor_b64", VReg_64>;
308def DS_MSKOR_B64 : DS_1A2D_NORET<"ds_mskor_b64", VReg_64>;
309let mayLoad = 0 in {
310def DS_WRITE_B64 : DS_1A1D_NORET<"ds_write_b64", VReg_64>;
311def DS_WRITE2_B64 : DS_1A2D_Off8_NORET<"ds_write2_b64", VReg_64>;
312def DS_WRITE2ST64_B64 : DS_1A2D_Off8_NORET<"ds_write2st64_b64", VReg_64>;
313}
314def DS_CMPST_B64 : DS_1A2D_NORET<"ds_cmpst_b64", VReg_64>;
315def DS_CMPST_F64 : DS_1A2D_NORET<"ds_cmpst_f64", VReg_64>;
316def DS_MIN_F64 : DS_1A1D_NORET<"ds_min_f64", VReg_64>;
317def DS_MAX_F64 : DS_1A1D_NORET<"ds_max_f64", VReg_64>;
318
319def DS_ADD_RTN_U32 : DS_1A1D_RET<"ds_add_rtn_u32">,
320 AtomicNoRet<"ds_add_u32", 1>;
Artem Tamazov2e217b82016-09-21 16:35:44 +0000[diff] [blame]321def DS_ADD_RTN_F32 : DS_1A1D_RET<"ds_add_rtn_f32">,
322 AtomicNoRet<"ds_add_f32", 1>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]323def DS_SUB_RTN_U32 : DS_1A1D_RET<"ds_sub_rtn_u32">,
324 AtomicNoRet<"ds_sub_u32", 1>;
325def DS_RSUB_RTN_U32 : DS_1A1D_RET<"ds_rsub_rtn_u32">,
326 AtomicNoRet<"ds_rsub_u32", 1>;
327def DS_INC_RTN_U32 : DS_1A1D_RET<"ds_inc_rtn_u32">,
328 AtomicNoRet<"ds_inc_u32", 1>;
329def DS_DEC_RTN_U32 : DS_1A1D_RET<"ds_dec_rtn_u32">,
330 AtomicNoRet<"ds_dec_u32", 1>;
331def DS_MIN_RTN_I32 : DS_1A1D_RET<"ds_min_rtn_i32">,
332 AtomicNoRet<"ds_min_i32", 1>;
333def DS_MAX_RTN_I32 : DS_1A1D_RET<"ds_max_rtn_i32">,
334 AtomicNoRet<"ds_max_i32", 1>;
335def DS_MIN_RTN_U32 : DS_1A1D_RET<"ds_min_rtn_u32">,
336 AtomicNoRet<"ds_min_u32", 1>;
337def DS_MAX_RTN_U32 : DS_1A1D_RET<"ds_max_rtn_u32">,
338 AtomicNoRet<"ds_max_u32", 1>;
339def DS_AND_RTN_B32 : DS_1A1D_RET<"ds_and_rtn_b32">,
340 AtomicNoRet<"ds_and_b32", 1>;
341def DS_OR_RTN_B32 : DS_1A1D_RET<"ds_or_rtn_b32">,
342 AtomicNoRet<"ds_or_b32", 1>;
343def DS_XOR_RTN_B32 : DS_1A1D_RET<"ds_xor_rtn_b32">,
344 AtomicNoRet<"ds_xor_b32", 1>;
345def DS_MSKOR_RTN_B32 : DS_1A2D_RET<"ds_mskor_rtn_b32">,
346 AtomicNoRet<"ds_mskor_b32", 1>;
347def DS_CMPST_RTN_B32 : DS_1A2D_RET <"ds_cmpst_rtn_b32">,
348 AtomicNoRet<"ds_cmpst_b32", 1>;
349def DS_CMPST_RTN_F32 : DS_1A2D_RET <"ds_cmpst_rtn_f32">,
350 AtomicNoRet<"ds_cmpst_f32", 1>;
Artem Tamazov751985a2016-10-21 14:49:22 +0000[diff] [blame]351def DS_MIN_RTN_F32 : DS_1A1D_RET <"ds_min_rtn_f32">,
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]352 AtomicNoRet<"ds_min_f32", 1>;
Artem Tamazov751985a2016-10-21 14:49:22 +0000[diff] [blame]353def DS_MAX_RTN_F32 : DS_1A1D_RET <"ds_max_rtn_f32">,
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]354 AtomicNoRet<"ds_max_f32", 1>;
355
356def DS_WRXCHG_RTN_B32 : DS_1A1D_RET<"ds_wrxchg_rtn_b32">,
357 AtomicNoRet<"", 1>;
Dmitry Preobrazhensky7184c442017-04-12 14:29:45 +0000[diff] [blame]358def DS_WRXCHG2_RTN_B32 : DS_1A2D_Off8_RET<"ds_wrxchg2_rtn_b32", VReg_64, VGPR_32>,
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]359 AtomicNoRet<"", 1>;
Dmitry Preobrazhensky7184c442017-04-12 14:29:45 +0000[diff] [blame]360def DS_WRXCHG2ST64_RTN_B32 : DS_1A2D_Off8_RET<"ds_wrxchg2st64_rtn_b32", VReg_64, VGPR_32>,
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]361 AtomicNoRet<"", 1>;
362
363def DS_ADD_RTN_U64 : DS_1A1D_RET<"ds_add_rtn_u64", VReg_64>,
364 AtomicNoRet<"ds_add_u64", 1>;
365def DS_SUB_RTN_U64 : DS_1A1D_RET<"ds_sub_rtn_u64", VReg_64>,
366 AtomicNoRet<"ds_sub_u64", 1>;
367def DS_RSUB_RTN_U64 : DS_1A1D_RET<"ds_rsub_rtn_u64", VReg_64>,
368 AtomicNoRet<"ds_rsub_u64", 1>;
369def DS_INC_RTN_U64 : DS_1A1D_RET<"ds_inc_rtn_u64", VReg_64>,
370 AtomicNoRet<"ds_inc_u64", 1>;
371def DS_DEC_RTN_U64 : DS_1A1D_RET<"ds_dec_rtn_u64", VReg_64>,
372 AtomicNoRet<"ds_dec_u64", 1>;
373def DS_MIN_RTN_I64 : DS_1A1D_RET<"ds_min_rtn_i64", VReg_64>,
374 AtomicNoRet<"ds_min_i64", 1>;
375def DS_MAX_RTN_I64 : DS_1A1D_RET<"ds_max_rtn_i64", VReg_64>,
376 AtomicNoRet<"ds_max_i64", 1>;
377def DS_MIN_RTN_U64 : DS_1A1D_RET<"ds_min_rtn_u64", VReg_64>,
378 AtomicNoRet<"ds_min_u64", 1>;
379def DS_MAX_RTN_U64 : DS_1A1D_RET<"ds_max_rtn_u64", VReg_64>,
380 AtomicNoRet<"ds_max_u64", 1>;
381def DS_AND_RTN_B64 : DS_1A1D_RET<"ds_and_rtn_b64", VReg_64>,
382 AtomicNoRet<"ds_and_b64", 1>;
383def DS_OR_RTN_B64 : DS_1A1D_RET<"ds_or_rtn_b64", VReg_64>,
384 AtomicNoRet<"ds_or_b64", 1>;
385def DS_XOR_RTN_B64 : DS_1A1D_RET<"ds_xor_rtn_b64", VReg_64>,
386 AtomicNoRet<"ds_xor_b64", 1>;
387def DS_MSKOR_RTN_B64 : DS_1A2D_RET<"ds_mskor_rtn_b64", VReg_64>,
388 AtomicNoRet<"ds_mskor_b64", 1>;
389def DS_CMPST_RTN_B64 : DS_1A2D_RET<"ds_cmpst_rtn_b64", VReg_64>,
390 AtomicNoRet<"ds_cmpst_b64", 1>;
391def DS_CMPST_RTN_F64 : DS_1A2D_RET<"ds_cmpst_rtn_f64", VReg_64>,
392 AtomicNoRet<"ds_cmpst_f64", 1>;
393def DS_MIN_RTN_F64 : DS_1A1D_RET<"ds_min_rtn_f64", VReg_64>,
394 AtomicNoRet<"ds_min_f64", 1>;
395def DS_MAX_RTN_F64 : DS_1A1D_RET<"ds_max_rtn_f64", VReg_64>,
396 AtomicNoRet<"ds_max_f64", 1>;
397
398def DS_WRXCHG_RTN_B64 : DS_1A1D_RET<"ds_wrxchg_rtn_b64", VReg_64>,
Dmitry Preobrazhensky7184c442017-04-12 14:29:45 +0000[diff] [blame]399 AtomicNoRet<"", 1>;
400def DS_WRXCHG2_RTN_B64 : DS_1A2D_Off8_RET<"ds_wrxchg2_rtn_b64", VReg_128, VReg_64>,
401 AtomicNoRet<"", 1>;
402def DS_WRXCHG2ST64_RTN_B64 : DS_1A2D_Off8_RET<"ds_wrxchg2st64_rtn_b64", VReg_128, VReg_64>,
403 AtomicNoRet<"", 1>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]404
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]405def DS_GWS_INIT : DS_GWS_1D<"ds_gws_init">;
406def DS_GWS_SEMA_V : DS_GWS_0D<"ds_gws_sema_v">;
407def DS_GWS_SEMA_BR : DS_GWS_1D<"ds_gws_sema_br">;
408def DS_GWS_SEMA_P : DS_GWS_0D<"ds_gws_sema_p">;
409def DS_GWS_BARRIER : DS_GWS_1D<"ds_gws_barrier">;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]410
411def DS_ADD_SRC2_U32 : DS_1A<"ds_add_src2_u32">;
412def DS_SUB_SRC2_U32 : DS_1A<"ds_sub_src2_u32">;
413def DS_RSUB_SRC2_U32 : DS_1A<"ds_rsub_src2_u32">;
414def DS_INC_SRC2_U32 : DS_1A<"ds_inc_src2_u32">;
415def DS_DEC_SRC2_U32 : DS_1A<"ds_dec_src2_u32">;
416def DS_MIN_SRC2_I32 : DS_1A<"ds_min_src2_i32">;
417def DS_MAX_SRC2_I32 : DS_1A<"ds_max_src2_i32">;
418def DS_MIN_SRC2_U32 : DS_1A<"ds_min_src2_u32">;
419def DS_MAX_SRC2_U32 : DS_1A<"ds_max_src2_u32">;
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]420def DS_AND_SRC2_B32 : DS_1A<"ds_and_src2_b32">;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]421def DS_OR_SRC2_B32 : DS_1A<"ds_or_src2_b32">;
422def DS_XOR_SRC2_B32 : DS_1A<"ds_xor_src2_b32">;
423def DS_MIN_SRC2_F32 : DS_1A<"ds_min_src2_f32">;
424def DS_MAX_SRC2_F32 : DS_1A<"ds_max_src2_f32">;
425
426def DS_ADD_SRC2_U64 : DS_1A<"ds_add_src2_u64">;
427def DS_SUB_SRC2_U64 : DS_1A<"ds_sub_src2_u64">;
428def DS_RSUB_SRC2_U64 : DS_1A<"ds_rsub_src2_u64">;
429def DS_INC_SRC2_U64 : DS_1A<"ds_inc_src2_u64">;
430def DS_DEC_SRC2_U64 : DS_1A<"ds_dec_src2_u64">;
431def DS_MIN_SRC2_I64 : DS_1A<"ds_min_src2_i64">;
432def DS_MAX_SRC2_I64 : DS_1A<"ds_max_src2_i64">;
433def DS_MIN_SRC2_U64 : DS_1A<"ds_min_src2_u64">;
434def DS_MAX_SRC2_U64 : DS_1A<"ds_max_src2_u64">;
435def DS_AND_SRC2_B64 : DS_1A<"ds_and_src2_b64">;
436def DS_OR_SRC2_B64 : DS_1A<"ds_or_src2_b64">;
437def DS_XOR_SRC2_B64 : DS_1A<"ds_xor_src2_b64">;
438def DS_MIN_SRC2_F64 : DS_1A<"ds_min_src2_f64">;
439def DS_MAX_SRC2_F64 : DS_1A<"ds_max_src2_f64">;
440
Dmitry Preobrazhenskye6ef0992017-04-14 12:28:07 +0000[diff] [blame^]441def DS_WRITE_SRC2_B32 : DS_1A<"ds_write_src2_b32">;
442def DS_WRITE_SRC2_B64 : DS_1A<"ds_write_src2_b64">;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]443
444let Uses = [EXEC], mayLoad = 0, mayStore = 0, isConvergent = 1 in {
445def DS_SWIZZLE_B32 : DS_1A_RET <"ds_swizzle_b32">;
446}
447
448let mayStore = 0 in {
449def DS_READ_I8 : DS_1A_RET<"ds_read_i8">;
450def DS_READ_U8 : DS_1A_RET<"ds_read_u8">;
451def DS_READ_I16 : DS_1A_RET<"ds_read_i16">;
452def DS_READ_U16 : DS_1A_RET<"ds_read_u16">;
453def DS_READ_B32 : DS_1A_RET<"ds_read_b32">;
454def DS_READ_B64 : DS_1A_RET<"ds_read_b64", VReg_64>;
455
456def DS_READ2_B32 : DS_1A_Off8_RET<"ds_read2_b32", VReg_64>;
457def DS_READ2ST64_B32 : DS_1A_Off8_RET<"ds_read2st64_b32", VReg_64>;
458
459def DS_READ2_B64 : DS_1A_Off8_RET<"ds_read2_b64", VReg_128>;
460def DS_READ2ST64_B64 : DS_1A_Off8_RET<"ds_read2st64_b64", VReg_128>;
461}
462
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]463def DS_CONSUME : DS_0A_RET<"ds_consume">;
464def DS_APPEND : DS_0A_RET<"ds_append">;
465def DS_ORDERED_COUNT : DS_1A_RET_GDS<"ds_ordered_count">;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]466
467//===----------------------------------------------------------------------===//
468// Instruction definitions for CI and newer.
469//===----------------------------------------------------------------------===//
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]470
471let SubtargetPredicate = isCIVI in {
472
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]473def DS_WRAP_RTN_B32 : DS_1A2D_RET<"ds_wrap_rtn_b32">, AtomicNoRet<"", 1>;
474
475def DS_CONDXCHG32_RTN_B64 : DS_1A1D_RET<"ds_condxchg32_rtn_b64", VReg_64>,
476 AtomicNoRet<"", 1>;
477
478def DS_GWS_SEMA_RELEASE_ALL : DS_GWS_0D<"ds_gws_sema_release_all">;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]479
Matt Arsenaultdedc5442017-02-28 20:15:43 +0000[diff] [blame]480let mayStore = 0 in {
481def DS_READ_B96 : DS_1A_RET<"ds_read_b96", VReg_96>;
482def DS_READ_B128: DS_1A_RET<"ds_read_b128", VReg_128>;
483} // End mayStore = 0
484
485let mayLoad = 0 in {
486def DS_WRITE_B96 : DS_1A1D_NORET<"ds_write_b96", VReg_96>;
487def DS_WRITE_B128 : DS_1A1D_NORET<"ds_write_b128", VReg_128>;
488} // End mayLoad = 0
489
Matt Arsenault78124982017-02-28 20:15:46 +0000[diff] [blame]490def DS_NOP : DS_VOID<"ds_nop">;
Matt Arsenaultdedc5442017-02-28 20:15:43 +0000[diff] [blame]491
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]492} // let SubtargetPredicate = isCIVI
493
494//===----------------------------------------------------------------------===//
495// Instruction definitions for VI and newer.
496//===----------------------------------------------------------------------===//
497
498let SubtargetPredicate = isVI in {
499
500let Uses = [EXEC] in {
501def DS_PERMUTE_B32 : DS_1A1D_PERMUTE <"ds_permute_b32",
502 int_amdgcn_ds_permute>;
503def DS_BPERMUTE_B32 : DS_1A1D_PERMUTE <"ds_bpermute_b32",
504 int_amdgcn_ds_bpermute>;
505}
506
507} // let SubtargetPredicate = isVI
508
509//===----------------------------------------------------------------------===//
510// DS Patterns
511//===----------------------------------------------------------------------===//
512
513let Predicates = [isGCN] in {
514
515def : Pat <
516 (int_amdgcn_ds_swizzle i32:$src, imm:$offset16),
517 (DS_SWIZZLE_B32 $src, (as_i16imm $offset16), (i1 0))
518>;
519
520class DSReadPat <DS_Pseudo inst, ValueType vt, PatFrag frag> : Pat <
521 (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset))),
522 (inst $ptr, (as_i16imm $offset), (i1 0))
523>;
524
525def : DSReadPat <DS_READ_I8, i32, si_sextload_local_i8>;
526def : DSReadPat <DS_READ_U8, i32, si_az_extload_local_i8>;
Tom Stellard115a6152016-11-10 16:02:37 +0000[diff] [blame]527def : DSReadPat <DS_READ_I8, i16, si_sextload_local_i8>;
528def : DSReadPat <DS_READ_U8, i16, si_az_extload_local_i8>;
529def : DSReadPat <DS_READ_I16, i32, si_sextload_local_i16>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]530def : DSReadPat <DS_READ_I16, i32, si_sextload_local_i16>;
531def : DSReadPat <DS_READ_U16, i32, si_az_extload_local_i16>;
Tom Stellard115a6152016-11-10 16:02:37 +0000[diff] [blame]532def : DSReadPat <DS_READ_U16, i16, si_load_local>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]533def : DSReadPat <DS_READ_B32, i32, si_load_local>;
534
535let AddedComplexity = 100 in {
536
537def : DSReadPat <DS_READ_B64, v2i32, si_load_local_align8>;
538
539} // End AddedComplexity = 100
540
541def : Pat <
542 (v2i32 (si_load_local (DS64Bit4ByteAligned i32:$ptr, i8:$offset0,
543 i8:$offset1))),
544 (DS_READ2_B32 $ptr, $offset0, $offset1, (i1 0))
545>;
546
547class DSWritePat <DS_Pseudo inst, ValueType vt, PatFrag frag> : Pat <
548 (frag vt:$value, (DS1Addr1Offset i32:$ptr, i32:$offset)),
549 (inst $ptr, $value, (as_i16imm $offset), (i1 0))
550>;
551
552def : DSWritePat <DS_WRITE_B8, i32, si_truncstore_local_i8>;
553def : DSWritePat <DS_WRITE_B16, i32, si_truncstore_local_i16>;
Tom Stellard115a6152016-11-10 16:02:37 +0000[diff] [blame]554def : DSWritePat <DS_WRITE_B8, i16, si_truncstore_local_i8>;
555def : DSWritePat <DS_WRITE_B16, i16, si_store_local>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]556def : DSWritePat <DS_WRITE_B32, i32, si_store_local>;
557
558let AddedComplexity = 100 in {
559
560def : DSWritePat <DS_WRITE_B64, v2i32, si_store_local_align8>;
561} // End AddedComplexity = 100
562
563def : Pat <
564 (si_store_local v2i32:$value, (DS64Bit4ByteAligned i32:$ptr, i8:$offset0,
565 i8:$offset1)),
Tom Stellard115a6152016-11-10 16:02:37 +0000[diff] [blame]566 (DS_WRITE2_B32 $ptr, (i32 (EXTRACT_SUBREG $value, sub0)),
567 (i32 (EXTRACT_SUBREG $value, sub1)), $offset0, $offset1,
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]568 (i1 0))
569>;
570
571class DSAtomicRetPat<DS_Pseudo inst, ValueType vt, PatFrag frag> : Pat <
572 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$value),
573 (inst $ptr, $value, (as_i16imm $offset), (i1 0))
574>;
575
576class DSAtomicCmpXChg<DS_Pseudo inst, ValueType vt, PatFrag frag> : Pat <
577 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$cmp, vt:$swap),
578 (inst $ptr, $cmp, $swap, (as_i16imm $offset), (i1 0))
579>;
580
581
582// 32-bit atomics.
583def : DSAtomicRetPat<DS_WRXCHG_RTN_B32, i32, si_atomic_swap_local>;
584def : DSAtomicRetPat<DS_ADD_RTN_U32, i32, si_atomic_load_add_local>;
585def : DSAtomicRetPat<DS_SUB_RTN_U32, i32, si_atomic_load_sub_local>;
586def : DSAtomicRetPat<DS_INC_RTN_U32, i32, si_atomic_inc_local>;
587def : DSAtomicRetPat<DS_DEC_RTN_U32, i32, si_atomic_dec_local>;
588def : DSAtomicRetPat<DS_AND_RTN_B32, i32, si_atomic_load_and_local>;
589def : DSAtomicRetPat<DS_OR_RTN_B32, i32, si_atomic_load_or_local>;
590def : DSAtomicRetPat<DS_XOR_RTN_B32, i32, si_atomic_load_xor_local>;
591def : DSAtomicRetPat<DS_MIN_RTN_I32, i32, si_atomic_load_min_local>;
592def : DSAtomicRetPat<DS_MAX_RTN_I32, i32, si_atomic_load_max_local>;
593def : DSAtomicRetPat<DS_MIN_RTN_U32, i32, si_atomic_load_umin_local>;
594def : DSAtomicRetPat<DS_MAX_RTN_U32, i32, si_atomic_load_umax_local>;
595def : DSAtomicCmpXChg<DS_CMPST_RTN_B32, i32, si_atomic_cmp_swap_32_local>;
596
597// 64-bit atomics.
598def : DSAtomicRetPat<DS_WRXCHG_RTN_B64, i64, si_atomic_swap_local>;
599def : DSAtomicRetPat<DS_ADD_RTN_U64, i64, si_atomic_load_add_local>;
600def : DSAtomicRetPat<DS_SUB_RTN_U64, i64, si_atomic_load_sub_local>;
601def : DSAtomicRetPat<DS_INC_RTN_U64, i64, si_atomic_inc_local>;
602def : DSAtomicRetPat<DS_DEC_RTN_U64, i64, si_atomic_dec_local>;
603def : DSAtomicRetPat<DS_AND_RTN_B64, i64, si_atomic_load_and_local>;
604def : DSAtomicRetPat<DS_OR_RTN_B64, i64, si_atomic_load_or_local>;
605def : DSAtomicRetPat<DS_XOR_RTN_B64, i64, si_atomic_load_xor_local>;
606def : DSAtomicRetPat<DS_MIN_RTN_I64, i64, si_atomic_load_min_local>;
607def : DSAtomicRetPat<DS_MAX_RTN_I64, i64, si_atomic_load_max_local>;
608def : DSAtomicRetPat<DS_MIN_RTN_U64, i64, si_atomic_load_umin_local>;
609def : DSAtomicRetPat<DS_MAX_RTN_U64, i64, si_atomic_load_umax_local>;
610
611def : DSAtomicCmpXChg<DS_CMPST_RTN_B64, i64, si_atomic_cmp_swap_64_local>;
612
613} // let Predicates = [isGCN]
614
615//===----------------------------------------------------------------------===//
616// Real instructions
617//===----------------------------------------------------------------------===//
618
619//===----------------------------------------------------------------------===//
620// SIInstructions.td
621//===----------------------------------------------------------------------===//
622
623class DS_Real_si <bits<8> op, DS_Pseudo ds> :
624 DS_Real <ds>,
625 SIMCInstr <ds.Mnemonic, SIEncodingFamily.SI> {
626 let AssemblerPredicates=[isSICI];
627 let DecoderNamespace="SICI";
628
629 // encoding
630 let Inst{7-0} = !if(ds.has_offset0, offset0, 0);
631 let Inst{15-8} = !if(ds.has_offset1, offset1, 0);
632 let Inst{17} = !if(ds.has_gds, gds, ds.gdsValue);
633 let Inst{25-18} = op;
634 let Inst{31-26} = 0x36; // ds prefix
635 let Inst{39-32} = !if(ds.has_addr, addr, 0);
636 let Inst{47-40} = !if(ds.has_data0, data0, 0);
637 let Inst{55-48} = !if(ds.has_data1, data1, 0);
638 let Inst{63-56} = !if(ds.has_vdst, vdst, 0);
639}
640
641def DS_ADD_U32_si : DS_Real_si<0x0, DS_ADD_U32>;
642def DS_SUB_U32_si : DS_Real_si<0x1, DS_SUB_U32>;
643def DS_RSUB_U32_si : DS_Real_si<0x2, DS_RSUB_U32>;
644def DS_INC_U32_si : DS_Real_si<0x3, DS_INC_U32>;
645def DS_DEC_U32_si : DS_Real_si<0x4, DS_DEC_U32>;
646def DS_MIN_I32_si : DS_Real_si<0x5, DS_MIN_I32>;
647def DS_MAX_I32_si : DS_Real_si<0x6, DS_MAX_I32>;
648def DS_MIN_U32_si : DS_Real_si<0x7, DS_MIN_U32>;
649def DS_MAX_U32_si : DS_Real_si<0x8, DS_MAX_U32>;
650def DS_AND_B32_si : DS_Real_si<0x9, DS_AND_B32>;
651def DS_OR_B32_si : DS_Real_si<0xa, DS_OR_B32>;
652def DS_XOR_B32_si : DS_Real_si<0xb, DS_XOR_B32>;
653def DS_MSKOR_B32_si : DS_Real_si<0xc, DS_MSKOR_B32>;
654def DS_WRITE_B32_si : DS_Real_si<0xd, DS_WRITE_B32>;
655def DS_WRITE2_B32_si : DS_Real_si<0xe, DS_WRITE2_B32>;
656def DS_WRITE2ST64_B32_si : DS_Real_si<0xf, DS_WRITE2ST64_B32>;
657def DS_CMPST_B32_si : DS_Real_si<0x10, DS_CMPST_B32>;
658def DS_CMPST_F32_si : DS_Real_si<0x11, DS_CMPST_F32>;
659def DS_MIN_F32_si : DS_Real_si<0x12, DS_MIN_F32>;
660def DS_MAX_F32_si : DS_Real_si<0x13, DS_MAX_F32>;
Matt Arsenault78124982017-02-28 20:15:46 +0000[diff] [blame]661def DS_NOP_si : DS_Real_si<0x14, DS_NOP>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]662def DS_GWS_INIT_si : DS_Real_si<0x19, DS_GWS_INIT>;
663def DS_GWS_SEMA_V_si : DS_Real_si<0x1a, DS_GWS_SEMA_V>;
664def DS_GWS_SEMA_BR_si : DS_Real_si<0x1b, DS_GWS_SEMA_BR>;
665def DS_GWS_SEMA_P_si : DS_Real_si<0x1c, DS_GWS_SEMA_P>;
666def DS_GWS_BARRIER_si : DS_Real_si<0x1d, DS_GWS_BARRIER>;
667def DS_WRITE_B8_si : DS_Real_si<0x1e, DS_WRITE_B8>;
668def DS_WRITE_B16_si : DS_Real_si<0x1f, DS_WRITE_B16>;
669def DS_ADD_RTN_U32_si : DS_Real_si<0x20, DS_ADD_RTN_U32>;
670def DS_SUB_RTN_U32_si : DS_Real_si<0x21, DS_SUB_RTN_U32>;
671def DS_RSUB_RTN_U32_si : DS_Real_si<0x22, DS_RSUB_RTN_U32>;
672def DS_INC_RTN_U32_si : DS_Real_si<0x23, DS_INC_RTN_U32>;
673def DS_DEC_RTN_U32_si : DS_Real_si<0x24, DS_DEC_RTN_U32>;
674def DS_MIN_RTN_I32_si : DS_Real_si<0x25, DS_MIN_RTN_I32>;
675def DS_MAX_RTN_I32_si : DS_Real_si<0x26, DS_MAX_RTN_I32>;
676def DS_MIN_RTN_U32_si : DS_Real_si<0x27, DS_MIN_RTN_U32>;
677def DS_MAX_RTN_U32_si : DS_Real_si<0x28, DS_MAX_RTN_U32>;
678def DS_AND_RTN_B32_si : DS_Real_si<0x29, DS_AND_RTN_B32>;
679def DS_OR_RTN_B32_si : DS_Real_si<0x2a, DS_OR_RTN_B32>;
680def DS_XOR_RTN_B32_si : DS_Real_si<0x2b, DS_XOR_RTN_B32>;
681def DS_MSKOR_RTN_B32_si : DS_Real_si<0x2c, DS_MSKOR_RTN_B32>;
682def DS_WRXCHG_RTN_B32_si : DS_Real_si<0x2d, DS_WRXCHG_RTN_B32>;
683def DS_WRXCHG2_RTN_B32_si : DS_Real_si<0x2e, DS_WRXCHG2_RTN_B32>;
684def DS_WRXCHG2ST64_RTN_B32_si : DS_Real_si<0x2f, DS_WRXCHG2ST64_RTN_B32>;
685def DS_CMPST_RTN_B32_si : DS_Real_si<0x30, DS_CMPST_RTN_B32>;
686def DS_CMPST_RTN_F32_si : DS_Real_si<0x31, DS_CMPST_RTN_F32>;
687def DS_MIN_RTN_F32_si : DS_Real_si<0x32, DS_MIN_RTN_F32>;
688def DS_MAX_RTN_F32_si : DS_Real_si<0x33, DS_MAX_RTN_F32>;
689
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]690// These instruction are CI/VI only
691def DS_WRAP_RTN_B32_si : DS_Real_si<0x34, DS_WRAP_RTN_B32>;
692def DS_CONDXCHG32_RTN_B64_si : DS_Real_si<0x7e, DS_CONDXCHG32_RTN_B64>;
693def DS_GWS_SEMA_RELEASE_ALL_si : DS_Real_si<0x18, DS_GWS_SEMA_RELEASE_ALL>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]694
695def DS_SWIZZLE_B32_si : DS_Real_si<0x35, DS_SWIZZLE_B32>;
696def DS_READ_B32_si : DS_Real_si<0x36, DS_READ_B32>;
697def DS_READ2_B32_si : DS_Real_si<0x37, DS_READ2_B32>;
698def DS_READ2ST64_B32_si : DS_Real_si<0x38, DS_READ2ST64_B32>;
699def DS_READ_I8_si : DS_Real_si<0x39, DS_READ_I8>;
700def DS_READ_U8_si : DS_Real_si<0x3a, DS_READ_U8>;
701def DS_READ_I16_si : DS_Real_si<0x3b, DS_READ_I16>;
702def DS_READ_U16_si : DS_Real_si<0x3c, DS_READ_U16>;
703def DS_CONSUME_si : DS_Real_si<0x3d, DS_CONSUME>;
704def DS_APPEND_si : DS_Real_si<0x3e, DS_APPEND>;
705def DS_ORDERED_COUNT_si : DS_Real_si<0x3f, DS_ORDERED_COUNT>;
706def DS_ADD_U64_si : DS_Real_si<0x40, DS_ADD_U64>;
707def DS_SUB_U64_si : DS_Real_si<0x41, DS_SUB_U64>;
708def DS_RSUB_U64_si : DS_Real_si<0x42, DS_RSUB_U64>;
709def DS_INC_U64_si : DS_Real_si<0x43, DS_INC_U64>;
710def DS_DEC_U64_si : DS_Real_si<0x44, DS_DEC_U64>;
711def DS_MIN_I64_si : DS_Real_si<0x45, DS_MIN_I64>;
712def DS_MAX_I64_si : DS_Real_si<0x46, DS_MAX_I64>;
713def DS_MIN_U64_si : DS_Real_si<0x47, DS_MIN_U64>;
714def DS_MAX_U64_si : DS_Real_si<0x48, DS_MAX_U64>;
715def DS_AND_B64_si : DS_Real_si<0x49, DS_AND_B64>;
716def DS_OR_B64_si : DS_Real_si<0x4a, DS_OR_B64>;
717def DS_XOR_B64_si : DS_Real_si<0x4b, DS_XOR_B64>;
718def DS_MSKOR_B64_si : DS_Real_si<0x4c, DS_MSKOR_B64>;
719def DS_WRITE_B64_si : DS_Real_si<0x4d, DS_WRITE_B64>;
720def DS_WRITE2_B64_si : DS_Real_si<0x4E, DS_WRITE2_B64>;
721def DS_WRITE2ST64_B64_si : DS_Real_si<0x4f, DS_WRITE2ST64_B64>;
722def DS_CMPST_B64_si : DS_Real_si<0x50, DS_CMPST_B64>;
723def DS_CMPST_F64_si : DS_Real_si<0x51, DS_CMPST_F64>;
724def DS_MIN_F64_si : DS_Real_si<0x52, DS_MIN_F64>;
725def DS_MAX_F64_si : DS_Real_si<0x53, DS_MAX_F64>;
726
727def DS_ADD_RTN_U64_si : DS_Real_si<0x60, DS_ADD_RTN_U64>;
728def DS_SUB_RTN_U64_si : DS_Real_si<0x61, DS_SUB_RTN_U64>;
729def DS_RSUB_RTN_U64_si : DS_Real_si<0x62, DS_RSUB_RTN_U64>;
730def DS_INC_RTN_U64_si : DS_Real_si<0x63, DS_INC_RTN_U64>;
731def DS_DEC_RTN_U64_si : DS_Real_si<0x64, DS_DEC_RTN_U64>;
732def DS_MIN_RTN_I64_si : DS_Real_si<0x65, DS_MIN_RTN_I64>;
733def DS_MAX_RTN_I64_si : DS_Real_si<0x66, DS_MAX_RTN_I64>;
734def DS_MIN_RTN_U64_si : DS_Real_si<0x67, DS_MIN_RTN_U64>;
735def DS_MAX_RTN_U64_si : DS_Real_si<0x68, DS_MAX_RTN_U64>;
736def DS_AND_RTN_B64_si : DS_Real_si<0x69, DS_AND_RTN_B64>;
737def DS_OR_RTN_B64_si : DS_Real_si<0x6a, DS_OR_RTN_B64>;
738def DS_XOR_RTN_B64_si : DS_Real_si<0x6b, DS_XOR_RTN_B64>;
739def DS_MSKOR_RTN_B64_si : DS_Real_si<0x6c, DS_MSKOR_RTN_B64>;
740def DS_WRXCHG_RTN_B64_si : DS_Real_si<0x6d, DS_WRXCHG_RTN_B64>;
741def DS_WRXCHG2_RTN_B64_si : DS_Real_si<0x6e, DS_WRXCHG2_RTN_B64>;
742def DS_WRXCHG2ST64_RTN_B64_si : DS_Real_si<0x6f, DS_WRXCHG2ST64_RTN_B64>;
743def DS_CMPST_RTN_B64_si : DS_Real_si<0x70, DS_CMPST_RTN_B64>;
744def DS_CMPST_RTN_F64_si : DS_Real_si<0x71, DS_CMPST_RTN_F64>;
745def DS_MIN_RTN_F64_si : DS_Real_si<0x72, DS_MIN_RTN_F64>;
746def DS_MAX_RTN_F64_si : DS_Real_si<0x73, DS_MAX_RTN_F64>;
747
748def DS_READ_B64_si : DS_Real_si<0x76, DS_READ_B64>;
749def DS_READ2_B64_si : DS_Real_si<0x77, DS_READ2_B64>;
750def DS_READ2ST64_B64_si : DS_Real_si<0x78, DS_READ2ST64_B64>;
751
752def DS_ADD_SRC2_U32_si : DS_Real_si<0x80, DS_ADD_SRC2_U32>;
753def DS_SUB_SRC2_U32_si : DS_Real_si<0x81, DS_SUB_SRC2_U32>;
754def DS_RSUB_SRC2_U32_si : DS_Real_si<0x82, DS_RSUB_SRC2_U32>;
755def DS_INC_SRC2_U32_si : DS_Real_si<0x83, DS_INC_SRC2_U32>;
756def DS_DEC_SRC2_U32_si : DS_Real_si<0x84, DS_DEC_SRC2_U32>;
757def DS_MIN_SRC2_I32_si : DS_Real_si<0x85, DS_MIN_SRC2_I32>;
758def DS_MAX_SRC2_I32_si : DS_Real_si<0x86, DS_MAX_SRC2_I32>;
759def DS_MIN_SRC2_U32_si : DS_Real_si<0x87, DS_MIN_SRC2_U32>;
760def DS_MAX_SRC2_U32_si : DS_Real_si<0x88, DS_MAX_SRC2_U32>;
761def DS_AND_SRC2_B32_si : DS_Real_si<0x89, DS_AND_SRC2_B32>;
762def DS_OR_SRC2_B32_si : DS_Real_si<0x8a, DS_OR_SRC2_B32>;
763def DS_XOR_SRC2_B32_si : DS_Real_si<0x8b, DS_XOR_SRC2_B32>;
764def DS_WRITE_SRC2_B32_si : DS_Real_si<0x8d, DS_WRITE_SRC2_B32>;
765
766def DS_MIN_SRC2_F32_si : DS_Real_si<0x92, DS_MIN_SRC2_F32>;
767def DS_MAX_SRC2_F32_si : DS_Real_si<0x93, DS_MAX_SRC2_F32>;
768
769def DS_ADD_SRC2_U64_si : DS_Real_si<0xc0, DS_ADD_SRC2_U64>;
770def DS_SUB_SRC2_U64_si : DS_Real_si<0xc1, DS_SUB_SRC2_U64>;
771def DS_RSUB_SRC2_U64_si : DS_Real_si<0xc2, DS_RSUB_SRC2_U64>;
772def DS_INC_SRC2_U64_si : DS_Real_si<0xc3, DS_INC_SRC2_U64>;
773def DS_DEC_SRC2_U64_si : DS_Real_si<0xc4, DS_DEC_SRC2_U64>;
774def DS_MIN_SRC2_I64_si : DS_Real_si<0xc5, DS_MIN_SRC2_I64>;
775def DS_MAX_SRC2_I64_si : DS_Real_si<0xc6, DS_MAX_SRC2_I64>;
776def DS_MIN_SRC2_U64_si : DS_Real_si<0xc7, DS_MIN_SRC2_U64>;
777def DS_MAX_SRC2_U64_si : DS_Real_si<0xc8, DS_MAX_SRC2_U64>;
778def DS_AND_SRC2_B64_si : DS_Real_si<0xc9, DS_AND_SRC2_B64>;
779def DS_OR_SRC2_B64_si : DS_Real_si<0xca, DS_OR_SRC2_B64>;
780def DS_XOR_SRC2_B64_si : DS_Real_si<0xcb, DS_XOR_SRC2_B64>;
781def DS_WRITE_SRC2_B64_si : DS_Real_si<0xcd, DS_WRITE_SRC2_B64>;
782
783def DS_MIN_SRC2_F64_si : DS_Real_si<0xd2, DS_MIN_SRC2_F64>;
784def DS_MAX_SRC2_F64_si : DS_Real_si<0xd3, DS_MAX_SRC2_F64>;
Matt Arsenaultdedc5442017-02-28 20:15:43 +0000[diff] [blame]785def DS_WRITE_B96_si : DS_Real_si<0xde, DS_WRITE_B96>;
786def DS_WRITE_B128_si : DS_Real_si<0xdf, DS_WRITE_B128>;
787def DS_READ_B96_si : DS_Real_si<0xfe, DS_READ_B96>;
788def DS_READ_B128_si : DS_Real_si<0xff, DS_READ_B128>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]789
790//===----------------------------------------------------------------------===//
791// VIInstructions.td
792//===----------------------------------------------------------------------===//
793
794class DS_Real_vi <bits<8> op, DS_Pseudo ds> :
795 DS_Real <ds>,
796 SIMCInstr <ds.Mnemonic, SIEncodingFamily.VI> {
797 let AssemblerPredicates = [isVI];
798 let DecoderNamespace="VI";
799
Matt Arsenaultf3dd8632016-11-01 00:55:14 +0000[diff] [blame]800 // encoding
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]801 let Inst{7-0} = !if(ds.has_offset0, offset0, 0);
802 let Inst{15-8} = !if(ds.has_offset1, offset1, 0);
803 let Inst{16} = !if(ds.has_gds, gds, ds.gdsValue);
804 let Inst{24-17} = op;
805 let Inst{31-26} = 0x36; // ds prefix
806 let Inst{39-32} = !if(ds.has_addr, addr, 0);
807 let Inst{47-40} = !if(ds.has_data0, data0, 0);
808 let Inst{55-48} = !if(ds.has_data1, data1, 0);
809 let Inst{63-56} = !if(ds.has_vdst, vdst, 0);
810}
811
812def DS_ADD_U32_vi : DS_Real_vi<0x0, DS_ADD_U32>;
813def DS_SUB_U32_vi : DS_Real_vi<0x1, DS_SUB_U32>;
814def DS_RSUB_U32_vi : DS_Real_vi<0x2, DS_RSUB_U32>;
815def DS_INC_U32_vi : DS_Real_vi<0x3, DS_INC_U32>;
816def DS_DEC_U32_vi : DS_Real_vi<0x4, DS_DEC_U32>;
817def DS_MIN_I32_vi : DS_Real_vi<0x5, DS_MIN_I32>;
818def DS_MAX_I32_vi : DS_Real_vi<0x6, DS_MAX_I32>;
819def DS_MIN_U32_vi : DS_Real_vi<0x7, DS_MIN_U32>;
820def DS_MAX_U32_vi : DS_Real_vi<0x8, DS_MAX_U32>;
821def DS_AND_B32_vi : DS_Real_vi<0x9, DS_AND_B32>;
822def DS_OR_B32_vi : DS_Real_vi<0xa, DS_OR_B32>;
823def DS_XOR_B32_vi : DS_Real_vi<0xb, DS_XOR_B32>;
824def DS_MSKOR_B32_vi : DS_Real_vi<0xc, DS_MSKOR_B32>;
825def DS_WRITE_B32_vi : DS_Real_vi<0xd, DS_WRITE_B32>;
826def DS_WRITE2_B32_vi : DS_Real_vi<0xe, DS_WRITE2_B32>;
827def DS_WRITE2ST64_B32_vi : DS_Real_vi<0xf, DS_WRITE2ST64_B32>;
828def DS_CMPST_B32_vi : DS_Real_vi<0x10, DS_CMPST_B32>;
829def DS_CMPST_F32_vi : DS_Real_vi<0x11, DS_CMPST_F32>;
830def DS_MIN_F32_vi : DS_Real_vi<0x12, DS_MIN_F32>;
831def DS_MAX_F32_vi : DS_Real_vi<0x13, DS_MAX_F32>;
Matt Arsenault78124982017-02-28 20:15:46 +0000[diff] [blame]832def DS_NOP_vi : DS_Real_vi<0x14, DS_NOP>;
Artem Tamazov2e217b82016-09-21 16:35:44 +0000[diff] [blame]833def DS_ADD_F32_vi : DS_Real_vi<0x15, DS_ADD_F32>;
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]834def DS_GWS_INIT_vi : DS_Real_vi<0x99, DS_GWS_INIT>;
835def DS_GWS_SEMA_V_vi : DS_Real_vi<0x9a, DS_GWS_SEMA_V>;
836def DS_GWS_SEMA_BR_vi : DS_Real_vi<0x9b, DS_GWS_SEMA_BR>;
837def DS_GWS_SEMA_P_vi : DS_Real_vi<0x9c, DS_GWS_SEMA_P>;
838def DS_GWS_BARRIER_vi : DS_Real_vi<0x9d, DS_GWS_BARRIER>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]839def DS_WRITE_B8_vi : DS_Real_vi<0x1e, DS_WRITE_B8>;
840def DS_WRITE_B16_vi : DS_Real_vi<0x1f, DS_WRITE_B16>;
841def DS_ADD_RTN_U32_vi : DS_Real_vi<0x20, DS_ADD_RTN_U32>;
842def DS_SUB_RTN_U32_vi : DS_Real_vi<0x21, DS_SUB_RTN_U32>;
843def DS_RSUB_RTN_U32_vi : DS_Real_vi<0x22, DS_RSUB_RTN_U32>;
844def DS_INC_RTN_U32_vi : DS_Real_vi<0x23, DS_INC_RTN_U32>;
845def DS_DEC_RTN_U32_vi : DS_Real_vi<0x24, DS_DEC_RTN_U32>;
846def DS_MIN_RTN_I32_vi : DS_Real_vi<0x25, DS_MIN_RTN_I32>;
847def DS_MAX_RTN_I32_vi : DS_Real_vi<0x26, DS_MAX_RTN_I32>;
848def DS_MIN_RTN_U32_vi : DS_Real_vi<0x27, DS_MIN_RTN_U32>;
849def DS_MAX_RTN_U32_vi : DS_Real_vi<0x28, DS_MAX_RTN_U32>;
850def DS_AND_RTN_B32_vi : DS_Real_vi<0x29, DS_AND_RTN_B32>;
851def DS_OR_RTN_B32_vi : DS_Real_vi<0x2a, DS_OR_RTN_B32>;
852def DS_XOR_RTN_B32_vi : DS_Real_vi<0x2b, DS_XOR_RTN_B32>;
853def DS_MSKOR_RTN_B32_vi : DS_Real_vi<0x2c, DS_MSKOR_RTN_B32>;
854def DS_WRXCHG_RTN_B32_vi : DS_Real_vi<0x2d, DS_WRXCHG_RTN_B32>;
855def DS_WRXCHG2_RTN_B32_vi : DS_Real_vi<0x2e, DS_WRXCHG2_RTN_B32>;
856def DS_WRXCHG2ST64_RTN_B32_vi : DS_Real_vi<0x2f, DS_WRXCHG2ST64_RTN_B32>;
857def DS_CMPST_RTN_B32_vi : DS_Real_vi<0x30, DS_CMPST_RTN_B32>;
858def DS_CMPST_RTN_F32_vi : DS_Real_vi<0x31, DS_CMPST_RTN_F32>;
859def DS_MIN_RTN_F32_vi : DS_Real_vi<0x32, DS_MIN_RTN_F32>;
860def DS_MAX_RTN_F32_vi : DS_Real_vi<0x33, DS_MAX_RTN_F32>;
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]861def DS_WRAP_RTN_B32_vi : DS_Real_vi<0x34, DS_WRAP_RTN_B32>;
Artem Tamazov2e217b82016-09-21 16:35:44 +0000[diff] [blame]862def DS_ADD_RTN_F32_vi : DS_Real_vi<0x35, DS_ADD_RTN_F32>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]863def DS_READ_B32_vi : DS_Real_vi<0x36, DS_READ_B32>;
864def DS_READ2_B32_vi : DS_Real_vi<0x37, DS_READ2_B32>;
865def DS_READ2ST64_B32_vi : DS_Real_vi<0x38, DS_READ2ST64_B32>;
866def DS_READ_I8_vi : DS_Real_vi<0x39, DS_READ_I8>;
867def DS_READ_U8_vi : DS_Real_vi<0x3a, DS_READ_U8>;
868def DS_READ_I16_vi : DS_Real_vi<0x3b, DS_READ_I16>;
869def DS_READ_U16_vi : DS_Real_vi<0x3c, DS_READ_U16>;
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]870def DS_CONSUME_vi : DS_Real_vi<0xbd, DS_CONSUME>;
871def DS_APPEND_vi : DS_Real_vi<0xbe, DS_APPEND>;
872def DS_ORDERED_COUNT_vi : DS_Real_vi<0xbf, DS_ORDERED_COUNT>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]873def DS_SWIZZLE_B32_vi : DS_Real_vi<0x3d, DS_SWIZZLE_B32>;
874def DS_PERMUTE_B32_vi : DS_Real_vi<0x3e, DS_PERMUTE_B32>;
875def DS_BPERMUTE_B32_vi : DS_Real_vi<0x3f, DS_BPERMUTE_B32>;
876
877def DS_ADD_U64_vi : DS_Real_vi<0x40, DS_ADD_U64>;
878def DS_SUB_U64_vi : DS_Real_vi<0x41, DS_SUB_U64>;
879def DS_RSUB_U64_vi : DS_Real_vi<0x42, DS_RSUB_U64>;
880def DS_INC_U64_vi : DS_Real_vi<0x43, DS_INC_U64>;
881def DS_DEC_U64_vi : DS_Real_vi<0x44, DS_DEC_U64>;
882def DS_MIN_I64_vi : DS_Real_vi<0x45, DS_MIN_I64>;
883def DS_MAX_I64_vi : DS_Real_vi<0x46, DS_MAX_I64>;
884def DS_MIN_U64_vi : DS_Real_vi<0x47, DS_MIN_U64>;
885def DS_MAX_U64_vi : DS_Real_vi<0x48, DS_MAX_U64>;
886def DS_AND_B64_vi : DS_Real_vi<0x49, DS_AND_B64>;
887def DS_OR_B64_vi : DS_Real_vi<0x4a, DS_OR_B64>;
888def DS_XOR_B64_vi : DS_Real_vi<0x4b, DS_XOR_B64>;
889def DS_MSKOR_B64_vi : DS_Real_vi<0x4c, DS_MSKOR_B64>;
890def DS_WRITE_B64_vi : DS_Real_vi<0x4d, DS_WRITE_B64>;
891def DS_WRITE2_B64_vi : DS_Real_vi<0x4E, DS_WRITE2_B64>;
892def DS_WRITE2ST64_B64_vi : DS_Real_vi<0x4f, DS_WRITE2ST64_B64>;
893def DS_CMPST_B64_vi : DS_Real_vi<0x50, DS_CMPST_B64>;
894def DS_CMPST_F64_vi : DS_Real_vi<0x51, DS_CMPST_F64>;
895def DS_MIN_F64_vi : DS_Real_vi<0x52, DS_MIN_F64>;
896def DS_MAX_F64_vi : DS_Real_vi<0x53, DS_MAX_F64>;
897
898def DS_ADD_RTN_U64_vi : DS_Real_vi<0x60, DS_ADD_RTN_U64>;
899def DS_SUB_RTN_U64_vi : DS_Real_vi<0x61, DS_SUB_RTN_U64>;
900def DS_RSUB_RTN_U64_vi : DS_Real_vi<0x62, DS_RSUB_RTN_U64>;
901def DS_INC_RTN_U64_vi : DS_Real_vi<0x63, DS_INC_RTN_U64>;
902def DS_DEC_RTN_U64_vi : DS_Real_vi<0x64, DS_DEC_RTN_U64>;
903def DS_MIN_RTN_I64_vi : DS_Real_vi<0x65, DS_MIN_RTN_I64>;
904def DS_MAX_RTN_I64_vi : DS_Real_vi<0x66, DS_MAX_RTN_I64>;
905def DS_MIN_RTN_U64_vi : DS_Real_vi<0x67, DS_MIN_RTN_U64>;
906def DS_MAX_RTN_U64_vi : DS_Real_vi<0x68, DS_MAX_RTN_U64>;
907def DS_AND_RTN_B64_vi : DS_Real_vi<0x69, DS_AND_RTN_B64>;
908def DS_OR_RTN_B64_vi : DS_Real_vi<0x6a, DS_OR_RTN_B64>;
909def DS_XOR_RTN_B64_vi : DS_Real_vi<0x6b, DS_XOR_RTN_B64>;
910def DS_MSKOR_RTN_B64_vi : DS_Real_vi<0x6c, DS_MSKOR_RTN_B64>;
911def DS_WRXCHG_RTN_B64_vi : DS_Real_vi<0x6d, DS_WRXCHG_RTN_B64>;
912def DS_WRXCHG2_RTN_B64_vi : DS_Real_vi<0x6e, DS_WRXCHG2_RTN_B64>;
913def DS_WRXCHG2ST64_RTN_B64_vi : DS_Real_vi<0x6f, DS_WRXCHG2ST64_RTN_B64>;
Dmitry Preobrazhenskye5147242017-04-07 13:07:13 +0000[diff] [blame]914def DS_CONDXCHG32_RTN_B64_vi : DS_Real_vi<0x7e, DS_CONDXCHG32_RTN_B64>;
915def DS_GWS_SEMA_RELEASE_ALL_vi : DS_Real_vi<0x98, DS_GWS_SEMA_RELEASE_ALL>;
Valery Pykhtin902db312016-08-01 14:21:30 +0000[diff] [blame]916def DS_CMPST_RTN_B64_vi : DS_Real_vi<0x70, DS_CMPST_RTN_B64>;
917def DS_CMPST_RTN_F64_vi : DS_Real_vi<0x71, DS_CMPST_RTN_F64>;
918def DS_MIN_RTN_F64_vi : DS_Real_vi<0x72, DS_MIN_RTN_F64>;
919def DS_MAX_RTN_F64_vi : DS_Real_vi<0x73, DS_MAX_RTN_F64>;
920
921def DS_READ_B64_vi : DS_Real_vi<0x76, DS_READ_B64>;
922def DS_READ2_B64_vi : DS_Real_vi<0x77, DS_READ2_B64>;
923def DS_READ2ST64_B64_vi : DS_Real_vi<0x78, DS_READ2ST64_B64>;
924
925def DS_ADD_SRC2_U32_vi : DS_Real_vi<0x80, DS_ADD_SRC2_U32>;
926def DS_SUB_SRC2_U32_vi : DS_Real_vi<0x81, DS_SUB_SRC2_U32>;
927def DS_RSUB_SRC2_U32_vi : DS_Real_vi<0x82, DS_RSUB_SRC2_U32>;
928def DS_INC_SRC2_U32_vi : DS_Real_vi<0x83, DS_INC_SRC2_U32>;
929def DS_DEC_SRC2_U32_vi : DS_Real_vi<0x84, DS_DEC_SRC2_U32>;
930def DS_MIN_SRC2_I32_vi : DS_Real_vi<0x85, DS_MIN_SRC2_I32>;
931def DS_MAX_SRC2_I32_vi : DS_Real_vi<0x86, DS_MAX_SRC2_I32>;
932def DS_MIN_SRC2_U32_vi : DS_Real_vi<0x87, DS_MIN_SRC2_U32>;
933def DS_MAX_SRC2_U32_vi : DS_Real_vi<0x88, DS_MAX_SRC2_U32>;
934def DS_AND_SRC2_B32_vi : DS_Real_vi<0x89, DS_AND_SRC2_B32>;
935def DS_OR_SRC2_B32_vi : DS_Real_vi<0x8a, DS_OR_SRC2_B32>;
936def DS_XOR_SRC2_B32_vi : DS_Real_vi<0x8b, DS_XOR_SRC2_B32>;
937def DS_WRITE_SRC2_B32_vi : DS_Real_vi<0x8d, DS_WRITE_SRC2_B32>;
938def DS_MIN_SRC2_F32_vi : DS_Real_vi<0x92, DS_MIN_SRC2_F32>;
939def DS_MAX_SRC2_F32_vi : DS_Real_vi<0x93, DS_MAX_SRC2_F32>;
940def DS_ADD_SRC2_U64_vi : DS_Real_vi<0xc0, DS_ADD_SRC2_U64>;
941def DS_SUB_SRC2_U64_vi : DS_Real_vi<0xc1, DS_SUB_SRC2_U64>;
942def DS_RSUB_SRC2_U64_vi : DS_Real_vi<0xc2, DS_RSUB_SRC2_U64>;
943def DS_INC_SRC2_U64_vi : DS_Real_vi<0xc3, DS_INC_SRC2_U64>;
944def DS_DEC_SRC2_U64_vi : DS_Real_vi<0xc4, DS_DEC_SRC2_U64>;
945def DS_MIN_SRC2_I64_vi : DS_Real_vi<0xc5, DS_MIN_SRC2_I64>;
946def DS_MAX_SRC2_I64_vi : DS_Real_vi<0xc6, DS_MAX_SRC2_I64>;
947def DS_MIN_SRC2_U64_vi : DS_Real_vi<0xc7, DS_MIN_SRC2_U64>;
948def DS_MAX_SRC2_U64_vi : DS_Real_vi<0xc8, DS_MAX_SRC2_U64>;
949def DS_AND_SRC2_B64_vi : DS_Real_vi<0xc9, DS_AND_SRC2_B64>;
950def DS_OR_SRC2_B64_vi : DS_Real_vi<0xca, DS_OR_SRC2_B64>;
951def DS_XOR_SRC2_B64_vi : DS_Real_vi<0xcb, DS_XOR_SRC2_B64>;
952def DS_WRITE_SRC2_B64_vi : DS_Real_vi<0xcd, DS_WRITE_SRC2_B64>;
953def DS_MIN_SRC2_F64_vi : DS_Real_vi<0xd2, DS_MIN_SRC2_F64>;
954def DS_MAX_SRC2_F64_vi : DS_Real_vi<0xd3, DS_MAX_SRC2_F64>;
Matt Arsenaultdedc5442017-02-28 20:15:43 +0000[diff] [blame]955def DS_WRITE_B96_vi : DS_Real_vi<0xde, DS_WRITE_B96>;
956def DS_WRITE_B128_vi : DS_Real_vi<0xdf, DS_WRITE_B128>;
957def DS_READ_B96_vi : DS_Real_vi<0xfe, DS_READ_B96>;
958def DS_READ_B128_vi : DS_Real_vi<0xff, DS_READ_B128>;