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gerrit-public.fairphone.software / toolchain / llvm-project / d08918684e8ec61c21de4f47fa1758bdf55a91b8 / . / llvm / lib / Target / ARM / ARM.td
blob: 96c7a91f7507f62363953a2959e7cc326f4e3e09 [file] [log] [blame]
Jia Liub22310f2012-02-18 12:03:15 +0000[diff] [blame]1//===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
Rafael Espindolaffdc24b2006-05-14 22:18:28 +0000[diff] [blame]2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattnerf3ebc3f2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
Rafael Espindolaffdc24b2006-05-14 22:18:28 +0000[diff] [blame]6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10//
11//===----------------------------------------------------------------------===//
12
13//===----------------------------------------------------------------------===//
14// Target-independent interfaces which we are implementing
15//===----------------------------------------------------------------------===//
16
Evan Cheng977e7be2008-11-24 07:34:46 +0000[diff] [blame]17include "llvm/Target/Target.td"
Rafael Espindolaffdc24b2006-05-14 22:18:28 +0000[diff] [blame]18
Evan Chengf2c26162011-07-07 08:26:46 +0000[diff] [blame]19//===----------------------------------------------------------------------===//
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]20// ARM Helper classes.
21//
22
23class ProcNoItin<string Name, list<SubtargetFeature> Features>
24 : Processor<Name, NoItineraries, Features>;
25
26class Architecture<string fname, string aname, list<SubtargetFeature> features >
27 : SubtargetFeature<fname, "ARMArch", aname,
28 !strconcat(aname, " architecture"), features>;
29
30//===----------------------------------------------------------------------===//
Evan Chengf2c26162011-07-07 08:26:46 +0000[diff] [blame]31// ARM Subtarget state.
32//
33
Evan Cheng1834f5d2011-07-07 19:05:12 +0000[diff] [blame]34def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
Evan Chengf2c26162011-07-07 08:26:46 +0000[diff] [blame]35 "Thumb mode">;
Jim Grosbach080fdf42010-09-30 01:57:53 +0000[diff] [blame]36
Eric Christopher824f42f2015-05-12 01:26:05 +0000[diff] [blame]37def ModeSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
38 "Use software floating point features.">;
39
Rafael Espindolaffdc24b2006-05-14 22:18:28 +0000[diff] [blame]40//===----------------------------------------------------------------------===//
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]41// ARM Subtarget features.
42//
43
Evan Cheng8b2bda02011-07-07 03:55:05 +0000[diff] [blame]44def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
Anton Korobeynikovb6f45382009-05-29 23:41:08 +0000[diff] [blame]45 "Enable VFP2 instructions">;
Evan Cheng8b2bda02011-07-07 03:55:05 +0000[diff] [blame]46def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
47 "Enable VFP3 instructions",
48 [FeatureVFP2]>;
49def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
50 "Enable NEON instructions",
51 [FeatureVFP3]>;
Evan Cheng2bd65362011-07-07 00:08:19 +0000[diff] [blame]52def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
Anton Korobeynikovb6f45382009-05-29 23:41:08 +0000[diff] [blame]53 "Enable Thumb2 instructions">;
Evan Cheng5190f092010-08-11 07:17:46 +0000[diff] [blame]54def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
Tim Northovera2292d02013-06-10 23:20:58 +0000[diff] [blame]55 "Does not support ARM mode execution",
56 [ModeThumb]>;
Anton Korobeynikov0a65a372010-03-14 18:42:38 +0000[diff] [blame]57def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
58 "Enable half-precision floating point">;
Bob Wilsone8a549c2012-09-29 21:43:49 +0000[diff] [blame]59def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true",
60 "Enable VFP4 instructions",
61 [FeatureVFP3, FeatureFP16]>;
Joey Goulyccd04892013-09-13 13:46:57 +0000[diff] [blame]62def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8",
Joey Goulyb1b0dd82013-06-27 11:49:26 +0000[diff] [blame]63 "true", "Enable ARMv8 FP",
64 [FeatureVFP4]>;
Oliver Stannard8addbf42015-12-01 10:23:06 +0000[diff] [blame]65def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
66 "Enable full half-precision floating point",
67 [FeatureFPARMv8]>;
Bob Wilsondd6eb5b2010-10-12 16:22:47 +0000[diff] [blame]68def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true",
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]69 "Restrict FP to 16 double registers">;
Jim Grosbach151cd8f2010-05-05 23:44:43 +0000[diff] [blame]70def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
71 "Enable divide instructions">;
Bob Wilsone8a549c2012-09-29 21:43:49 +0000[diff] [blame]72def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm",
73 "HasHardwareDivideInARM", "true",
74 "Enable divide instructions in ARM mode">;
Evan Cheng40921a42010-08-11 06:51:54 +0000[diff] [blame]75def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
Jim Grosbach151cd8f2010-05-05 23:44:43 +0000[diff] [blame]76 "Enable Thumb2 extract and pack instructions">;
Evan Cheng40921a42010-08-11 06:51:54 +0000[diff] [blame]77def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",
78 "Has data barrier (dmb / dsb) instructions">;
Bradley Smith4c21cba2016-01-15 10:23:46 +0000[diff] [blame]79def FeatureV7Clrex : SubtargetFeature<"v7clrex", "HasV7Clrex", "true",
80 "Has v7 clrex instruction">;
81def FeatureAcquireRelease : SubtargetFeature<"acquire-release",
82 "HasAcquireRelease", "true",
83 "Has v8 acquire/release (lda/ldaex etc) instructions">;
Evan Cheng58066e32010-07-13 19:21:50 +0000[diff] [blame]84def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
85 "FP compare + branch is slow">;
Jim Grosbach4d5dc3e2010-08-11 15:44:15 +0000[diff] [blame]86def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
87 "Floating point unit supports single precision only">;
Tim Northovercedd4812013-05-23 19:11:14 +0000[diff] [blame]88def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
89 "Enable support for Performance Monitor extensions">;
Tim Northoverc6047652013-04-10 12:08:35 +0000[diff] [blame]90def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",
91 "Enable support for TrustZone security extensions">;
Bradley Smithfed3e4a2016-01-25 11:24:47 +0000[diff] [blame]92def Feature8MSecExt : SubtargetFeature<"8msecext", "Has8MSecExt", "true",
93 "Enable support for ARMv8-M Security Extensions">;
Amara Emerson33089092013-09-19 11:59:01 +0000[diff] [blame]94def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
95 "Enable support for Cryptography extensions",
96 [FeatureNEON]>;
Bernard Ogdenee87e852013-10-29 09:47:35 +0000[diff] [blame]97def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
98 "Enable support for CRC instructions">;
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]99
Tim Northover13510302014-04-01 13:22:02 +0000[diff] [blame]100// Cyclone has preferred instructions for zeroing VFP registers, which can
101// execute in 0 cycles.
102def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
103 "Has zero-cycle zeroing instructions">;
104
Evan Cheng62c7b5b2010-12-05 22:04:16 +0000[diff] [blame]105// Some processors have FP multiply-accumulate instructions that don't
106// play nicely with other VFP / NEON instructions, and it's generally better
Jim Grosbacha43386b2010-03-25 23:11:16 +0000[diff] [blame]107// to just not use them.
Evan Cheng62c7b5b2010-12-05 22:04:16 +0000[diff] [blame]108def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
109 "Disable VFP / NEON MAC instructions">;
Evan Cheng38bf5ad2011-03-31 19:38:48 +0000[diff] [blame]110
111// Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
112def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
113 "HasVMLxForwarding", "true",
114 "Has multiplier accumulator forwarding">;
115
Jim Grosbach71fcb4f2010-03-25 23:47:34 +0000[diff] [blame]116// Some processors benefit from using NEON instructions for scalar
117// single-precision FP operations.
Jim Grosbach62800a92010-08-17 18:39:16 +0000[diff] [blame]118def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
119 "true",
120 "Use NEON for single precision FP">;
Jim Grosbach71fcb4f2010-03-25 23:47:34 +0000[diff] [blame]121
Evan Chengce8fb682010-08-09 18:35:19 +0000[diff] [blame]122// Disable 32-bit to 16-bit narrowing for experimentation.
123def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
124 "Prefer 32-bit Thumb instrs">;
Jim Grosbacha43386b2010-03-25 23:11:16 +0000[diff] [blame]125
Bob Wilsona2881ee2011-04-19 18:11:49 +0000[diff] [blame]126/// Some instructions update CPSR partially, which can add false dependency for
127/// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
128/// mapped to a separate physical register. Avoid partial CPSR update for these
129/// processors.
130def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
131 "AvoidCPSRPartialUpdate", "true",
132 "Avoid CPSR partial update for OOO execution">;
133
Evan Chengddc0cb62012-12-20 19:59:30 +0000[diff] [blame]134def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop",
135 "AvoidMOVsShifterOperand", "true",
136 "Avoid movs instructions with shifter operand">;
137
Evan Cheng65f9d192012-02-28 18:51:51 +0000[diff] [blame]138// Some processors perform return stack prediction. CodeGen should avoid issue
139// "normal" call instructions to callees which do not return.
140def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true",
141 "Has return address stack">;
142
Artyom Skrobov5a6e3942015-10-23 17:19:19 +0000[diff] [blame]143/// DSP extension.
144def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true",
Artyom Skrobovcf296442015-09-24 17:31:16 +0000[diff] [blame]145 "Supports DSP instructions in ARM and/or Thumb2">;
Jim Grosbachcf1464d2011-07-01 21:12:19 +0000[diff] [blame]146
Evan Cheng8740ee32010-11-03 06:34:55 +0000[diff] [blame]147// Multiprocessing extension.
148def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
149 "Supports Multiprocessing extension">;
Evan Cheng40921a42010-08-11 06:51:54 +0000[diff] [blame]150
Bradley Smith25219752013-11-01 13:27:35 +0000[diff] [blame]151// Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8).
152def FeatureVirtualization : SubtargetFeature<"virtualization",
153 "HasVirtualization", "true",
154 "Supports Virtualization extension",
155 [FeatureHWDiv, FeatureHWDivARM]>;
156
Amara Emerson330afb52013-09-23 14:26:15 +0000[diff] [blame]157// M-series ISA
158def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass",
James Molloy21efa7d2011-09-28 14:21:38 +0000[diff] [blame]159 "Is microcontroller profile ('M' series)">;
160
Amara Emerson330afb52013-09-23 14:26:15 +0000[diff] [blame]161// R-series ISA
162def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass",
163 "Is realtime profile ('R' series)">;
164
165// A-series ISA
166def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass",
167 "Is application profile ('A' series)">;
168
Eli Bendersky2e2ce492013-01-30 16:30:19 +0000[diff] [blame]169// Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
170// See ARMInstrInfo.td for details.
171def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
172 "NaCl trap">;
173
Akira Hatanaka2670f4a2015-07-28 22:44:28 +0000[diff] [blame]174def FeatureStrictAlign : SubtargetFeature<"strict-align",
175 "StrictAlign", "true",
176 "Disallow all unaligned memory "
177 "access">;
178
Akira Hatanaka1bc8af72015-07-07 06:54:42 +0000[diff] [blame]179def FeatureLongCalls : SubtargetFeature<"long-calls", "GenLongCalls", "true",
180 "Generate calls via indirect call "
181 "instructions">;
182
Akira Hatanaka28581522015-07-21 01:42:02 +0000[diff] [blame]183def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true",
184 "Reserve R9, making it unavailable as "
185 "GPR">;
186
Akira Hatanaka024d91a2015-07-16 00:58:23 +0000[diff] [blame]187def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true",
188 "Don't use movt/movw pairs for 32-bit "
189 "imms">;
190
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]191
192//===----------------------------------------------------------------------===//
193// ARM ISAa.
194//
195
Evan Cheng8b2bda02011-07-07 03:55:05 +0000[diff] [blame]196def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true",
Evan Chengf2c26162011-07-07 08:26:46 +0000[diff] [blame]197 "Support ARM v4T instructions">;
Evan Cheng8b2bda02011-07-07 03:55:05 +0000[diff] [blame]198def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true",
Evan Chengf2c26162011-07-07 08:26:46 +0000[diff] [blame]199 "Support ARM v5T instructions",
Evan Cheng8b2bda02011-07-07 03:55:05 +0000[diff] [blame]200 [HasV4TOps]>;
201def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true",
Evan Chengf2c26162011-07-07 08:26:46 +0000[diff] [blame]202 "Support ARM v5TE, v5TEj, and v5TExp instructions",
Evan Cheng8b2bda02011-07-07 03:55:05 +0000[diff] [blame]203 [HasV5TOps]>;
204def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true",
Evan Chengf2c26162011-07-07 08:26:46 +0000[diff] [blame]205 "Support ARM v6 instructions",
Evan Cheng8b2bda02011-07-07 03:55:05 +0000[diff] [blame]206 [HasV5TEOps]>;
Tim Northoverf86d1f02013-10-07 11:10:47 +0000[diff] [blame]207def HasV6MOps : SubtargetFeature<"v6m", "HasV6MOps", "true",
208 "Support ARM v6M instructions",
209 [HasV6Ops]>;
Bradley Smithe26f7992016-01-15 10:24:39 +0000[diff] [blame]210def HasV8MBaselineOps : SubtargetFeature<"v8m", "HasV8MBaselineOps", "true",
211 "Support ARM v8M Baseline instructions",
212 [HasV6MOps]>;
Renato Golin12350602015-03-17 11:55:28 +0000[diff] [blame]213def HasV6KOps : SubtargetFeature<"v6k", "HasV6KOps", "true",
214 "Support ARM v6k instructions",
215 [HasV6Ops]>;
Evan Cheng8b2bda02011-07-07 03:55:05 +0000[diff] [blame]216def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
Evan Chengf2c26162011-07-07 08:26:46 +0000[diff] [blame]217 "Support ARM v6t2 instructions",
Bradley Smithe26f7992016-01-15 10:24:39 +0000[diff] [blame]218 [HasV8MBaselineOps, HasV6KOps, FeatureThumb2]>;
Evan Cheng8b2bda02011-07-07 03:55:05 +0000[diff] [blame]219def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
Evan Chengf2c26162011-07-07 08:26:46 +0000[diff] [blame]220 "Support ARM v7 instructions",
Bradley Smith4c21cba2016-01-15 10:23:46 +0000[diff] [blame]221 [HasV6T2Ops, FeaturePerfMon,
222 FeatureV7Clrex]>;
Joey Goulyb3f550e2013-06-26 16:58:26 +0000[diff] [blame]223def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true",
224 "Support ARM v8 instructions",
Bradley Smith4c21cba2016-01-15 10:23:46 +0000[diff] [blame]225 [HasV7Ops, FeatureAcquireRelease]>;
Vladimir Sukharev2afdb322015-04-01 14:54:56 +0000[diff] [blame]226def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
Vladimir Sukharevc632cda2015-03-26 17:05:54 +0000[diff] [blame]227 "Support ARM v8.1a instructions",
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]228 [HasV8Ops]>;
Oliver Stannard8addbf42015-12-01 10:23:06 +0000[diff] [blame]229def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
230 "Support ARM v8.2a instructions",
231 [HasV8_1aOps]>;
Bradley Smithe26f7992016-01-15 10:24:39 +0000[diff] [blame]232def HasV8MMainlineOps : SubtargetFeature<"v8m.main", "HasV8MMainlineOps", "true",
233 "Support ARM v8M Mainline instructions",
234 [HasV7Ops]>;
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]235
Evan Cheng40921a42010-08-11 06:51:54 +0000[diff] [blame]236
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]237//===----------------------------------------------------------------------===//
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]238// ARM Processor subtarget features.
239//
240
241def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
242 "Cortex-A5 ARM processors", []>;
243def ProcA7 : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7",
244 "Cortex-A7 ARM processors", []>;
245def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
246 "Cortex-A8 ARM processors", []>;
247def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
248 "Cortex-A9 ARM processors", []>;
249def ProcA12 : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12",
250 "Cortex-A12 ARM processors", []>;
251def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
252 "Cortex-A15 ARM processors", []>;
253def ProcA17 : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17",
254 "Cortex-A17 ARM processors", []>;
Renato Golin2b6b7ff2016-03-21 17:29:01 +0000[diff] [blame]255def ProcA32 : SubtargetFeature<"a32", "ARMProcFamily", "CortexA32",
256 "Cortex-A32 ARM processors", []>;
Christof Douma8b5dc2c2015-12-02 11:53:44 +0000[diff] [blame]257def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
258 "Cortex-A35 ARM processors", []>;
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]259def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
260 "Cortex-A53 ARM processors", []>;
261def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
262 "Cortex-A57 ARM processors", []>;
263def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
264 "Cortex-A72 ARM processors", []>;
265
266def ProcKrait : SubtargetFeature<"krait", "ARMProcFamily", "Krait",
267 "Qualcomm ARM processors", []>;
268def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
269 "Swift ARM processors", []>;
270
MinSeong Kima7385eb2016-01-05 12:51:59 +0000[diff] [blame]271def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1",
272 "Samsung Exynos-M1 processors", []>;
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]273
274def ProcR4 : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4",
Bradley Smith4c21cba2016-01-15 10:23:46 +0000[diff] [blame]275 "Cortex-R4 ARM processors", []>;
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]276def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
277 "Cortex-R5 ARM processors", []>;
278def ProcR7 : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7",
279 "Cortex-R7 ARM processors", []>;
280
281
282//===----------------------------------------------------------------------===//
283// ARM schedules.
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]284//
285
Evan Cheng4e712de2009-06-19 01:51:50 +0000[diff] [blame]286include "ARMSchedule.td"
287
Richard Bartonc31078c2013-11-22 11:53:16 +0000[diff] [blame]288
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]289//===----------------------------------------------------------------------===//
290// ARM architectures
291//
Bob Wilsone8a549c2012-09-29 21:43:49 +0000[diff] [blame]292
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]293def ARMv2 : Architecture<"armv2", "ARMv2", []>;
Bernard Ogden4400cde2013-10-14 13:16:57 +0000[diff] [blame]294
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]295def ARMv2a : Architecture<"armv2a", "ARMv2a", []>;
Renato Golin16ea8ba2014-10-13 10:22:19 +0000[diff] [blame]296
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]297def ARMv3 : Architecture<"armv3", "ARMv3", []>;
Bernard Ogden4400cde2013-10-14 13:16:57 +0000[diff] [blame]298
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]299def ARMv3m : Architecture<"armv3m", "ARMv3m", []>;
Bernard Ogden53169762013-10-14 13:17:07 +0000[diff] [blame]300
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]301def ARMv4 : Architecture<"armv4", "ARMv4", []>;
Javed Absar5c5e3c52015-04-09 14:07:28 +0000[diff] [blame]302
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]303def ARMv4t : Architecture<"armv4t", "ARMv4t", [HasV4TOps]>;
Evan Chengbf407072010-09-10 01:29:16 +0000[diff] [blame]304
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]305def ARMv5t : Architecture<"armv5t", "ARMv5t", [HasV5TOps]>;
Ana Pazos93a07c22013-12-06 22:48:17 +0000[diff] [blame]306
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]307def ARMv5te : Architecture<"armv5te", "ARMv5te", [HasV5TEOps]>;
Rafael Espindolad89b16d2014-01-02 13:40:08 +0000[diff] [blame]308
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]309def ARMv5tej : Architecture<"armv5tej", "ARMv5tej", [HasV5TEOps]>;
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]310
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]311def ARMv6 : Architecture<"armv6", "ARMv6", [HasV6Ops]>;
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]312
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]313def ARMv6t2 : Architecture<"armv6t2", "ARMv6t2", [HasV6T2Ops,
Artyom Skrobovcf296442015-09-24 17:31:16 +0000[diff] [blame]314 FeatureDSP]>;
Anton Korobeynikovb6f45382009-05-29 23:41:08 +0000[diff] [blame]315
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]316def ARMv6k : Architecture<"armv6k", "ARMv6k", [HasV6KOps]>;
317
Artyom Skrobovf187a652015-11-16 14:05:32 +0000[diff] [blame]318def ARMv6kz : Architecture<"armv6kz", "ARMv6kz", [HasV6KOps,
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]319 FeatureTrustZone]>;
320
321def ARMv6m : Architecture<"armv6-m", "ARMv6m", [HasV6MOps,
322 FeatureNoARM,
323 FeatureDB,
324 FeatureMClass]>;
325
326def ARMv6sm : Architecture<"armv6s-m", "ARMv6sm", [HasV6MOps,
327 FeatureNoARM,
328 FeatureDB,
329 FeatureMClass]>;
330
331def ARMv7a : Architecture<"armv7-a", "ARMv7a", [HasV7Ops,
332 FeatureNEON,
333 FeatureDB,
334 FeatureDSP,
335 FeatureAClass]>;
336
337def ARMv7r : Architecture<"armv7-r", "ARMv7r", [HasV7Ops,
338 FeatureDB,
339 FeatureDSP,
340 FeatureHWDiv,
341 FeatureRClass]>;
342
343def ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops,
344 FeatureThumb2,
345 FeatureNoARM,
346 FeatureDB,
347 FeatureHWDiv,
348 FeatureMClass]>;
349
350def ARMv7em : Architecture<"armv7e-m", "ARMv7em", [HasV7Ops,
351 FeatureThumb2,
352 FeatureNoARM,
353 FeatureDB,
354 FeatureHWDiv,
355 FeatureMClass,
356 FeatureDSP,
357 FeatureT2XtPk]>;
358
359def ARMv8a : Architecture<"armv8-a", "ARMv8a", [HasV8Ops,
360 FeatureAClass,
361 FeatureDB,
362 FeatureFPARMv8,
363 FeatureNEON,
364 FeatureDSP,
365 FeatureTrustZone,
366 FeatureMP,
367 FeatureVirtualization,
368 FeatureCrypto,
369 FeatureCRC]>;
370
371def ARMv81a : Architecture<"armv8.1-a", "ARMv81a", [HasV8_1aOps,
372 FeatureAClass,
373 FeatureDB,
374 FeatureFPARMv8,
375 FeatureNEON,
376 FeatureDSP,
377 FeatureTrustZone,
378 FeatureMP,
379 FeatureVirtualization,
380 FeatureCrypto,
381 FeatureCRC]>;
382
Oliver Stannard46670712015-12-01 10:33:56 +0000[diff] [blame]383def ARMv82a : Architecture<"armv8.2-a", "ARMv82a", [HasV8_2aOps,
384 FeatureAClass,
385 FeatureDB,
386 FeatureFPARMv8,
387 FeatureNEON,
388 FeatureDSP,
389 FeatureTrustZone,
390 FeatureMP,
391 FeatureVirtualization,
392 FeatureCrypto,
393 FeatureCRC]>;
394
Bradley Smithe26f7992016-01-15 10:24:39 +0000[diff] [blame]395def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline",
396 [HasV8MBaselineOps,
397 FeatureNoARM,
398 FeatureDB,
399 FeatureHWDiv,
Bradley Smith433c22e2016-01-15 10:26:51 +0000[diff] [blame]400 FeatureV7Clrex,
Bradley Smithfed3e4a2016-01-25 11:24:47 +0000[diff] [blame]401 Feature8MSecExt,
Bradley Smithe26f7992016-01-15 10:24:39 +0000[diff] [blame]402 FeatureAcquireRelease,
403 FeatureMClass]>;
404
405def ARMv8mMainline : Architecture<"armv8-m.main", "ARMv8mMainline",
406 [HasV8MMainlineOps,
407 FeatureNoARM,
408 FeatureDB,
409 FeatureHWDiv,
Bradley Smithfed3e4a2016-01-25 11:24:47 +0000[diff] [blame]410 Feature8MSecExt,
Bradley Smithe26f7992016-01-15 10:24:39 +0000[diff] [blame]411 FeatureAcquireRelease,
412 FeatureMClass]>;
413
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]414// Aliases
415def IWMMXT : Architecture<"iwmmxt", "ARMv5te", [ARMv5te]>;
416def IWMMXT2 : Architecture<"iwmmxt2", "ARMv5te", [ARMv5te]>;
417def XScale : Architecture<"xscale", "ARMv5te", [ARMv5te]>;
418def ARMv6j : Architecture<"armv6j", "ARMv7a", [ARMv6]>;
419def ARMv7k : Architecture<"armv7k", "ARMv7a", [ARMv7a]>;
420def ARMv7s : Architecture<"armv7s", "ARMv7a", [ARMv7a]>;
421
422
423//===----------------------------------------------------------------------===//
424// ARM processors
425//
426
427// Dummy CPU, used to target architectures
428def : ProcNoItin<"generic", []>;
429
430def : ProcNoItin<"arm8", [ARMv4]>;
431def : ProcNoItin<"arm810", [ARMv4]>;
432def : ProcNoItin<"strongarm", [ARMv4]>;
433def : ProcNoItin<"strongarm110", [ARMv4]>;
434def : ProcNoItin<"strongarm1100", [ARMv4]>;
435def : ProcNoItin<"strongarm1110", [ARMv4]>;
436
437def : ProcNoItin<"arm7tdmi", [ARMv4t]>;
438def : ProcNoItin<"arm7tdmi-s", [ARMv4t]>;
439def : ProcNoItin<"arm710t", [ARMv4t]>;
440def : ProcNoItin<"arm720t", [ARMv4t]>;
441def : ProcNoItin<"arm9", [ARMv4t]>;
442def : ProcNoItin<"arm9tdmi", [ARMv4t]>;
443def : ProcNoItin<"arm920", [ARMv4t]>;
444def : ProcNoItin<"arm920t", [ARMv4t]>;
445def : ProcNoItin<"arm922t", [ARMv4t]>;
446def : ProcNoItin<"arm940t", [ARMv4t]>;
447def : ProcNoItin<"ep9312", [ARMv4t]>;
448
449def : ProcNoItin<"arm10tdmi", [ARMv5t]>;
450def : ProcNoItin<"arm1020t", [ARMv5t]>;
451
452def : ProcNoItin<"arm9e", [ARMv5te]>;
453def : ProcNoItin<"arm926ej-s", [ARMv5te]>;
454def : ProcNoItin<"arm946e-s", [ARMv5te]>;
455def : ProcNoItin<"arm966e-s", [ARMv5te]>;
456def : ProcNoItin<"arm968e-s", [ARMv5te]>;
457def : ProcNoItin<"arm10e", [ARMv5te]>;
458def : ProcNoItin<"arm1020e", [ARMv5te]>;
459def : ProcNoItin<"arm1022e", [ARMv5te]>;
460def : ProcNoItin<"xscale", [ARMv5te]>;
461def : ProcNoItin<"iwmmxt", [ARMv5te]>;
462
463def : Processor<"arm1136j-s", ARMV6Itineraries, [ARMv6]>;
464def : Processor<"arm1136jf-s", ARMV6Itineraries, [ARMv6,
465 FeatureVFP2,
466 FeatureHasSlowFPVMLx]>;
467
468def : Processor<"cortex-m0", ARMV6Itineraries, [ARMv6m]>;
469def : Processor<"cortex-m0plus", ARMV6Itineraries, [ARMv6m]>;
470def : Processor<"cortex-m1", ARMV6Itineraries, [ARMv6m]>;
471def : Processor<"sc000", ARMV6Itineraries, [ARMv6m]>;
472
Artyom Skrobovf187a652015-11-16 14:05:32 +0000[diff] [blame]473def : Processor<"arm1176jz-s", ARMV6Itineraries, [ARMv6kz]>;
474def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ARMv6kz,
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]475 FeatureVFP2,
476 FeatureHasSlowFPVMLx]>;
477
478def : Processor<"mpcorenovfp", ARMV6Itineraries, [ARMv6k]>;
479def : Processor<"mpcore", ARMV6Itineraries, [ARMv6k,
480 FeatureVFP2,
481 FeatureHasSlowFPVMLx]>;
482
483def : Processor<"arm1156t2-s", ARMV6Itineraries, [ARMv6t2]>;
484def : Processor<"arm1156t2f-s", ARMV6Itineraries, [ARMv6t2,
485 FeatureVFP2,
486 FeatureHasSlowFPVMLx]>;
487
Quentin Colombet13cd5212012-11-29 19:48:01 +0000[diff] [blame]488// FIXME: A5 has currently the same Schedule model as A8
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]489def : ProcessorModel<"cortex-a5", CortexA8Model, [ARMv7a, ProcA5,
490 FeatureHasRAS,
491 FeatureTrustZone,
492 FeatureSlowFPBrcc,
493 FeatureHasSlowFPVMLx,
494 FeatureVMLxForwarding,
495 FeatureT2XtPk,
496 FeatureMP,
497 FeatureVFP4]>;
498
499def : ProcessorModel<"cortex-a7", CortexA8Model, [ARMv7a, ProcA7,
500 FeatureHasRAS,
501 FeatureTrustZone,
502 FeatureSlowFPBrcc,
503 FeatureHasSlowFPVMLx,
504 FeatureVMLxForwarding,
505 FeatureT2XtPk,
506 FeatureMP,
507 FeatureVFP4,
508 FeatureHWDiv,
509 FeatureHWDivARM,
510 FeatureVirtualization]>;
511
512def : ProcessorModel<"cortex-a8", CortexA8Model, [ARMv7a, ProcA8,
513 FeatureHasRAS,
514 FeatureTrustZone,
515 FeatureSlowFPBrcc,
516 FeatureHasSlowFPVMLx,
517 FeatureVMLxForwarding,
518 FeatureT2XtPk]>;
519
520def : ProcessorModel<"cortex-a9", CortexA9Model, [ARMv7a, ProcA9,
521 FeatureHasRAS,
522 FeatureTrustZone,
523 FeatureVMLxForwarding,
524 FeatureT2XtPk,
525 FeatureFP16,
526 FeatureAvoidPartialCPSR,
527 FeatureMP]>;
Richard Bartonc31078c2013-11-22 11:53:16 +0000[diff] [blame]528
529// FIXME: A12 has currently the same Schedule model as A9
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]530def : ProcessorModel<"cortex-a12", CortexA9Model, [ARMv7a, ProcA12,
531 FeatureHasRAS,
532 FeatureTrustZone,
533 FeatureVMLxForwarding,
534 FeatureT2XtPk,
535 FeatureVFP4,
536 FeatureHWDiv,
537 FeatureHWDivARM,
538 FeatureAvoidPartialCPSR,
539 FeatureVirtualization,
540 FeatureMP]>;
Richard Bartonc31078c2013-11-22 11:53:16 +0000[diff] [blame]541
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]542// FIXME: A15 has currently the same Schedule model as A9.
543def : ProcessorModel<"cortex-a15", CortexA9Model, [ARMv7a, ProcA15,
544 FeatureHasRAS,
545 FeatureTrustZone,
546 FeatureT2XtPk,
547 FeatureVFP4,
548 FeatureMP,
549 FeatureHWDiv,
550 FeatureHWDivARM,
551 FeatureAvoidPartialCPSR,
552 FeatureVirtualization]>;
Richard Bartonc31078c2013-11-22 11:53:16 +0000[diff] [blame]553
Renato Golin16ea8ba2014-10-13 10:22:19 +0000[diff] [blame]554// FIXME: A17 has currently the same Schedule model as A9
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]555def : ProcessorModel<"cortex-a17", CortexA9Model, [ARMv7a, ProcA17,
556 FeatureHasRAS,
557 FeatureTrustZone,
558 FeatureMP,
559 FeatureVMLxForwarding,
560 FeatureT2XtPk,
561 FeatureVFP4,
562 FeatureHWDiv,
563 FeatureHWDivARM,
564 FeatureAvoidPartialCPSR,
565 FeatureVirtualization]>;
Renato Golin16ea8ba2014-10-13 10:22:19 +0000[diff] [blame]566
Tim Northover13510302014-04-01 13:22:02 +0000[diff] [blame]567// FIXME: krait has currently the same Schedule model as A9
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]568// FIXME: krait has currently the same features as A9 plus VFP4 and hardware
569// division features.
570def : ProcessorModel<"krait", CortexA9Model, [ARMv7a, ProcKrait,
571 FeatureHasRAS,
572 FeatureVMLxForwarding,
573 FeatureT2XtPk,
574 FeatureFP16,
575 FeatureAvoidPartialCPSR,
576 FeatureVFP4,
577 FeatureHWDiv,
578 FeatureHWDivARM]>;
579
580def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift,
581 FeatureHasRAS,
582 FeatureNEONForFP,
583 FeatureT2XtPk,
584 FeatureVFP4,
585 FeatureMP,
586 FeatureHWDiv,
587 FeatureHWDivARM,
588 FeatureAvoidPartialCPSR,
589 FeatureAvoidMOVsShOp,
590 FeatureHasSlowFPVMLx]>;
Tim Northover13510302014-04-01 13:22:02 +0000[diff] [blame]591
Javed Absar5c5e3c52015-04-09 14:07:28 +0000[diff] [blame]592// FIXME: R4 has currently the same ProcessorModel as A8.
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]593def : ProcessorModel<"cortex-r4", CortexA8Model, [ARMv7r, ProcR4,
594 FeatureHasRAS,
595 FeatureAvoidPartialCPSR,
596 FeatureT2XtPk]>;
Javed Absar5c5e3c52015-04-09 14:07:28 +0000[diff] [blame]597
598// FIXME: R4F has currently the same ProcessorModel as A8.
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]599def : ProcessorModel<"cortex-r4f", CortexA8Model, [ARMv7r, ProcR4,
600 FeatureHasRAS,
601 FeatureSlowFPBrcc,
602 FeatureHasSlowFPVMLx,
603 FeatureVFP3,
604 FeatureD16,
605 FeatureAvoidPartialCPSR,
606 FeatureT2XtPk]>;
Javed Absar5c5e3c52015-04-09 14:07:28 +0000[diff] [blame]607
Quentin Colombetb1b66e72012-12-21 04:35:05 +0000[diff] [blame]608// FIXME: R5 has currently the same ProcessorModel as A8.
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]609def : ProcessorModel<"cortex-r5", CortexA8Model, [ARMv7r, ProcR5,
610 FeatureHasRAS,
611 FeatureVFP3,
612 FeatureD16,
613 FeatureSlowFPBrcc,
614 FeatureHWDivARM,
615 FeatureHasSlowFPVMLx,
616 FeatureAvoidPartialCPSR,
617 FeatureT2XtPk]>;
Evan Cheng49e02fc2010-08-11 06:30:38 +0000[diff] [blame]618
Bradley Smith26c99222015-02-18 10:33:30 +0000[diff] [blame]619// FIXME: R7 has currently the same ProcessorModel as A8 and is modelled as R5.
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]620def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7,
621 FeatureHasRAS,
622 FeatureVFP3,
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]623 FeatureD16,
Bradley Smithd5a1f472015-12-07 10:54:36 +0000[diff] [blame]624 FeatureFP16,
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]625 FeatureMP,
626 FeatureSlowFPBrcc,
627 FeatureHWDivARM,
628 FeatureHasSlowFPVMLx,
629 FeatureAvoidPartialCPSR,
630 FeatureT2XtPk]>;
Bradley Smith26c99222015-02-18 10:33:30 +0000[diff] [blame]631
Alexandros Lamprineas84316422016-03-10 17:38:41 +0000[diff] [blame]632def : ProcessorModel<"cortex-r8", CortexA8Model, [ARMv7r,
633 FeatureHasRAS,
634 FeatureVFP3,
635 FeatureD16,
636 FeatureFP16,
637 FeatureMP,
638 FeatureSlowFPBrcc,
639 FeatureHWDivARM,
640 FeatureHasSlowFPVMLx,
641 FeatureAvoidPartialCPSR,
642 FeatureT2XtPk]>;
643
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]644def : ProcNoItin<"cortex-m3", [ARMv7m]>;
645def : ProcNoItin<"sc300", [ARMv7m]>;
Evan Cheng8b2bda02011-07-07 03:55:05 +0000[diff] [blame]646
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]647def : ProcNoItin<"cortex-m4", [ARMv7em,
648 FeatureVFP4,
649 FeatureVFPOnlySP,
650 FeatureD16]>;
651
652def : ProcNoItin<"cortex-m7", [ARMv7em,
653 FeatureFPARMv8,
654 FeatureD16]>;
Oliver Stannard37e4daa2014-10-01 09:02:17 +0000[diff] [blame]655
Renato Golin2b6b7ff2016-03-21 17:29:01 +0000[diff] [blame]656def : ProcNoItin<"cortex-a32", [ARMv8a,
657 FeatureHWDiv,
658 FeatureHWDivARM,
659 FeatureT2XtPk,
660 FeatureCrypto,
661 FeatureCRC]>;
Anton Korobeynikov0b91cc42009-05-23 19:51:43 +0000[diff] [blame]662
Christof Douma8b5dc2c2015-12-02 11:53:44 +0000[diff] [blame]663def : ProcNoItin<"cortex-a35", [ARMv8a, ProcA35,
664 FeatureHWDiv,
665 FeatureHWDivARM,
666 FeatureT2XtPk,
667 FeatureCrypto,
668 FeatureCRC]>;
669
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]670def : ProcNoItin<"cortex-a53", [ARMv8a, ProcA53,
671 FeatureHWDiv,
672 FeatureHWDivARM,
673 FeatureT2XtPk,
674 FeatureCrypto,
675 FeatureCRC]>;
Bob Wilsone8a549c2012-09-29 21:43:49 +0000[diff] [blame]676
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]677def : ProcNoItin<"cortex-a57", [ARMv8a, ProcA57,
678 FeatureHWDiv,
679 FeatureHWDivARM,
680 FeatureT2XtPk,
681 FeatureCrypto,
682 FeatureCRC]>;
683
684def : ProcNoItin<"cortex-a72", [ARMv8a, ProcA72,
685 FeatureHWDiv,
686 FeatureHWDivARM,
687 FeatureT2XtPk,
688 FeatureCrypto,
689 FeatureCRC]>;
Joey Goulyb3f550e2013-06-26 16:58:26 +0000[diff] [blame]690
Tim Northover13510302014-04-01 13:22:02 +0000[diff] [blame]691// Cyclone is very similar to swift
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]692def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift,
693 FeatureHasRAS,
694 FeatureNEONForFP,
695 FeatureT2XtPk,
696 FeatureVFP4,
697 FeatureMP,
698 FeatureHWDiv,
699 FeatureHWDivARM,
700 FeatureAvoidPartialCPSR,
701 FeatureAvoidMOVsShOp,
702 FeatureHasSlowFPVMLx,
703 FeatureCrypto,
704 FeatureZCZeroing]>;
705
MinSeong Kima7385eb2016-01-05 12:51:59 +0000[diff] [blame]706def : ProcNoItin<"exynos-m1", [ARMv8a, ProcExynosM1,
707 FeatureHWDiv,
708 FeatureHWDivARM,
709 FeatureT2XtPk,
710 FeatureCrypto,
711 FeatureCRC]>;
Ana Pazos93a07c22013-12-06 22:48:17 +0000[diff] [blame]712
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]713//===----------------------------------------------------------------------===//
Rafael Espindolaffdc24b2006-05-14 22:18:28 +0000[diff] [blame]714// Register File Description
715//===----------------------------------------------------------------------===//
716
717include "ARMRegisterInfo.td"
718
Bob Wilsona4c22902009-04-17 19:07:39 +0000[diff] [blame]719include "ARMCallingConv.td"
720
Rafael Espindolaffdc24b2006-05-14 22:18:28 +0000[diff] [blame]721//===----------------------------------------------------------------------===//
722// Instruction Descriptions
723//===----------------------------------------------------------------------===//
724
725include "ARMInstrInfo.td"
726
Jakob Stoklund Olesenb93331f2010-04-05 03:10:20 +0000[diff] [blame]727def ARMInstrInfo : InstrInfo;
Rafael Espindolaffdc24b2006-05-14 22:18:28 +0000[diff] [blame]728
729//===----------------------------------------------------------------------===//
730// Declare the target which we are implementing
731//===----------------------------------------------------------------------===//
732
Akira Hatanakaee974752015-03-27 23:41:42 +0000[diff] [blame]733def ARMAsmWriter : AsmWriter {
734 string AsmWriterClassName = "InstPrinter";
735 int PassSubtarget = 1;
736 int Variant = 0;
737 bit isMCAsmWriter = 1;
738}
739
Colin LeMahieu8a0453e2015-11-09 00:31:07 +0000[diff] [blame]740def ARMAsmParserVariant : AsmParserVariant {
741 int Variant = 0;
742 string Name = "ARM";
743 string BreakCharacters = ".";
744}
745
Rafael Espindolaffdc24b2006-05-14 22:18:28 +0000[diff] [blame]746def ARM : Target {
Rafael Espindolaffdc24b2006-05-14 22:18:28 +0000[diff] [blame]747 // Pull in Instruction Info:
748 let InstructionSet = ARMInstrInfo;
Akira Hatanakaee974752015-03-27 23:41:42 +0000[diff] [blame]749 let AssemblyWriters = [ARMAsmWriter];
Colin LeMahieu8a0453e2015-11-09 00:31:07 +0000[diff] [blame]750 let AssemblyParserVariants = [ARMAsmParserVariant];
Rafael Espindolaffdc24b2006-05-14 22:18:28 +0000[diff] [blame]751}