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gerrit-public.fairphone.software / toolchain / llvm-project / e7a35539c5521985d75e89f3329a84fed09584e4 / . / llvm / lib / Target / Mips / MipsSEISelLowering.cpp
blob: 2382ea271661204197ce111c6e3ce4ca55844ba7 [file] [log] [blame]
Akira Hatanaka44ebe002013-03-14 19:09:52 +0000[diff] [blame]1//===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===//
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Subclass of MipsTargetLowering specialized for mips32/64.
11//
12//===----------------------------------------------------------------------===//
13#include "MipsSEISelLowering.h"
Eric Christopher79cc1e32014-09-02 22:28:02 +0000[diff] [blame]14#include "MipsMachineFunction.h"
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]15#include "MipsRegisterInfo.h"
16#include "MipsTargetMachine.h"
Simon Dardis548a53f2017-01-10 16:40:57 +0000[diff] [blame]17#include "llvm/ADT/APInt.h"
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]18#include "llvm/CodeGen/MachineInstrBuilder.h"
19#include "llvm/CodeGen/MachineRegisterInfo.h"
Akira Hatanakaa6bbde52013-04-13 02:13:30 +0000[diff] [blame]20#include "llvm/IR/Intrinsics.h"
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]21#include "llvm/Support/CommandLine.h"
Daniel Sanders62aeab82013-10-30 13:31:27 +0000[diff] [blame]22#include "llvm/Support/Debug.h"
Simon Dardis548a53f2017-01-10 16:40:57 +0000[diff] [blame]23#include "llvm/Support/ErrorHandling.h"
Hans Wennborg3e9b1c12013-10-30 16:10:10 +0000[diff] [blame]24#include "llvm/Support/raw_ostream.h"
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]25#include "llvm/Target/TargetInstrInfo.h"
26
27using namespace llvm;
28
Chandler Carruth84e68b22014-04-22 02:41:26 +0000[diff] [blame]29#define DEBUG_TYPE "mips-isel"
30
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]31static cl::opt<bool>
Simon Dardis57f4ae42016-08-04 09:17:07 +0000[diff] [blame]32UseMipsTailCalls("mips-tail-calls", cl::Hidden,
Simon Dardisd2ed8ab2016-09-27 13:15:54 +0000[diff] [blame]33 cl::desc("MIPS: permit tail calls."), cl::init(false));
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]34
Akira Hatanaka63791212013-09-07 00:52:30 +0000[diff] [blame]35static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
36 cl::desc("Expand double precision loads and "
37 "stores to their single precision "
38 "counterparts"));
39
Eric Christopherb1526602014-09-19 23:30:42 +0000[diff] [blame]40MipsSETargetLowering::MipsSETargetLowering(const MipsTargetMachine &TM,
Eric Christopher8924d272014-07-18 23:25:04 +0000[diff] [blame]41 const MipsSubtarget &STI)
42 : MipsTargetLowering(TM, STI) {
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]43 // Set up the register classes
Akira Hatanaka13e6ccf2013-08-06 23:08:38 +0000[diff] [blame]44 addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]45
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]46 if (Subtarget.isGP64bit())
Akira Hatanaka13e6ccf2013-08-06 23:08:38 +0000[diff] [blame]47 addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]48
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]49 if (Subtarget.hasDSP() || Subtarget.hasMSA()) {
Daniel Sanders36c671e2013-09-27 09:44:59 +0000[diff] [blame]50 // Expand all truncating stores and extending loads.
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]51 for (MVT VT0 : MVT::vector_valuetypes()) {
Ahmed Bougacha2b6917b2015-01-08 00:51:32 +0000[diff] [blame]52 for (MVT VT1 : MVT::vector_valuetypes()) {
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]53 setTruncStoreAction(VT0, VT1, Expand);
Ahmed Bougacha2b6917b2015-01-08 00:51:32 +0000[diff] [blame]54 setLoadExtAction(ISD::SEXTLOAD, VT0, VT1, Expand);
55 setLoadExtAction(ISD::ZEXTLOAD, VT0, VT1, Expand);
56 setLoadExtAction(ISD::EXTLOAD, VT0, VT1, Expand);
57 }
Daniel Sanders36c671e2013-09-27 09:44:59 +0000[diff] [blame]58 }
59 }
60
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]61 if (Subtarget.hasDSP()) {
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]62 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
63
64 for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
Akira Hatanaka654655f2013-08-14 00:53:38 +0000[diff] [blame]65 addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]66
67 // Expand all builtin opcodes.
68 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
69 setOperationAction(Opc, VecTys[i], Expand);
70
Akira Hatanaka2f088222013-04-13 00:55:41 +0000[diff] [blame]71 setOperationAction(ISD::ADD, VecTys[i], Legal);
72 setOperationAction(ISD::SUB, VecTys[i], Legal);
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]73 setOperationAction(ISD::LOAD, VecTys[i], Legal);
74 setOperationAction(ISD::STORE, VecTys[i], Legal);
75 setOperationAction(ISD::BITCAST, VecTys[i], Legal);
76 }
Akira Hatanaka1ebb2a12013-04-19 23:21:32 +0000[diff] [blame]77
78 setTargetDAGCombine(ISD::SHL);
79 setTargetDAGCombine(ISD::SRA);
80 setTargetDAGCombine(ISD::SRL);
Akira Hatanaka68741cc2013-04-30 22:37:26 +0000[diff] [blame]81 setTargetDAGCombine(ISD::SETCC);
82 setTargetDAGCombine(ISD::VSELECT);
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]83 }
84
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]85 if (Subtarget.hasDSPR2())
Akira Hatanaka2f088222013-04-13 00:55:41 +0000[diff] [blame]86 setOperationAction(ISD::MUL, MVT::v2i16, Legal);
87
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]88 if (Subtarget.hasMSA()) {
Daniel Sandersc65f58a2013-09-11 10:15:48 +0000[diff] [blame]89 addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass);
90 addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass);
91 addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);
92 addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);
93 addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass);
94 addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass);
95 addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass);
Daniel Sandersf7456c72013-09-23 13:22:24 +0000[diff] [blame]96
Simon Dardis0e2ee3b2016-11-18 16:17:44 +0000[diff] [blame]97 // f16 is a storage-only type, always promote it to f32.
98 addRegisterClass(MVT::f16, &Mips::MSA128HRegClass);
99 setOperationAction(ISD::SETCC, MVT::f16, Promote);
100 setOperationAction(ISD::BR_CC, MVT::f16, Promote);
101 setOperationAction(ISD::SELECT_CC, MVT::f16, Promote);
102 setOperationAction(ISD::SELECT, MVT::f16, Promote);
103 setOperationAction(ISD::FADD, MVT::f16, Promote);
104 setOperationAction(ISD::FSUB, MVT::f16, Promote);
105 setOperationAction(ISD::FMUL, MVT::f16, Promote);
106 setOperationAction(ISD::FDIV, MVT::f16, Promote);
107 setOperationAction(ISD::FREM, MVT::f16, Promote);
108 setOperationAction(ISD::FMA, MVT::f16, Promote);
109 setOperationAction(ISD::FNEG, MVT::f16, Promote);
110 setOperationAction(ISD::FABS, MVT::f16, Promote);
111 setOperationAction(ISD::FCEIL, MVT::f16, Promote);
112 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Promote);
113 setOperationAction(ISD::FCOS, MVT::f16, Promote);
114 setOperationAction(ISD::FP_EXTEND, MVT::f16, Promote);
115 setOperationAction(ISD::FFLOOR, MVT::f16, Promote);
116 setOperationAction(ISD::FNEARBYINT, MVT::f16, Promote);
117 setOperationAction(ISD::FPOW, MVT::f16, Promote);
118 setOperationAction(ISD::FPOWI, MVT::f16, Promote);
119 setOperationAction(ISD::FRINT, MVT::f16, Promote);
120 setOperationAction(ISD::FSIN, MVT::f16, Promote);
121 setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
122 setOperationAction(ISD::FSQRT, MVT::f16, Promote);
123 setOperationAction(ISD::FEXP, MVT::f16, Promote);
124 setOperationAction(ISD::FEXP2, MVT::f16, Promote);
125 setOperationAction(ISD::FLOG, MVT::f16, Promote);
126 setOperationAction(ISD::FLOG2, MVT::f16, Promote);
127 setOperationAction(ISD::FLOG10, MVT::f16, Promote);
128 setOperationAction(ISD::FROUND, MVT::f16, Promote);
129 setOperationAction(ISD::FTRUNC, MVT::f16, Promote);
130 setOperationAction(ISD::FMINNUM, MVT::f16, Promote);
131 setOperationAction(ISD::FMAXNUM, MVT::f16, Promote);
132 setOperationAction(ISD::FMINNAN, MVT::f16, Promote);
133 setOperationAction(ISD::FMAXNAN, MVT::f16, Promote);
134
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000[diff] [blame]135 setTargetDAGCombine(ISD::AND);
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000[diff] [blame]136 setTargetDAGCombine(ISD::OR);
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000[diff] [blame]137 setTargetDAGCombine(ISD::SRA);
Daniel Sanderse1d24352013-09-24 12:04:44 +0000[diff] [blame]138 setTargetDAGCombine(ISD::VSELECT);
Daniel Sandersf7456c72013-09-23 13:22:24 +0000[diff] [blame]139 setTargetDAGCombine(ISD::XOR);
Jack Carter3a2c2d42013-08-13 20:54:07 +0000[diff] [blame]140 }
141
Eric Christophere8ae3e32015-05-07 23:10:21 +0000[diff] [blame]142 if (!Subtarget.useSoftFloat()) {
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]143 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
144
145 // When dealing with single precision only, use libcalls
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]146 if (!Subtarget.isSingleFloat()) {
147 if (Subtarget.isFP64bit())
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]148 addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
149 else
150 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
151 }
152 }
153
Akira Hatanakabe8612f2013-03-30 01:36:35 +0000[diff] [blame]154 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
155 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom);
156 setOperationAction(ISD::MULHS, MVT::i32, Custom);
157 setOperationAction(ISD::MULHU, MVT::i32, Custom);
158
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]159 if (Subtarget.hasCnMips())
Kai Nacke93fe5e82014-03-20 11:51:58 +0000[diff] [blame]160 setOperationAction(ISD::MUL, MVT::i64, Legal);
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]161 else if (Subtarget.isGP64bit())
Kai Nacke93fe5e82014-03-20 11:51:58 +0000[diff] [blame]162 setOperationAction(ISD::MUL, MVT::i64, Custom);
163
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]164 if (Subtarget.isGP64bit()) {
Vasileios Kalintirisef96a8e2015-01-26 12:33:22 +0000[diff] [blame]165 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Custom);
166 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Custom);
Akira Hatanaka4f1130e2013-04-11 19:29:26 +0000[diff] [blame]167 setOperationAction(ISD::MULHS, MVT::i64, Custom);
168 setOperationAction(ISD::MULHU, MVT::i64, Custom);
Jan Vesely54468a5a2014-10-17 14:45:28 +0000[diff] [blame]169 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
170 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
Akira Hatanaka4f1130e2013-04-11 19:29:26 +0000[diff] [blame]171 }
Akira Hatanakabe8612f2013-03-30 01:36:35 +0000[diff] [blame]172
Akira Hatanakaa6bbde52013-04-13 02:13:30 +0000[diff] [blame]173 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
174 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
175
Akira Hatanakabe8612f2013-03-30 01:36:35 +0000[diff] [blame]176 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
177 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]178 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
179 setOperationAction(ISD::LOAD, MVT::i32, Custom);
180 setOperationAction(ISD::STORE, MVT::i32, Custom);
181
Akira Hatanaka5832fc62013-06-26 18:48:17 +0000[diff] [blame]182 setTargetDAGCombine(ISD::MUL);
Akira Hatanaka9efcd762013-03-30 01:42:24 +0000[diff] [blame]183
Daniel Sandersce09d072013-08-28 12:14:50 +0000[diff] [blame]184 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
Daniel Sanderse6ed5b72013-08-28 12:04:29 +0000[diff] [blame]185 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
186 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
187
Akira Hatanaka63791212013-09-07 00:52:30 +0000[diff] [blame]188 if (NoDPLoadStore) {
189 setOperationAction(ISD::LOAD, MVT::f64, Custom);
190 setOperationAction(ISD::STORE, MVT::f64, Custom);
191 }
192
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]193 if (Subtarget.hasMips32r6()) {
Daniel Sanders308181e2014-06-12 10:44:10 +0000[diff] [blame]194 // MIPS32r6 replaces the accumulator-based multiplies with a three register
195 // instruction
Daniel Sanders826f8b32014-06-12 10:54:16 +0000[diff] [blame]196 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
197 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
Daniel Sanders308181e2014-06-12 10:44:10 +0000[diff] [blame]198 setOperationAction(ISD::MUL, MVT::i32, Legal);
199 setOperationAction(ISD::MULHS, MVT::i32, Legal);
200 setOperationAction(ISD::MULHU, MVT::i32, Legal);
201
202 // MIPS32r6 replaces the accumulator-based division/remainder with separate
203 // three register division and remainder instructions.
204 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
205 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
206 setOperationAction(ISD::SDIV, MVT::i32, Legal);
207 setOperationAction(ISD::UDIV, MVT::i32, Legal);
208 setOperationAction(ISD::SREM, MVT::i32, Legal);
209 setOperationAction(ISD::UREM, MVT::i32, Legal);
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]210
211 // MIPS32r6 replaces conditional moves with an equivalent that removes the
212 // need for three GPR read ports.
213 setOperationAction(ISD::SETCC, MVT::i32, Legal);
214 setOperationAction(ISD::SELECT, MVT::i32, Legal);
215 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
216
217 setOperationAction(ISD::SETCC, MVT::f32, Legal);
218 setOperationAction(ISD::SELECT, MVT::f32, Legal);
219 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
220
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]221 assert(Subtarget.isFP64bit() && "FR=1 is required for MIPS32r6");
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]222 setOperationAction(ISD::SETCC, MVT::f64, Legal);
223 setOperationAction(ISD::SELECT, MVT::f64, Legal);
224 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
225
Daniel Sanders3d3ea532014-06-12 15:00:17 +0000[diff] [blame]226 setOperationAction(ISD::BRCOND, MVT::Other, Legal);
227
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]228 // Floating point > and >= are supported via < and <=
229 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
230 setCondCodeAction(ISD::SETOGT, MVT::f32, Expand);
231 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand);
232 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
233
234 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
235 setCondCodeAction(ISD::SETOGT, MVT::f64, Expand);
236 setCondCodeAction(ISD::SETUGE, MVT::f64, Expand);
237 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
Daniel Sanders308181e2014-06-12 10:44:10 +0000[diff] [blame]238 }
239
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]240 if (Subtarget.hasMips64r6()) {
Daniel Sanders308181e2014-06-12 10:44:10 +0000[diff] [blame]241 // MIPS64r6 replaces the accumulator-based multiplies with a three register
242 // instruction
Vasileios Kalintirisef96a8e2015-01-26 12:33:22 +0000[diff] [blame]243 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
244 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
Daniel Sanders308181e2014-06-12 10:44:10 +0000[diff] [blame]245 setOperationAction(ISD::MUL, MVT::i64, Legal);
246 setOperationAction(ISD::MULHS, MVT::i64, Legal);
247 setOperationAction(ISD::MULHU, MVT::i64, Legal);
248
249 // MIPS32r6 replaces the accumulator-based division/remainder with separate
250 // three register division and remainder instructions.
251 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
252 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
253 setOperationAction(ISD::SDIV, MVT::i64, Legal);
254 setOperationAction(ISD::UDIV, MVT::i64, Legal);
255 setOperationAction(ISD::SREM, MVT::i64, Legal);
256 setOperationAction(ISD::UREM, MVT::i64, Legal);
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame]257
258 // MIPS64r6 replaces conditional moves with an equivalent that removes the
259 // need for three GPR read ports.
260 setOperationAction(ISD::SETCC, MVT::i64, Legal);
261 setOperationAction(ISD::SELECT, MVT::i64, Legal);
262 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
Daniel Sanders308181e2014-06-12 10:44:10 +0000[diff] [blame]263 }
264
Eric Christopher23a3a7c2015-02-26 00:00:24 +0000[diff] [blame]265 computeRegisterProperties(Subtarget.getRegisterInfo());
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]266}
267
268const MipsTargetLowering *
Eric Christopherb1526602014-09-19 23:30:42 +0000[diff] [blame]269llvm::createMipsSETargetLowering(const MipsTargetMachine &TM,
Eric Christopher8924d272014-07-18 23:25:04 +0000[diff] [blame]270 const MipsSubtarget &STI) {
271 return new MipsSETargetLowering(TM, STI);
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]272}
273
Eric Christopherbf33a3c2014-07-02 23:18:40 +0000[diff] [blame]274const TargetRegisterClass *
275MipsSETargetLowering::getRepRegClassFor(MVT VT) const {
276 if (VT == MVT::Untyped)
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]277 return Subtarget.hasDSP() ? &Mips::ACC64DSPRegClass : &Mips::ACC64RegClass;
Eric Christopherbf33a3c2014-07-02 23:18:40 +0000[diff] [blame]278
279 return TargetLowering::getRepRegClassFor(VT);
280}
281
Daniel Sanders7a289d02013-09-23 12:02:46 +0000[diff] [blame]282// Enable MSA support for the given integer type and Register class.
Daniel Sanders3c9a0ad2013-08-23 10:10:13 +0000[diff] [blame]283void MipsSETargetLowering::
Daniel Sandersc65f58a2013-09-11 10:15:48 +0000[diff] [blame]284addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
285 addRegisterClass(Ty, RC);
286
287 // Expand all builtin opcodes.
288 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
289 setOperationAction(Opc, Ty, Expand);
290
291 setOperationAction(ISD::BITCAST, Ty, Legal);
292 setOperationAction(ISD::LOAD, Ty, Legal);
293 setOperationAction(ISD::STORE, Ty, Legal);
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000[diff] [blame]294 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Custom);
295 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
Daniel Sanders7a289d02013-09-23 12:02:46 +0000[diff] [blame]296 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
Daniel Sandersc65f58a2013-09-11 10:15:48 +0000[diff] [blame]297
Daniel Sandersfa5ab1c2013-09-11 10:28:16 +0000[diff] [blame]298 setOperationAction(ISD::ADD, Ty, Legal);
Daniel Sanders8ca81e42013-09-23 12:57:42 +0000[diff] [blame]299 setOperationAction(ISD::AND, Ty, Legal);
Daniel Sandersfbcb5822013-09-11 11:58:30 +0000[diff] [blame]300 setOperationAction(ISD::CTLZ, Ty, Legal);
Daniel Sanders766cb692013-09-23 13:40:21 +0000[diff] [blame]301 setOperationAction(ISD::CTPOP, Ty, Legal);
Daniel Sandersfbcb5822013-09-11 11:58:30 +0000[diff] [blame]302 setOperationAction(ISD::MUL, Ty, Legal);
Daniel Sanders8ca81e42013-09-23 12:57:42 +0000[diff] [blame]303 setOperationAction(ISD::OR, Ty, Legal);
Daniel Sanders607952b2013-09-11 10:38:58 +0000[diff] [blame]304 setOperationAction(ISD::SDIV, Ty, Legal);
Daniel Sanders0210dd42013-10-01 10:22:35 +0000[diff] [blame]305 setOperationAction(ISD::SREM, Ty, Legal);
Daniel Sandersfbcb5822013-09-11 11:58:30 +0000[diff] [blame]306 setOperationAction(ISD::SHL, Ty, Legal);
307 setOperationAction(ISD::SRA, Ty, Legal);
308 setOperationAction(ISD::SRL, Ty, Legal);
309 setOperationAction(ISD::SUB, Ty, Legal);
Daniel Sanders607952b2013-09-11 10:38:58 +0000[diff] [blame]310 setOperationAction(ISD::UDIV, Ty, Legal);
Daniel Sanders0210dd42013-10-01 10:22:35 +0000[diff] [blame]311 setOperationAction(ISD::UREM, Ty, Legal);
Daniel Sanderse5087042013-09-24 14:02:15 +0000[diff] [blame]312 setOperationAction(ISD::VECTOR_SHUFFLE, Ty, Custom);
Daniel Sanderse1d24352013-09-24 12:04:44 +0000[diff] [blame]313 setOperationAction(ISD::VSELECT, Ty, Legal);
Daniel Sanders8ca81e42013-09-23 12:57:42 +0000[diff] [blame]314 setOperationAction(ISD::XOR, Ty, Legal);
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]315
Daniel Sanders015972b2013-10-11 10:00:06 +0000[diff] [blame]316 if (Ty == MVT::v4i32 || Ty == MVT::v2i64) {
317 setOperationAction(ISD::FP_TO_SINT, Ty, Legal);
318 setOperationAction(ISD::FP_TO_UINT, Ty, Legal);
319 setOperationAction(ISD::SINT_TO_FP, Ty, Legal);
320 setOperationAction(ISD::UINT_TO_FP, Ty, Legal);
321 }
322
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]323 setOperationAction(ISD::SETCC, Ty, Legal);
324 setCondCodeAction(ISD::SETNE, Ty, Expand);
325 setCondCodeAction(ISD::SETGE, Ty, Expand);
326 setCondCodeAction(ISD::SETGT, Ty, Expand);
327 setCondCodeAction(ISD::SETUGE, Ty, Expand);
328 setCondCodeAction(ISD::SETUGT, Ty, Expand);
Daniel Sandersc65f58a2013-09-11 10:15:48 +0000[diff] [blame]329}
330
Daniel Sanders7a289d02013-09-23 12:02:46 +0000[diff] [blame]331// Enable MSA support for the given floating-point type and Register class.
Daniel Sandersc65f58a2013-09-11 10:15:48 +0000[diff] [blame]332void MipsSETargetLowering::
333addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
Daniel Sanders3c9a0ad2013-08-23 10:10:13 +0000[diff] [blame]334 addRegisterClass(Ty, RC);
Jack Carterbabdcc82013-08-15 12:24:57 +0000[diff] [blame]335
336 // Expand all builtin opcodes.
337 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
338 setOperationAction(Opc, Ty, Expand);
339
340 setOperationAction(ISD::LOAD, Ty, Legal);
341 setOperationAction(ISD::STORE, Ty, Legal);
342 setOperationAction(ISD::BITCAST, Ty, Legal);
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000[diff] [blame]343 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Legal);
Daniel Sandersa5150702013-09-27 12:31:32 +0000[diff] [blame]344 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
Daniel Sanders1dfddc72013-10-15 13:14:41 +0000[diff] [blame]345 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
Daniel Sandersf5bd9372013-09-11 10:51:30 +0000[diff] [blame]346
347 if (Ty != MVT::v8f16) {
Daniel Sanders4f3ff1b2013-09-24 13:02:08 +0000[diff] [blame]348 setOperationAction(ISD::FABS, Ty, Legal);
Daniel Sandersf5bd9372013-09-11 10:51:30 +0000[diff] [blame]349 setOperationAction(ISD::FADD, Ty, Legal);
350 setOperationAction(ISD::FDIV, Ty, Legal);
Daniel Sandersa9521602013-10-23 10:36:52 +0000[diff] [blame]351 setOperationAction(ISD::FEXP2, Ty, Legal);
Daniel Sandersf5bd9372013-09-11 10:51:30 +0000[diff] [blame]352 setOperationAction(ISD::FLOG2, Ty, Legal);
Daniel Sandersd7103f32013-10-11 10:14:25 +0000[diff] [blame]353 setOperationAction(ISD::FMA, Ty, Legal);
Daniel Sandersf5bd9372013-09-11 10:51:30 +0000[diff] [blame]354 setOperationAction(ISD::FMUL, Ty, Legal);
355 setOperationAction(ISD::FRINT, Ty, Legal);
356 setOperationAction(ISD::FSQRT, Ty, Legal);
357 setOperationAction(ISD::FSUB, Ty, Legal);
Daniel Sanderse1d24352013-09-24 12:04:44 +0000[diff] [blame]358 setOperationAction(ISD::VSELECT, Ty, Legal);
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]359
360 setOperationAction(ISD::SETCC, Ty, Legal);
361 setCondCodeAction(ISD::SETOGE, Ty, Expand);
362 setCondCodeAction(ISD::SETOGT, Ty, Expand);
363 setCondCodeAction(ISD::SETUGE, Ty, Expand);
364 setCondCodeAction(ISD::SETUGT, Ty, Expand);
365 setCondCodeAction(ISD::SETGE, Ty, Expand);
366 setCondCodeAction(ISD::SETGT, Ty, Expand);
Daniel Sandersf5bd9372013-09-11 10:51:30 +0000[diff] [blame]367 }
Jack Carterbabdcc82013-08-15 12:24:57 +0000[diff] [blame]368}
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]369
370bool
Matt Arsenault6f2a5262014-07-27 17:46:40 +0000[diff] [blame]371MipsSETargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
372 unsigned,
373 unsigned,
374 bool *Fast) const {
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]375 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
376
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]377 if (Subtarget.systemSupportsUnalignedAccess()) {
Daniel Sandersac272632014-05-23 13:18:02 +0000[diff] [blame]378 // MIPS32r6/MIPS64r6 is required to support unaligned access. It's
379 // implementation defined whether this is handled by hardware, software, or
380 // a hybrid of the two but it's expected that most implementations will
381 // handle the majority of cases in hardware.
382 if (Fast)
383 *Fast = true;
384 return true;
385 }
386
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]387 switch (SVT) {
388 case MVT::i64:
389 case MVT::i32:
390 if (Fast)
391 *Fast = true;
392 return true;
393 default:
394 return false;
395 }
396}
397
Akira Hatanakabe8612f2013-03-30 01:36:35 +0000[diff] [blame]398SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
399 SelectionDAG &DAG) const {
400 switch(Op.getOpcode()) {
Akira Hatanaka63791212013-09-07 00:52:30 +0000[diff] [blame]401 case ISD::LOAD: return lowerLOAD(Op, DAG);
402 case ISD::STORE: return lowerSTORE(Op, DAG);
Akira Hatanakabe8612f2013-03-30 01:36:35 +0000[diff] [blame]403 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
404 case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
405 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
406 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
407 case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
408 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
Akira Hatanakad8fb0322013-04-22 20:13:37 +0000[diff] [blame]409 case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
410 DAG);
Akira Hatanakaa6bbde52013-04-13 02:13:30 +0000[diff] [blame]411 case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
412 case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG);
Daniel Sanderse6ed5b72013-08-28 12:04:29 +0000[diff] [blame]413 case ISD::INTRINSIC_VOID: return lowerINTRINSIC_VOID(Op, DAG);
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000[diff] [blame]414 case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG);
Daniel Sanders7a289d02013-09-23 12:02:46 +0000[diff] [blame]415 case ISD::BUILD_VECTOR: return lowerBUILD_VECTOR(Op, DAG);
Daniel Sanderse5087042013-09-24 14:02:15 +0000[diff] [blame]416 case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG);
Akira Hatanakabe8612f2013-03-30 01:36:35 +0000[diff] [blame]417 }
418
419 return MipsTargetLowering::LowerOperation(Op, DAG);
420}
421
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000[diff] [blame]422// Fold zero extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT
423//
424// Performs the following transformations:
425// - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to zero extension if its
426// sign/zero-extension is completely overwritten by the new one performed by
427// the ISD::AND.
428// - Removes redundant zero extensions performed by an ISD::AND.
429static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
430 TargetLowering::DAGCombinerInfo &DCI,
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]431 const MipsSubtarget &Subtarget) {
432 if (!Subtarget.hasMSA())
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000[diff] [blame]433 return SDValue();
434
435 SDValue Op0 = N->getOperand(0);
436 SDValue Op1 = N->getOperand(1);
437 unsigned Op0Opcode = Op0->getOpcode();
438
439 // (and (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d)
440 // where $d + 1 == 2^n and n == 32
441 // or $d + 1 == 2^n and n <= 32 and ZExt
442 // -> (MipsVExtractZExt $a, $b, $c)
443 if (Op0Opcode == MipsISD::VEXTRACT_SEXT_ELT ||
444 Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT) {
445 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(Op1);
446
447 if (!Mask)
448 return SDValue();
449
450 int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2();
451
452 if (Log2IfPositive <= 0)
453 return SDValue(); // Mask+1 is not a power of 2
454
455 SDValue Op0Op2 = Op0->getOperand(2);
456 EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT();
457 unsigned ExtendTySize = ExtendTy.getSizeInBits();
458 unsigned Log2 = Log2IfPositive;
459
460 if ((Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT && Log2 >= ExtendTySize) ||
461 Log2 == ExtendTySize) {
462 SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 };
Chandler Carruth356665a2014-08-01 22:09:43 +0000[diff] [blame]463 return DAG.getNode(MipsISD::VEXTRACT_ZEXT_ELT, SDLoc(Op0),
464 Op0->getVTList(),
465 makeArrayRef(Ops, Op0->getNumOperands()));
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000[diff] [blame]466 }
467 }
468
469 return SDValue();
470}
471
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000[diff] [blame]472// Determine if the specified node is a constant vector splat.
473//
474// Returns true and sets Imm if:
475// * N is a ISD::BUILD_VECTOR representing a constant splat
476//
477// This function is quite similar to MipsSEDAGToDAGISel::selectVSplat. The
478// differences are that it assumes the MSA has already been checked and the
479// arbitrary requirement for a maximum of 32-bit integers isn't applied (and
480// must not be in order for binsri.d to be selectable).
481static bool isVSplat(SDValue N, APInt &Imm, bool IsLittleEndian) {
482 BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N.getNode());
483
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]484 if (!Node)
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000[diff] [blame]485 return false;
486
487 APInt SplatValue, SplatUndef;
488 unsigned SplatBitSize;
489 bool HasAnyUndefs;
490
491 if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
492 8, !IsLittleEndian))
493 return false;
494
495 Imm = SplatValue;
496
497 return true;
498}
499
Daniel Sandersab94b532013-10-30 15:20:38 +0000[diff] [blame]500// Test whether the given node is an all-ones build_vector.
501static bool isVectorAllOnes(SDValue N) {
502 // Look through bitcasts. Endianness doesn't matter because we are looking
503 // for an all-ones value.
504 if (N->getOpcode() == ISD::BITCAST)
505 N = N->getOperand(0);
506
507 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N);
508
509 if (!BVN)
510 return false;
511
512 APInt SplatValue, SplatUndef;
513 unsigned SplatBitSize;
514 bool HasAnyUndefs;
515
516 // Endianness doesn't matter in this context because we are looking for
517 // an all-ones value.
518 if (BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs))
519 return SplatValue.isAllOnesValue();
520
521 return false;
522}
523
524// Test whether N is the bitwise inverse of OfNode.
525static bool isBitwiseInverse(SDValue N, SDValue OfNode) {
526 if (N->getOpcode() != ISD::XOR)
527 return false;
528
529 if (isVectorAllOnes(N->getOperand(0)))
530 return N->getOperand(1) == OfNode;
531
532 if (isVectorAllOnes(N->getOperand(1)))
533 return N->getOperand(0) == OfNode;
534
535 return false;
536}
537
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000[diff] [blame]538// Perform combines where ISD::OR is the root node.
539//
540// Performs the following transformations:
541// - (or (and $a, $mask), (and $b, $inv_mask)) => (vselect $mask, $a, $b)
542// where $inv_mask is the bitwise inverse of $mask and the 'or' has a 128-bit
543// vector type.
544static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
545 TargetLowering::DAGCombinerInfo &DCI,
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]546 const MipsSubtarget &Subtarget) {
547 if (!Subtarget.hasMSA())
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000[diff] [blame]548 return SDValue();
549
550 EVT Ty = N->getValueType(0);
551
552 if (!Ty.is128BitVector())
553 return SDValue();
554
555 SDValue Op0 = N->getOperand(0);
556 SDValue Op1 = N->getOperand(1);
557
558 if (Op0->getOpcode() == ISD::AND && Op1->getOpcode() == ISD::AND) {
559 SDValue Op0Op0 = Op0->getOperand(0);
560 SDValue Op0Op1 = Op0->getOperand(1);
561 SDValue Op1Op0 = Op1->getOperand(0);
562 SDValue Op1Op1 = Op1->getOperand(1);
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]563 bool IsLittleEndian = !Subtarget.isLittle();
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000[diff] [blame]564
565 SDValue IfSet, IfClr, Cond;
Daniel Sandersab94b532013-10-30 15:20:38 +0000[diff] [blame]566 bool IsConstantMask = false;
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000[diff] [blame]567 APInt Mask, InvMask;
568
569 // If Op0Op0 is an appropriate mask, try to find it's inverse in either
570 // Op1Op0, or Op1Op1. Keep track of the Cond, IfSet, and IfClr nodes, while
571 // looking.
572 // IfClr will be set if we find a valid match.
573 if (isVSplat(Op0Op0, Mask, IsLittleEndian)) {
574 Cond = Op0Op0;
575 IfSet = Op0Op1;
576
Daniel Sandersc8c50fb2013-11-21 16:11:31 +0000[diff] [blame]577 if (isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
578 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000[diff] [blame]579 IfClr = Op1Op1;
Daniel Sandersc8c50fb2013-11-21 16:11:31 +0000[diff] [blame]580 else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
581 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000[diff] [blame]582 IfClr = Op1Op0;
Daniel Sandersab94b532013-10-30 15:20:38 +0000[diff] [blame]583
584 IsConstantMask = true;
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000[diff] [blame]585 }
586
587 // If IfClr is not yet set, and Op0Op1 is an appropriate mask, try the same
588 // thing again using this mask.
589 // IfClr will be set if we find a valid match.
590 if (!IfClr.getNode() && isVSplat(Op0Op1, Mask, IsLittleEndian)) {
591 Cond = Op0Op1;
592 IfSet = Op0Op0;
593
Daniel Sandersc8c50fb2013-11-21 16:11:31 +0000[diff] [blame]594 if (isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
595 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000[diff] [blame]596 IfClr = Op1Op1;
Daniel Sandersc8c50fb2013-11-21 16:11:31 +0000[diff] [blame]597 else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
598 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000[diff] [blame]599 IfClr = Op1Op0;
Daniel Sandersab94b532013-10-30 15:20:38 +0000[diff] [blame]600
601 IsConstantMask = true;
602 }
603
604 // If IfClr is not yet set, try looking for a non-constant match.
605 // IfClr will be set if we find a valid match amongst the eight
606 // possibilities.
607 if (!IfClr.getNode()) {
608 if (isBitwiseInverse(Op0Op0, Op1Op0)) {
609 Cond = Op1Op0;
610 IfSet = Op1Op1;
611 IfClr = Op0Op1;
612 } else if (isBitwiseInverse(Op0Op1, Op1Op0)) {
613 Cond = Op1Op0;
614 IfSet = Op1Op1;
615 IfClr = Op0Op0;
616 } else if (isBitwiseInverse(Op0Op0, Op1Op1)) {
617 Cond = Op1Op1;
618 IfSet = Op1Op0;
619 IfClr = Op0Op1;
620 } else if (isBitwiseInverse(Op0Op1, Op1Op1)) {
621 Cond = Op1Op1;
622 IfSet = Op1Op0;
623 IfClr = Op0Op0;
624 } else if (isBitwiseInverse(Op1Op0, Op0Op0)) {
625 Cond = Op0Op0;
626 IfSet = Op0Op1;
627 IfClr = Op1Op1;
628 } else if (isBitwiseInverse(Op1Op1, Op0Op0)) {
629 Cond = Op0Op0;
630 IfSet = Op0Op1;
631 IfClr = Op1Op0;
632 } else if (isBitwiseInverse(Op1Op0, Op0Op1)) {
633 Cond = Op0Op1;
634 IfSet = Op0Op0;
635 IfClr = Op1Op1;
636 } else if (isBitwiseInverse(Op1Op1, Op0Op1)) {
637 Cond = Op0Op1;
638 IfSet = Op0Op0;
639 IfClr = Op1Op0;
640 }
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000[diff] [blame]641 }
642
643 // At this point, IfClr will be set if we have a valid match.
644 if (!IfClr.getNode())
645 return SDValue();
646
647 assert(Cond.getNode() && IfSet.getNode());
648
649 // Fold degenerate cases.
Daniel Sandersab94b532013-10-30 15:20:38 +0000[diff] [blame]650 if (IsConstantMask) {
651 if (Mask.isAllOnesValue())
652 return IfSet;
653 else if (Mask == 0)
654 return IfClr;
655 }
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000[diff] [blame]656
657 // Transform the DAG into an equivalent VSELECT.
Daniel Sandersdf2215452014-03-12 11:54:00 +0000[diff] [blame]658 return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfSet, IfClr);
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000[diff] [blame]659 }
660
661 return SDValue();
662}
663
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]664static SDValue genConstMult(SDValue X, uint64_t C, const SDLoc &DL, EVT VT,
Akira Hatanaka5832fc62013-06-26 18:48:17 +0000[diff] [blame]665 EVT ShiftTy, SelectionDAG &DAG) {
666 // Clear the upper (64 - VT.sizeInBits) bits.
667 C &= ((uint64_t)-1) >> (64 - VT.getSizeInBits());
668
669 // Return 0.
670 if (C == 0)
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]671 return DAG.getConstant(0, DL, VT);
Akira Hatanaka5832fc62013-06-26 18:48:17 +0000[diff] [blame]672
673 // Return x.
674 if (C == 1)
675 return X;
676
677 // If c is power of 2, return (shl x, log2(c)).
678 if (isPowerOf2_64(C))
679 return DAG.getNode(ISD::SHL, DL, VT, X,
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]680 DAG.getConstant(Log2_64(C), DL, ShiftTy));
Akira Hatanaka5832fc62013-06-26 18:48:17 +0000[diff] [blame]681
682 unsigned Log2Ceil = Log2_64_Ceil(C);
683 uint64_t Floor = 1LL << Log2_64(C);
684 uint64_t Ceil = Log2Ceil == 64 ? 0LL : 1LL << Log2Ceil;
685
686 // If |c - floor_c| <= |c - ceil_c|,
687 // where floor_c = pow(2, floor(log2(c))) and ceil_c = pow(2, ceil(log2(c))),
688 // return (add constMult(x, floor_c), constMult(x, c - floor_c)).
689 if (C - Floor <= Ceil - C) {
690 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG);
691 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG);
692 return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);
693 }
694
695 // If |c - floor_c| > |c - ceil_c|,
696 // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)).
697 SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG);
698 SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG);
699 return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
700}
701
702static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG,
703 const TargetLowering::DAGCombinerInfo &DCI,
704 const MipsSETargetLowering *TL) {
705 EVT VT = N->getValueType(0);
706
707 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
708 if (!VT.isVector())
Mehdi Amini9639d652015-07-09 02:09:20 +0000[diff] [blame]709 return genConstMult(N->getOperand(0), C->getZExtValue(), SDLoc(N), VT,
Mehdi Aminieaabc512015-07-09 15:12:23 +0000[diff] [blame]710 TL->getScalarShiftAmountTy(DAG.getDataLayout(), VT),
711 DAG);
Akira Hatanaka5832fc62013-06-26 18:48:17 +0000[diff] [blame]712
713 return SDValue(N, 0);
714}
715
Akira Hatanaka1ebb2a12013-04-19 23:21:32 +0000[diff] [blame]716static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
717 SelectionDAG &DAG,
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]718 const MipsSubtarget &Subtarget) {
Akira Hatanaka1ebb2a12013-04-19 23:21:32 +0000[diff] [blame]719 // See if this is a vector splat immediate node.
720 APInt SplatValue, SplatUndef;
721 unsigned SplatBitSize;
722 bool HasAnyUndefs;
Sanjay Patel1ed771f2016-09-14 16:37:15 +0000[diff] [blame]723 unsigned EltSize = Ty.getScalarSizeInBits();
Akira Hatanaka1ebb2a12013-04-19 23:21:32 +0000[diff] [blame]724 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
725
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]726 if (!Subtarget.hasDSP())
Daniel Sanders6e664bc2013-11-21 11:40:14 +0000[diff] [blame]727 return SDValue();
728
Akira Hatanaka0d6964c2013-04-22 19:58:23 +0000[diff] [blame]729 if (!BV ||
Akira Hatanakad8fb0322013-04-22 20:13:37 +0000[diff] [blame]730 !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]731 EltSize, !Subtarget.isLittle()) ||
Akira Hatanaka0d6964c2013-04-22 19:58:23 +0000[diff] [blame]732 (SplatBitSize != EltSize) ||
Akira Hatanakae9d0b312013-04-23 18:09:42 +0000[diff] [blame]733 (SplatValue.getZExtValue() >= EltSize))
Akira Hatanaka1ebb2a12013-04-19 23:21:32 +0000[diff] [blame]734 return SDValue();
735
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]736 SDLoc DL(N);
737 return DAG.getNode(Opc, DL, Ty, N->getOperand(0),
738 DAG.getConstant(SplatValue.getZExtValue(), DL, MVT::i32));
Akira Hatanaka1ebb2a12013-04-19 23:21:32 +0000[diff] [blame]739}
740
741static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
742 TargetLowering::DAGCombinerInfo &DCI,
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]743 const MipsSubtarget &Subtarget) {
Akira Hatanaka1ebb2a12013-04-19 23:21:32 +0000[diff] [blame]744 EVT Ty = N->getValueType(0);
745
746 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
747 return SDValue();
748
749 return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget);
750}
751
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000[diff] [blame]752// Fold sign-extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT for MSA and fold
753// constant splats into MipsISD::SHRA_DSP for DSPr2.
754//
755// Performs the following transformations:
756// - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to sign extension if its
757// sign/zero-extension is completely overwritten by the new one performed by
758// the ISD::SRA and ISD::SHL nodes.
759// - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL
760// sequence.
761//
762// See performDSPShiftCombine for more information about the transformation
763// used for DSPr2.
Akira Hatanaka1ebb2a12013-04-19 23:21:32 +0000[diff] [blame]764static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
765 TargetLowering::DAGCombinerInfo &DCI,
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]766 const MipsSubtarget &Subtarget) {
Akira Hatanaka1ebb2a12013-04-19 23:21:32 +0000[diff] [blame]767 EVT Ty = N->getValueType(0);
768
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]769 if (Subtarget.hasMSA()) {
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000[diff] [blame]770 SDValue Op0 = N->getOperand(0);
771 SDValue Op1 = N->getOperand(1);
772
773 // (sra (shl (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d), imm:$d)
774 // where $d + sizeof($c) == 32
775 // or $d + sizeof($c) <= 32 and SExt
776 // -> (MipsVExtractSExt $a, $b, $c)
777 if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) {
778 SDValue Op0Op0 = Op0->getOperand(0);
779 ConstantSDNode *ShAmount = dyn_cast<ConstantSDNode>(Op1);
780
781 if (!ShAmount)
782 return SDValue();
783
Daniel Sandersf4f1a872013-09-27 09:25:29 +0000[diff] [blame]784 if (Op0Op0->getOpcode() != MipsISD::VEXTRACT_SEXT_ELT &&
785 Op0Op0->getOpcode() != MipsISD::VEXTRACT_ZEXT_ELT)
786 return SDValue();
787
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000[diff] [blame]788 EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT();
789 unsigned TotalBits = ShAmount->getZExtValue() + ExtendTy.getSizeInBits();
790
791 if (TotalBits == 32 ||
792 (Op0Op0->getOpcode() == MipsISD::VEXTRACT_SEXT_ELT &&
793 TotalBits <= 32)) {
794 SDValue Ops[] = { Op0Op0->getOperand(0), Op0Op0->getOperand(1),
795 Op0Op0->getOperand(2) };
Chandler Carruth356665a2014-08-01 22:09:43 +0000[diff] [blame]796 return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, SDLoc(Op0Op0),
797 Op0Op0->getVTList(),
798 makeArrayRef(Ops, Op0Op0->getNumOperands()));
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000[diff] [blame]799 }
800 }
801 }
802
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]803 if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget.hasDSPR2()))
Akira Hatanaka1ebb2a12013-04-19 23:21:32 +0000[diff] [blame]804 return SDValue();
805
806 return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget);
807}
808
809
810static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG,
811 TargetLowering::DAGCombinerInfo &DCI,
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]812 const MipsSubtarget &Subtarget) {
Akira Hatanaka1ebb2a12013-04-19 23:21:32 +0000[diff] [blame]813 EVT Ty = N->getValueType(0);
814
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]815 if (((Ty != MVT::v2i16) || !Subtarget.hasDSPR2()) && (Ty != MVT::v4i8))
Akira Hatanaka1ebb2a12013-04-19 23:21:32 +0000[diff] [blame]816 return SDValue();
817
818 return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget);
819}
820
Akira Hatanaka68741cc2013-04-30 22:37:26 +0000[diff] [blame]821static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) {
822 bool IsV216 = (Ty == MVT::v2i16);
823
824 switch (CC) {
825 case ISD::SETEQ:
826 case ISD::SETNE: return true;
827 case ISD::SETLT:
828 case ISD::SETLE:
829 case ISD::SETGT:
830 case ISD::SETGE: return IsV216;
831 case ISD::SETULT:
832 case ISD::SETULE:
833 case ISD::SETUGT:
834 case ISD::SETUGE: return !IsV216;
835 default: return false;
836 }
837}
838
839static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) {
840 EVT Ty = N->getValueType(0);
841
842 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
843 return SDValue();
844
845 if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get()))
846 return SDValue();
847
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]848 return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0),
Akira Hatanaka68741cc2013-04-30 22:37:26 +0000[diff] [blame]849 N->getOperand(1), N->getOperand(2));
850}
851
852static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) {
853 EVT Ty = N->getValueType(0);
854
Daniel Sanders3ce56622013-09-24 12:18:31 +0000[diff] [blame]855 if (Ty.is128BitVector() && Ty.isInteger()) {
856 // Try the following combines:
857 // (vselect (setcc $a, $b, SETLT), $b, $a)) -> (vsmax $a, $b)
858 // (vselect (setcc $a, $b, SETLE), $b, $a)) -> (vsmax $a, $b)
859 // (vselect (setcc $a, $b, SETLT), $a, $b)) -> (vsmin $a, $b)
860 // (vselect (setcc $a, $b, SETLE), $a, $b)) -> (vsmin $a, $b)
861 // (vselect (setcc $a, $b, SETULT), $b, $a)) -> (vumax $a, $b)
862 // (vselect (setcc $a, $b, SETULE), $b, $a)) -> (vumax $a, $b)
863 // (vselect (setcc $a, $b, SETULT), $a, $b)) -> (vumin $a, $b)
864 // (vselect (setcc $a, $b, SETULE), $a, $b)) -> (vumin $a, $b)
865 // SETGT/SETGE/SETUGT/SETUGE variants of these will show up initially but
866 // will be expanded to equivalent SETLT/SETLE/SETULT/SETULE versions by the
867 // legalizer.
868 SDValue Op0 = N->getOperand(0);
Akira Hatanaka68741cc2013-04-30 22:37:26 +0000[diff] [blame]869
Daniel Sanders3ce56622013-09-24 12:18:31 +0000[diff] [blame]870 if (Op0->getOpcode() != ISD::SETCC)
871 return SDValue();
Akira Hatanaka68741cc2013-04-30 22:37:26 +0000[diff] [blame]872
Daniel Sanders3ce56622013-09-24 12:18:31 +0000[diff] [blame]873 ISD::CondCode CondCode = cast<CondCodeSDNode>(Op0->getOperand(2))->get();
874 bool Signed;
Akira Hatanaka68741cc2013-04-30 22:37:26 +0000[diff] [blame]875
Daniel Sanders3ce56622013-09-24 12:18:31 +0000[diff] [blame]876 if (CondCode == ISD::SETLT || CondCode == ISD::SETLE)
877 Signed = true;
878 else if (CondCode == ISD::SETULT || CondCode == ISD::SETULE)
879 Signed = false;
880 else
881 return SDValue();
882
883 SDValue Op1 = N->getOperand(1);
884 SDValue Op2 = N->getOperand(2);
885 SDValue Op0Op0 = Op0->getOperand(0);
886 SDValue Op0Op1 = Op0->getOperand(1);
887
888 if (Op1 == Op0Op0 && Op2 == Op0Op1)
889 return DAG.getNode(Signed ? MipsISD::VSMIN : MipsISD::VUMIN, SDLoc(N),
890 Ty, Op1, Op2);
891 else if (Op1 == Op0Op1 && Op2 == Op0Op0)
892 return DAG.getNode(Signed ? MipsISD::VSMAX : MipsISD::VUMAX, SDLoc(N),
893 Ty, Op1, Op2);
894 } else if ((Ty == MVT::v2i16) || (Ty == MVT::v4i8)) {
895 SDValue SetCC = N->getOperand(0);
896
897 if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
898 return SDValue();
899
900 return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty,
901 SetCC.getOperand(0), SetCC.getOperand(1),
902 N->getOperand(1), N->getOperand(2), SetCC.getOperand(2));
903 }
904
905 return SDValue();
Akira Hatanaka68741cc2013-04-30 22:37:26 +0000[diff] [blame]906}
907
Daniel Sandersf7456c72013-09-23 13:22:24 +0000[diff] [blame]908static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG,
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]909 const MipsSubtarget &Subtarget) {
Daniel Sandersf7456c72013-09-23 13:22:24 +0000[diff] [blame]910 EVT Ty = N->getValueType(0);
911
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]912 if (Subtarget.hasMSA() && Ty.is128BitVector() && Ty.isInteger()) {
Daniel Sandersf7456c72013-09-23 13:22:24 +0000[diff] [blame]913 // Try the following combines:
914 // (xor (or $a, $b), (build_vector allones))
915 // (xor (or $a, $b), (bitcast (build_vector allones)))
916 SDValue Op0 = N->getOperand(0);
917 SDValue Op1 = N->getOperand(1);
918 SDValue NotOp;
Daniel Sandersf7456c72013-09-23 13:22:24 +0000[diff] [blame]919
920 if (ISD::isBuildVectorAllOnes(Op0.getNode()))
921 NotOp = Op1;
922 else if (ISD::isBuildVectorAllOnes(Op1.getNode()))
923 NotOp = Op0;
Daniel Sandersf7456c72013-09-23 13:22:24 +0000[diff] [blame]924 else
925 return SDValue();
926
927 if (NotOp->getOpcode() == ISD::OR)
928 return DAG.getNode(MipsISD::VNOR, SDLoc(N), Ty, NotOp->getOperand(0),
929 NotOp->getOperand(1));
930 }
931
932 return SDValue();
933}
934
Akira Hatanaka9efcd762013-03-30 01:42:24 +0000[diff] [blame]935SDValue
936MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
937 SelectionDAG &DAG = DCI.DAG;
Akira Hatanaka68741cc2013-04-30 22:37:26 +0000[diff] [blame]938 SDValue Val;
Akira Hatanaka9efcd762013-03-30 01:42:24 +0000[diff] [blame]939
940 switch (N->getOpcode()) {
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000[diff] [blame]941 case ISD::AND:
942 Val = performANDCombine(N, DAG, DCI, Subtarget);
943 break;
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000[diff] [blame]944 case ISD::OR:
945 Val = performORCombine(N, DAG, DCI, Subtarget);
946 break;
Akira Hatanaka5832fc62013-06-26 18:48:17 +0000[diff] [blame]947 case ISD::MUL:
948 return performMULCombine(N, DAG, DCI, this);
Akira Hatanaka1ebb2a12013-04-19 23:21:32 +0000[diff] [blame]949 case ISD::SHL:
Petar Jovanovicb71386a2017-03-15 13:10:08 +0000[diff] [blame]950 Val = performSHLCombine(N, DAG, DCI, Subtarget);
951 break;
Akira Hatanaka1ebb2a12013-04-19 23:21:32 +0000[diff] [blame]952 case ISD::SRA:
953 return performSRACombine(N, DAG, DCI, Subtarget);
954 case ISD::SRL:
955 return performSRLCombine(N, DAG, DCI, Subtarget);
Akira Hatanaka68741cc2013-04-30 22:37:26 +0000[diff] [blame]956 case ISD::VSELECT:
957 return performVSELECTCombine(N, DAG);
Daniel Sandersf7456c72013-09-23 13:22:24 +0000[diff] [blame]958 case ISD::XOR:
959 Val = performXORCombine(N, DAG, Subtarget);
960 break;
961 case ISD::SETCC:
Akira Hatanaka68741cc2013-04-30 22:37:26 +0000[diff] [blame]962 Val = performSETCCCombine(N, DAG);
963 break;
Akira Hatanaka9efcd762013-03-30 01:42:24 +0000[diff] [blame]964 }
Akira Hatanaka68741cc2013-04-30 22:37:26 +0000[diff] [blame]965
Daniel Sanders62aeab82013-10-30 13:31:27 +0000[diff] [blame]966 if (Val.getNode()) {
967 DEBUG(dbgs() << "\nMipsSE DAG Combine:\n";
968 N->printrWithDepth(dbgs(), &DAG);
969 dbgs() << "\n=> \n";
970 Val.getNode()->printrWithDepth(dbgs(), &DAG);
971 dbgs() << "\n");
Akira Hatanaka68741cc2013-04-30 22:37:26 +0000[diff] [blame]972 return Val;
Daniel Sanders62aeab82013-10-30 13:31:27 +0000[diff] [blame]973 }
Akira Hatanaka68741cc2013-04-30 22:37:26 +0000[diff] [blame]974
975 return MipsTargetLowering::PerformDAGCombine(N, DCI);
Akira Hatanaka9efcd762013-03-30 01:42:24 +0000[diff] [blame]976}
977
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]978MachineBasicBlock *
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]979MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]980 MachineBasicBlock *BB) const {
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]981 switch (MI.getOpcode()) {
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]982 default:
983 return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
984 case Mips::BPOSGE32_PSEUDO:
985 return emitBPOSGE32(MI, BB);
Daniel Sandersce09d072013-08-28 12:14:50 +0000[diff] [blame]986 case Mips::SNZ_B_PSEUDO:
987 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B);
988 case Mips::SNZ_H_PSEUDO:
989 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H);
990 case Mips::SNZ_W_PSEUDO:
991 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W);
992 case Mips::SNZ_D_PSEUDO:
993 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D);
994 case Mips::SNZ_V_PSEUDO:
995 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V);
996 case Mips::SZ_B_PSEUDO:
997 return emitMSACBranchPseudo(MI, BB, Mips::BZ_B);
998 case Mips::SZ_H_PSEUDO:
999 return emitMSACBranchPseudo(MI, BB, Mips::BZ_H);
1000 case Mips::SZ_W_PSEUDO:
1001 return emitMSACBranchPseudo(MI, BB, Mips::BZ_W);
1002 case Mips::SZ_D_PSEUDO:
1003 return emitMSACBranchPseudo(MI, BB, Mips::BZ_D);
1004 case Mips::SZ_V_PSEUDO:
1005 return emitMSACBranchPseudo(MI, BB, Mips::BZ_V);
Daniel Sanders39bb8ba2013-09-27 12:17:32 +0000[diff] [blame]1006 case Mips::COPY_FW_PSEUDO:
1007 return emitCOPY_FW(MI, BB);
1008 case Mips::COPY_FD_PSEUDO:
1009 return emitCOPY_FD(MI, BB);
Daniel Sandersa5150702013-09-27 12:31:32 +0000[diff] [blame]1010 case Mips::INSERT_FW_PSEUDO:
1011 return emitINSERT_FW(MI, BB);
1012 case Mips::INSERT_FD_PSEUDO:
1013 return emitINSERT_FD(MI, BB);
Daniel Sanderse296a0f2014-04-30 12:09:32 +0000[diff] [blame]1014 case Mips::INSERT_B_VIDX_PSEUDO:
Daniel Sanderseda60d22015-05-05 10:32:24 +0000[diff] [blame]1015 case Mips::INSERT_B_VIDX64_PSEUDO:
Daniel Sanderse296a0f2014-04-30 12:09:32 +0000[diff] [blame]1016 return emitINSERT_DF_VIDX(MI, BB, 1, false);
1017 case Mips::INSERT_H_VIDX_PSEUDO:
Daniel Sanderseda60d22015-05-05 10:32:24 +0000[diff] [blame]1018 case Mips::INSERT_H_VIDX64_PSEUDO:
Daniel Sanderse296a0f2014-04-30 12:09:32 +0000[diff] [blame]1019 return emitINSERT_DF_VIDX(MI, BB, 2, false);
1020 case Mips::INSERT_W_VIDX_PSEUDO:
Daniel Sanderseda60d22015-05-05 10:32:24 +0000[diff] [blame]1021 case Mips::INSERT_W_VIDX64_PSEUDO:
Daniel Sanderse296a0f2014-04-30 12:09:32 +0000[diff] [blame]1022 return emitINSERT_DF_VIDX(MI, BB, 4, false);
1023 case Mips::INSERT_D_VIDX_PSEUDO:
Daniel Sanderseda60d22015-05-05 10:32:24 +0000[diff] [blame]1024 case Mips::INSERT_D_VIDX64_PSEUDO:
Daniel Sanderse296a0f2014-04-30 12:09:32 +0000[diff] [blame]1025 return emitINSERT_DF_VIDX(MI, BB, 8, false);
1026 case Mips::INSERT_FW_VIDX_PSEUDO:
Daniel Sanderseda60d22015-05-05 10:32:24 +0000[diff] [blame]1027 case Mips::INSERT_FW_VIDX64_PSEUDO:
Daniel Sanderse296a0f2014-04-30 12:09:32 +0000[diff] [blame]1028 return emitINSERT_DF_VIDX(MI, BB, 4, true);
1029 case Mips::INSERT_FD_VIDX_PSEUDO:
Daniel Sanderseda60d22015-05-05 10:32:24 +0000[diff] [blame]1030 case Mips::INSERT_FD_VIDX64_PSEUDO:
Daniel Sanderse296a0f2014-04-30 12:09:32 +0000[diff] [blame]1031 return emitINSERT_DF_VIDX(MI, BB, 8, true);
Daniel Sanders1dfddc72013-10-15 13:14:41 +0000[diff] [blame]1032 case Mips::FILL_FW_PSEUDO:
1033 return emitFILL_FW(MI, BB);
1034 case Mips::FILL_FD_PSEUDO:
1035 return emitFILL_FD(MI, BB);
Daniel Sandersa9521602013-10-23 10:36:52 +0000[diff] [blame]1036 case Mips::FEXP2_W_1_PSEUDO:
1037 return emitFEXP2_W_1(MI, BB);
1038 case Mips::FEXP2_D_1_PSEUDO:
1039 return emitFEXP2_D_1(MI, BB);
Simon Dardis0e2ee3b2016-11-18 16:17:44 +0000[diff] [blame]1040 case Mips::ST_F16:
1041 return emitST_F16_PSEUDO(MI, BB);
1042 case Mips::LD_F16:
1043 return emitLD_F16_PSEUDO(MI, BB);
1044 case Mips::MSA_FP_EXTEND_W_PSEUDO:
1045 return emitFPEXTEND_PSEUDO(MI, BB, false);
1046 case Mips::MSA_FP_ROUND_W_PSEUDO:
1047 return emitFPROUND_PSEUDO(MI, BB, false);
1048 case Mips::MSA_FP_EXTEND_D_PSEUDO:
1049 return emitFPEXTEND_PSEUDO(MI, BB, true);
1050 case Mips::MSA_FP_ROUND_D_PSEUDO:
1051 return emitFPROUND_PSEUDO(MI, BB, true);
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]1052 }
1053}
1054
Daniel Sanders23e98772014-11-02 16:09:29 +0000[diff] [blame]1055bool MipsSETargetLowering::isEligibleForTailCallOptimization(
1056 const CCState &CCInfo, unsigned NextStackOffset,
1057 const MipsFunctionInfo &FI) const {
Simon Dardis57f4ae42016-08-04 09:17:07 +0000[diff] [blame]1058 if (!UseMipsTailCalls)
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]1059 return false;
1060
Vasileios Kalintiris43dff0c2015-10-26 12:38:43 +0000[diff] [blame]1061 // Exception has to be cleared with eret.
1062 if (FI.isISR())
1063 return false;
1064
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]1065 // Return false if either the callee or caller has a byval argument.
Daniel Sanders23e98772014-11-02 16:09:29 +0000[diff] [blame]1066 if (CCInfo.getInRegsParamsCount() > 0 || FI.hasByvalArg())
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]1067 return false;
1068
1069 // Return true if the callee's argument area is no larger than the
1070 // caller's.
1071 return NextStackOffset <= FI.getIncomingArgSize();
1072}
1073
1074void MipsSETargetLowering::
1075getOpndList(SmallVectorImpl<SDValue> &Ops,
1076 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
1077 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
Sasa Stankovic7072a792014-10-01 08:22:21 +0000[diff] [blame]1078 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
1079 SDValue Chain) const {
Akira Hatanaka168d4e52013-11-27 23:38:42 +0000[diff] [blame]1080 Ops.push_back(Callee);
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]1081 MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
Sasa Stankovic7072a792014-10-01 08:22:21 +0000[diff] [blame]1082 InternalLinkage, IsCallReloc, CLI, Callee,
1083 Chain);
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]1084}
1085
Akira Hatanaka63791212013-09-07 00:52:30 +0000[diff] [blame]1086SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1087 LoadSDNode &Nd = *cast<LoadSDNode>(Op);
1088
1089 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
1090 return MipsTargetLowering::lowerLOAD(Op, DAG);
1091
1092 // Replace a double precision load with two i32 loads and a buildpair64.
1093 SDLoc DL(Op);
1094 SDValue Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
1095 EVT PtrVT = Ptr.getValueType();
1096
1097 // i32 load from lower address.
Justin Lebar9c375812016-07-15 18:27:10 +0000[diff] [blame]1098 SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, Ptr, MachinePointerInfo(),
1099 Nd.getAlignment(), Nd.getMemOperand()->getFlags());
Akira Hatanaka63791212013-09-07 00:52:30 +0000[diff] [blame]1100
1101 // i32 load from higher address.
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]1102 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, DL, PtrVT));
Justin Lebar9c375812016-07-15 18:27:10 +0000[diff] [blame]1103 SDValue Hi = DAG.getLoad(
1104 MVT::i32, DL, Lo.getValue(1), Ptr, MachinePointerInfo(),
1105 std::min(Nd.getAlignment(), 4U), Nd.getMemOperand()->getFlags());
Akira Hatanaka63791212013-09-07 00:52:30 +0000[diff] [blame]1106
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]1107 if (!Subtarget.isLittle())
Akira Hatanaka63791212013-09-07 00:52:30 +0000[diff] [blame]1108 std::swap(Lo, Hi);
1109
1110 SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
1111 SDValue Ops[2] = {BP, Hi.getValue(1)};
Craig Topper64941d92014-04-27 19:20:57 +0000[diff] [blame]1112 return DAG.getMergeValues(Ops, DL);
Akira Hatanaka63791212013-09-07 00:52:30 +0000[diff] [blame]1113}
1114
1115SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1116 StoreSDNode &Nd = *cast<StoreSDNode>(Op);
1117
1118 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
1119 return MipsTargetLowering::lowerSTORE(Op, DAG);
1120
1121 // Replace a double precision store with two extractelement64s and i32 stores.
1122 SDLoc DL(Op);
1123 SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
1124 EVT PtrVT = Ptr.getValueType();
1125 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]1126 Val, DAG.getConstant(0, DL, MVT::i32));
Akira Hatanaka63791212013-09-07 00:52:30 +0000[diff] [blame]1127 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]1128 Val, DAG.getConstant(1, DL, MVT::i32));
Akira Hatanaka63791212013-09-07 00:52:30 +0000[diff] [blame]1129
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]1130 if (!Subtarget.isLittle())
Akira Hatanaka63791212013-09-07 00:52:30 +0000[diff] [blame]1131 std::swap(Lo, Hi);
1132
1133 // i32 store to lower address.
Justin Lebar9c375812016-07-15 18:27:10 +0000[diff] [blame]1134 Chain =
1135 DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(), Nd.getAlignment(),
1136 Nd.getMemOperand()->getFlags(), Nd.getAAInfo());
Akira Hatanaka63791212013-09-07 00:52:30 +0000[diff] [blame]1137
1138 // i32 store to higher address.
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]1139 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, DL, PtrVT));
Akira Hatanaka63791212013-09-07 00:52:30 +0000[diff] [blame]1140 return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(),
Justin Lebar9c375812016-07-15 18:27:10 +0000[diff] [blame]1141 std::min(Nd.getAlignment(), 4U),
1142 Nd.getMemOperand()->getFlags(), Nd.getAAInfo());
Akira Hatanaka63791212013-09-07 00:52:30 +0000[diff] [blame]1143}
1144
Akira Hatanakabe8612f2013-03-30 01:36:35 +0000[diff] [blame]1145SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
1146 bool HasLo, bool HasHi,
1147 SelectionDAG &DAG) const {
Daniel Sanders308181e2014-06-12 10:44:10 +0000[diff] [blame]1148 // MIPS32r6/MIPS64r6 removed accumulator based multiplies.
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]1149 assert(!Subtarget.hasMips32r6());
Daniel Sanders308181e2014-06-12 10:44:10 +0000[diff] [blame]1150
Akira Hatanakabe8612f2013-03-30 01:36:35 +0000[diff] [blame]1151 EVT Ty = Op.getOperand(0).getValueType();
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]1152 SDLoc DL(Op);
Akira Hatanakabe8612f2013-03-30 01:36:35 +0000[diff] [blame]1153 SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
1154 Op.getOperand(0), Op.getOperand(1));
1155 SDValue Lo, Hi;
1156
1157 if (HasLo)
Akira Hatanakad98c99f2013-10-15 01:12:50 +0000[diff] [blame]1158 Lo = DAG.getNode(MipsISD::MFLO, DL, Ty, Mult);
Akira Hatanakabe8612f2013-03-30 01:36:35 +0000[diff] [blame]1159 if (HasHi)
Akira Hatanakad98c99f2013-10-15 01:12:50 +0000[diff] [blame]1160 Hi = DAG.getNode(MipsISD::MFHI, DL, Ty, Mult);
Akira Hatanakabe8612f2013-03-30 01:36:35 +0000[diff] [blame]1161
1162 if (!HasLo || !HasHi)
1163 return HasLo ? Lo : Hi;
1164
1165 SDValue Vals[] = { Lo, Hi };
Craig Topper64941d92014-04-27 19:20:57 +0000[diff] [blame]1166 return DAG.getMergeValues(Vals, DL);
Akira Hatanakabe8612f2013-03-30 01:36:35 +0000[diff] [blame]1167}
1168
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]1169static SDValue initAccumulator(SDValue In, const SDLoc &DL, SelectionDAG &DAG) {
Akira Hatanakaa6bbde52013-04-13 02:13:30 +0000[diff] [blame]1170 SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]1171 DAG.getConstant(0, DL, MVT::i32));
Akira Hatanakaa6bbde52013-04-13 02:13:30 +0000[diff] [blame]1172 SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]1173 DAG.getConstant(1, DL, MVT::i32));
Akira Hatanakad98c99f2013-10-15 01:12:50 +0000[diff] [blame]1174 return DAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, InLo, InHi);
Akira Hatanakaa6bbde52013-04-13 02:13:30 +0000[diff] [blame]1175}
1176
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]1177static SDValue extractLOHI(SDValue Op, const SDLoc &DL, SelectionDAG &DAG) {
Akira Hatanakad98c99f2013-10-15 01:12:50 +0000[diff] [blame]1178 SDValue Lo = DAG.getNode(MipsISD::MFLO, DL, MVT::i32, Op);
1179 SDValue Hi = DAG.getNode(MipsISD::MFHI, DL, MVT::i32, Op);
Akira Hatanakaa6bbde52013-04-13 02:13:30 +0000[diff] [blame]1180 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
1181}
1182
1183// This function expands mips intrinsic nodes which have 64-bit input operands
1184// or output values.
1185//
1186// out64 = intrinsic-node in64
1187// =>
1188// lo = copy (extract-element (in64, 0))
1189// hi = copy (extract-element (in64, 1))
1190// mips-specific-node
1191// v0 = copy lo
1192// v1 = copy hi
1193// out64 = merge-values (v0, v1)
1194//
1195static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]1196 SDLoc DL(Op);
Akira Hatanakaa6bbde52013-04-13 02:13:30 +0000[diff] [blame]1197 bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
1198 SmallVector<SDValue, 3> Ops;
1199 unsigned OpNo = 0;
1200
1201 // See if Op has a chain input.
1202 if (HasChainIn)
1203 Ops.push_back(Op->getOperand(OpNo++));
1204
1205 // The next operand is the intrinsic opcode.
1206 assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant);
1207
1208 // See if the next operand has type i64.
1209 SDValue Opnd = Op->getOperand(++OpNo), In64;
1210
1211 if (Opnd.getValueType() == MVT::i64)
1212 In64 = initAccumulator(Opnd, DL, DAG);
1213 else
1214 Ops.push_back(Opnd);
1215
1216 // Push the remaining operands.
1217 for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)
1218 Ops.push_back(Op->getOperand(OpNo));
1219
1220 // Add In64 to the end of the list.
1221 if (In64.getNode())
1222 Ops.push_back(In64);
1223
1224 // Scan output.
1225 SmallVector<EVT, 2> ResTys;
1226
1227 for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end();
1228 I != E; ++I)
1229 ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I);
1230
1231 // Create node.
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]1232 SDValue Val = DAG.getNode(Opc, DL, ResTys, Ops);
Akira Hatanakaa6bbde52013-04-13 02:13:30 +0000[diff] [blame]1233 SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;
1234
1235 if (!HasChainIn)
1236 return Out;
1237
1238 assert(Val->getValueType(1) == MVT::Other);
1239 SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) };
Craig Topper64941d92014-04-27 19:20:57 +0000[diff] [blame]1240 return DAG.getMergeValues(Vals, DL);
Akira Hatanakaa6bbde52013-04-13 02:13:30 +0000[diff] [blame]1241}
1242
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000[diff] [blame]1243// Lower an MSA copy intrinsic into the specified SelectionDAG node
1244static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1245 SDLoc DL(Op);
1246 SDValue Vec = Op->getOperand(1);
1247 SDValue Idx = Op->getOperand(2);
1248 EVT ResTy = Op->getValueType(0);
1249 EVT EltTy = Vec->getValueType(0).getVectorElementType();
1250
1251 SDValue Result = DAG.getNode(Opc, DL, ResTy, Vec, Idx,
1252 DAG.getValueType(EltTy));
1253
1254 return Result;
1255}
1256
Daniel Sanders50b80412013-11-15 12:56:49 +0000[diff] [blame]1257static SDValue lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG) {
1258 EVT ResVecTy = Op->getValueType(0);
1259 EVT ViaVecTy = ResVecTy;
1260 SDLoc DL(Op);
Daniel Sanders86d0c8d2013-09-23 14:29:55 +0000[diff] [blame]1261
Daniel Sanders50b80412013-11-15 12:56:49 +0000[diff] [blame]1262 // When ResVecTy == MVT::v2i64, LaneA is the upper 32 bits of the lane and
1263 // LaneB is the lower 32-bits. Otherwise LaneA and LaneB are alternating
1264 // lanes.
1265 SDValue LaneA;
1266 SDValue LaneB = Op->getOperand(2);
1267
1268 if (ResVecTy == MVT::v2i64) {
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]1269 LaneA = DAG.getConstant(0, DL, MVT::i32);
Daniel Sandersf49dd822013-09-24 13:33:07 +0000[diff] [blame]1270 ViaVecTy = MVT::v4i32;
Daniel Sanders50b80412013-11-15 12:56:49 +0000[diff] [blame]1271 } else
1272 LaneA = LaneB;
Daniel Sanders86d0c8d2013-09-23 14:29:55 +0000[diff] [blame]1273
Daniel Sanders50b80412013-11-15 12:56:49 +0000[diff] [blame]1274 SDValue Ops[16] = { LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB,
1275 LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB };
Daniel Sandersf49dd822013-09-24 13:33:07 +0000[diff] [blame]1276
Ahmed Bougacha128f8732016-04-26 21:15:30 +0000[diff] [blame]1277 SDValue Result = DAG.getBuildVector(
1278 ViaVecTy, DL, makeArrayRef(Ops, ViaVecTy.getVectorNumElements()));
Daniel Sanders50b80412013-11-15 12:56:49 +0000[diff] [blame]1279
1280 if (ViaVecTy != ResVecTy)
1281 Result = DAG.getNode(ISD::BITCAST, DL, ResVecTy, Result);
Daniel Sandersf49dd822013-09-24 13:33:07 +0000[diff] [blame]1282
1283 return Result;
1284}
1285
Simon Dardis548a53f2017-01-10 16:40:57 +0000[diff] [blame]1286static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG,
1287 bool IsSigned = false) {
1288 return DAG.getConstant(
1289 APInt(Op->getValueType(0).getScalarType().getSizeInBits(),
1290 Op->getConstantOperandVal(ImmOp), IsSigned),
1291 SDLoc(Op), Op->getValueType(0));
Daniel Sanders50b80412013-11-15 12:56:49 +0000[diff] [blame]1292}
1293
1294static SDValue getBuildVectorSplat(EVT VecTy, SDValue SplatValue,
1295 bool BigEndian, SelectionDAG &DAG) {
1296 EVT ViaVecTy = VecTy;
1297 SDValue SplatValueA = SplatValue;
1298 SDValue SplatValueB = SplatValue;
1299 SDLoc DL(SplatValue);
1300
1301 if (VecTy == MVT::v2i64) {
1302 // v2i64 BUILD_VECTOR must be performed via v4i32 so split into i32's.
1303 ViaVecTy = MVT::v4i32;
1304
1305 SplatValueA = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValue);
1306 SplatValueB = DAG.getNode(ISD::SRL, DL, MVT::i64, SplatValue,
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]1307 DAG.getConstant(32, DL, MVT::i32));
Daniel Sanders50b80412013-11-15 12:56:49 +0000[diff] [blame]1308 SplatValueB = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValueB);
1309 }
1310
1311 // We currently hold the parts in little endian order. Swap them if
1312 // necessary.
1313 if (BigEndian)
1314 std::swap(SplatValueA, SplatValueB);
1315
1316 SDValue Ops[16] = { SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1317 SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1318 SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1319 SplatValueA, SplatValueB, SplatValueA, SplatValueB };
1320
Ahmed Bougacha128f8732016-04-26 21:15:30 +0000[diff] [blame]1321 SDValue Result = DAG.getBuildVector(
1322 ViaVecTy, DL, makeArrayRef(Ops, ViaVecTy.getVectorNumElements()));
Daniel Sanders50b80412013-11-15 12:56:49 +0000[diff] [blame]1323
1324 if (VecTy != ViaVecTy)
1325 Result = DAG.getNode(ISD::BITCAST, DL, VecTy, Result);
1326
1327 return Result;
Daniel Sandersf5bd9372013-09-11 10:51:30 +0000[diff] [blame]1328}
1329
Daniel Sandersa5bc99f2013-11-12 10:31:49 +0000[diff] [blame]1330static SDValue lowerMSABinaryBitImmIntr(SDValue Op, SelectionDAG &DAG,
1331 unsigned Opc, SDValue Imm,
1332 bool BigEndian) {
1333 EVT VecTy = Op->getValueType(0);
1334 SDValue Exp2Imm;
1335 SDLoc DL(Op);
1336
Daniel Sanders50b80412013-11-15 12:56:49 +0000[diff] [blame]1337 // The DAG Combiner can't constant fold bitcasted vectors yet so we must do it
1338 // here for now.
Daniel Sandersa5bc99f2013-11-12 10:31:49 +0000[diff] [blame]1339 if (VecTy == MVT::v2i64) {
1340 if (ConstantSDNode *CImm = dyn_cast<ConstantSDNode>(Imm)) {
1341 APInt BitImm = APInt(64, 1) << CImm->getAPIntValue();
1342
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]1343 SDValue BitImmHiOp = DAG.getConstant(BitImm.lshr(32).trunc(32), DL,
1344 MVT::i32);
1345 SDValue BitImmLoOp = DAG.getConstant(BitImm.trunc(32), DL, MVT::i32);
Daniel Sanders50b80412013-11-15 12:56:49 +0000[diff] [blame]1346
1347 if (BigEndian)
1348 std::swap(BitImmLoOp, BitImmHiOp);
1349
Ahmed Bougacha128f8732016-04-26 21:15:30 +0000[diff] [blame]1350 Exp2Imm = DAG.getNode(
1351 ISD::BITCAST, DL, MVT::v2i64,
1352 DAG.getBuildVector(MVT::v4i32, DL,
1353 {BitImmLoOp, BitImmHiOp, BitImmLoOp, BitImmHiOp}));
Daniel Sandersa5bc99f2013-11-12 10:31:49 +0000[diff] [blame]1354 }
1355 }
1356
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1357 if (!Exp2Imm.getNode()) {
Daniel Sandersa5bc99f2013-11-12 10:31:49 +0000[diff] [blame]1358 // We couldnt constant fold, do a vector shift instead
Daniel Sanders50b80412013-11-15 12:56:49 +0000[diff] [blame]1359
1360 // Extend i32 to i64 if necessary. Sign or zero extend doesn't matter since
1361 // only values 0-63 are valid.
1362 if (VecTy == MVT::v2i64)
1363 Imm = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Imm);
1364
1365 Exp2Imm = getBuildVectorSplat(VecTy, Imm, BigEndian, DAG);
1366
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]1367 Exp2Imm = DAG.getNode(ISD::SHL, DL, VecTy, DAG.getConstant(1, DL, VecTy),
1368 Exp2Imm);
Daniel Sandersa5bc99f2013-11-12 10:31:49 +0000[diff] [blame]1369 }
1370
1371 return DAG.getNode(Opc, DL, VecTy, Op->getOperand(1), Exp2Imm);
1372}
1373
Petar Jovanovic2b6fe3f2017-04-20 13:26:46 +0000[diff] [blame]1374static SDValue truncateVecElts(SDValue Op, SelectionDAG &DAG) {
1375 SDLoc DL(Op);
1376 EVT ResTy = Op->getValueType(0);
1377 SDValue Vec = Op->getOperand(2);
1378 bool BigEndian = !DAG.getSubtarget().getTargetTriple().isLittleEndian();
1379 MVT ResEltTy = ResTy == MVT::v2i64 ? MVT::i64 : MVT::i32;
1380 SDValue ConstValue = DAG.getConstant(Vec.getScalarValueSizeInBits() - 1,
1381 DL, ResEltTy);
1382 SDValue SplatVec = getBuildVectorSplat(ResTy, ConstValue, BigEndian, DAG);
1383
1384 return DAG.getNode(ISD::AND, DL, ResTy, Vec, SplatVec);
1385}
1386
Daniel Sanders3f6eb542013-11-12 10:45:18 +0000[diff] [blame]1387static SDValue lowerMSABitClear(SDValue Op, SelectionDAG &DAG) {
1388 EVT ResTy = Op->getValueType(0);
Daniel Sanders3f6eb542013-11-12 10:45:18 +0000[diff] [blame]1389 SDLoc DL(Op);
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]1390 SDValue One = DAG.getConstant(1, DL, ResTy);
Petar Jovanovic2b6fe3f2017-04-20 13:26:46 +0000[diff] [blame]1391 SDValue Bit = DAG.getNode(ISD::SHL, DL, ResTy, One, truncateVecElts(Op, DAG));
Daniel Sanders3f6eb542013-11-12 10:45:18 +0000[diff] [blame]1392
Daniel Sanders71ce0ca2013-11-15 16:02:04 +0000[diff] [blame]1393 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1),
1394 DAG.getNOT(DL, Bit, ResTy));
Daniel Sanders3f6eb542013-11-12 10:45:18 +0000[diff] [blame]1395}
1396
1397static SDValue lowerMSABitClearImm(SDValue Op, SelectionDAG &DAG) {
1398 SDLoc DL(Op);
1399 EVT ResTy = Op->getValueType(0);
Sanjay Patel1ed771f2016-09-14 16:37:15 +0000[diff] [blame]1400 APInt BitImm = APInt(ResTy.getScalarSizeInBits(), 1)
Daniel Sanders50b80412013-11-15 12:56:49 +0000[diff] [blame]1401 << cast<ConstantSDNode>(Op->getOperand(2))->getAPIntValue();
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]1402 SDValue BitMask = DAG.getConstant(~BitImm, DL, ResTy);
Daniel Sanders3f6eb542013-11-12 10:45:18 +0000[diff] [blame]1403
1404 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), BitMask);
1405}
1406
Akira Hatanakaa6bbde52013-04-13 02:13:30 +0000[diff] [blame]1407SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
1408 SelectionDAG &DAG) const {
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1409 SDLoc DL(Op);
Simon Dardis548a53f2017-01-10 16:40:57 +0000[diff] [blame]1410 unsigned Intrinsic = cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue();
1411 switch (Intrinsic) {
Akira Hatanakaa6bbde52013-04-13 02:13:30 +0000[diff] [blame]1412 default:
1413 return SDValue();
1414 case Intrinsic::mips_shilo:
1415 return lowerDSPIntr(Op, DAG, MipsISD::SHILO);
1416 case Intrinsic::mips_dpau_h_qbl:
1417 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL);
1418 case Intrinsic::mips_dpau_h_qbr:
1419 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR);
1420 case Intrinsic::mips_dpsu_h_qbl:
1421 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL);
1422 case Intrinsic::mips_dpsu_h_qbr:
1423 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR);
1424 case Intrinsic::mips_dpa_w_ph:
1425 return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH);
1426 case Intrinsic::mips_dps_w_ph:
1427 return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH);
1428 case Intrinsic::mips_dpax_w_ph:
1429 return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH);
1430 case Intrinsic::mips_dpsx_w_ph:
1431 return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH);
1432 case Intrinsic::mips_mulsa_w_ph:
1433 return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH);
1434 case Intrinsic::mips_mult:
1435 return lowerDSPIntr(Op, DAG, MipsISD::Mult);
1436 case Intrinsic::mips_multu:
1437 return lowerDSPIntr(Op, DAG, MipsISD::Multu);
1438 case Intrinsic::mips_madd:
1439 return lowerDSPIntr(Op, DAG, MipsISD::MAdd);
1440 case Intrinsic::mips_maddu:
1441 return lowerDSPIntr(Op, DAG, MipsISD::MAddu);
1442 case Intrinsic::mips_msub:
1443 return lowerDSPIntr(Op, DAG, MipsISD::MSub);
1444 case Intrinsic::mips_msubu:
1445 return lowerDSPIntr(Op, DAG, MipsISD::MSubu);
Daniel Sandersfa5ab1c2013-09-11 10:28:16 +0000[diff] [blame]1446 case Intrinsic::mips_addv_b:
1447 case Intrinsic::mips_addv_h:
1448 case Intrinsic::mips_addv_w:
1449 case Intrinsic::mips_addv_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1450 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1451 Op->getOperand(2));
Daniel Sanders86d0c8d2013-09-23 14:29:55 +0000[diff] [blame]1452 case Intrinsic::mips_addvi_b:
1453 case Intrinsic::mips_addvi_h:
1454 case Intrinsic::mips_addvi_w:
1455 case Intrinsic::mips_addvi_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1456 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1457 lowerMSASplatImm(Op, 2, DAG));
Daniel Sanders8ca81e42013-09-23 12:57:42 +0000[diff] [blame]1458 case Intrinsic::mips_and_v:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1459 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1460 Op->getOperand(2));
Daniel Sandersbfc39ce2013-09-24 12:32:47 +0000[diff] [blame]1461 case Intrinsic::mips_andi_b:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1462 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1463 lowerMSASplatImm(Op, 2, DAG));
Daniel Sanders3f6eb542013-11-12 10:45:18 +0000[diff] [blame]1464 case Intrinsic::mips_bclr_b:
1465 case Intrinsic::mips_bclr_h:
1466 case Intrinsic::mips_bclr_w:
1467 case Intrinsic::mips_bclr_d:
1468 return lowerMSABitClear(Op, DAG);
1469 case Intrinsic::mips_bclri_b:
1470 case Intrinsic::mips_bclri_h:
1471 case Intrinsic::mips_bclri_w:
1472 case Intrinsic::mips_bclri_d:
1473 return lowerMSABitClearImm(Op, DAG);
Daniel Sandersd74b1302013-10-30 14:45:14 +0000[diff] [blame]1474 case Intrinsic::mips_binsli_b:
1475 case Intrinsic::mips_binsli_h:
1476 case Intrinsic::mips_binsli_w:
1477 case Intrinsic::mips_binsli_d: {
Daniel Sandersdf2215452014-03-12 11:54:00 +0000[diff] [blame]1478 // binsli_x(IfClear, IfSet, nbits) -> (vselect LBitsMask, IfSet, IfClear)
Daniel Sandersd74b1302013-10-30 14:45:14 +0000[diff] [blame]1479 EVT VecTy = Op->getValueType(0);
1480 EVT EltTy = VecTy.getVectorElementType();
Simon Dardis548a53f2017-01-10 16:40:57 +0000[diff] [blame]1481 if (Op->getConstantOperandVal(3) >= EltTy.getSizeInBits())
1482 report_fatal_error("Immediate out of range");
Daniel Sandersd74b1302013-10-30 14:45:14 +0000[diff] [blame]1483 APInt Mask = APInt::getHighBitsSet(EltTy.getSizeInBits(),
Petar Jovanovicbc54eb82017-04-07 13:31:36 +0000[diff] [blame]1484 Op->getConstantOperandVal(3) + 1);
Daniel Sandersd74b1302013-10-30 14:45:14 +0000[diff] [blame]1485 return DAG.getNode(ISD::VSELECT, DL, VecTy,
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]1486 DAG.getConstant(Mask, DL, VecTy, true),
1487 Op->getOperand(2), Op->getOperand(1));
Daniel Sandersd74b1302013-10-30 14:45:14 +0000[diff] [blame]1488 }
1489 case Intrinsic::mips_binsri_b:
1490 case Intrinsic::mips_binsri_h:
1491 case Intrinsic::mips_binsri_w:
1492 case Intrinsic::mips_binsri_d: {
Daniel Sandersdf2215452014-03-12 11:54:00 +0000[diff] [blame]1493 // binsri_x(IfClear, IfSet, nbits) -> (vselect RBitsMask, IfSet, IfClear)
Daniel Sandersd74b1302013-10-30 14:45:14 +0000[diff] [blame]1494 EVT VecTy = Op->getValueType(0);
1495 EVT EltTy = VecTy.getVectorElementType();
Simon Dardis548a53f2017-01-10 16:40:57 +0000[diff] [blame]1496 if (Op->getConstantOperandVal(3) >= EltTy.getSizeInBits())
1497 report_fatal_error("Immediate out of range");
Daniel Sandersd74b1302013-10-30 14:45:14 +0000[diff] [blame]1498 APInt Mask = APInt::getLowBitsSet(EltTy.getSizeInBits(),
Petar Jovanovicbc54eb82017-04-07 13:31:36 +0000[diff] [blame]1499 Op->getConstantOperandVal(3) + 1);
Daniel Sandersd74b1302013-10-30 14:45:14 +0000[diff] [blame]1500 return DAG.getNode(ISD::VSELECT, DL, VecTy,
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]1501 DAG.getConstant(Mask, DL, VecTy, true),
1502 Op->getOperand(2), Op->getOperand(1));
Daniel Sandersd74b1302013-10-30 14:45:14 +0000[diff] [blame]1503 }
Daniel Sandersab94b532013-10-30 15:20:38 +0000[diff] [blame]1504 case Intrinsic::mips_bmnz_v:
1505 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1506 Op->getOperand(2), Op->getOperand(1));
1507 case Intrinsic::mips_bmnzi_b:
1508 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1509 lowerMSASplatImm(Op, 3, DAG), Op->getOperand(2),
1510 Op->getOperand(1));
1511 case Intrinsic::mips_bmz_v:
1512 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1513 Op->getOperand(1), Op->getOperand(2));
1514 case Intrinsic::mips_bmzi_b:
1515 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1516 lowerMSASplatImm(Op, 3, DAG), Op->getOperand(1),
1517 Op->getOperand(2));
Daniel Sandersa5bc99f2013-11-12 10:31:49 +0000[diff] [blame]1518 case Intrinsic::mips_bneg_b:
1519 case Intrinsic::mips_bneg_h:
1520 case Intrinsic::mips_bneg_w:
1521 case Intrinsic::mips_bneg_d: {
1522 EVT VecTy = Op->getValueType(0);
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]1523 SDValue One = DAG.getConstant(1, DL, VecTy);
Daniel Sandersa5bc99f2013-11-12 10:31:49 +0000[diff] [blame]1524
1525 return DAG.getNode(ISD::XOR, DL, VecTy, Op->getOperand(1),
1526 DAG.getNode(ISD::SHL, DL, VecTy, One,
Petar Jovanovic2b6fe3f2017-04-20 13:26:46 +0000[diff] [blame]1527 truncateVecElts(Op, DAG)));
Daniel Sandersa5bc99f2013-11-12 10:31:49 +0000[diff] [blame]1528 }
1529 case Intrinsic::mips_bnegi_b:
1530 case Intrinsic::mips_bnegi_h:
1531 case Intrinsic::mips_bnegi_w:
1532 case Intrinsic::mips_bnegi_d:
1533 return lowerMSABinaryBitImmIntr(Op, DAG, ISD::XOR, Op->getOperand(2),
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]1534 !Subtarget.isLittle());
Daniel Sandersce09d072013-08-28 12:14:50 +0000[diff] [blame]1535 case Intrinsic::mips_bnz_b:
1536 case Intrinsic::mips_bnz_h:
1537 case Intrinsic::mips_bnz_w:
1538 case Intrinsic::mips_bnz_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1539 return DAG.getNode(MipsISD::VALL_NONZERO, DL, Op->getValueType(0),
1540 Op->getOperand(1));
Daniel Sandersce09d072013-08-28 12:14:50 +0000[diff] [blame]1541 case Intrinsic::mips_bnz_v:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1542 return DAG.getNode(MipsISD::VANY_NONZERO, DL, Op->getValueType(0),
1543 Op->getOperand(1));
Daniel Sanderse1d24352013-09-24 12:04:44 +0000[diff] [blame]1544 case Intrinsic::mips_bsel_v:
Daniel Sandersdf2215452014-03-12 11:54:00 +0000[diff] [blame]1545 // bsel_v(Mask, IfClear, IfSet) -> (vselect Mask, IfSet, IfClear)
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1546 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
Daniel Sandersdf2215452014-03-12 11:54:00 +0000[diff] [blame]1547 Op->getOperand(1), Op->getOperand(3),
1548 Op->getOperand(2));
Daniel Sanderse1d24352013-09-24 12:04:44 +0000[diff] [blame]1549 case Intrinsic::mips_bseli_b:
Daniel Sandersdf2215452014-03-12 11:54:00 +0000[diff] [blame]1550 // bseli_v(Mask, IfClear, IfSet) -> (vselect Mask, IfSet, IfClear)
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1551 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
Daniel Sandersdf2215452014-03-12 11:54:00 +0000[diff] [blame]1552 Op->getOperand(1), lowerMSASplatImm(Op, 3, DAG),
1553 Op->getOperand(2));
Daniel Sandersa5bc99f2013-11-12 10:31:49 +0000[diff] [blame]1554 case Intrinsic::mips_bset_b:
1555 case Intrinsic::mips_bset_h:
1556 case Intrinsic::mips_bset_w:
1557 case Intrinsic::mips_bset_d: {
1558 EVT VecTy = Op->getValueType(0);
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]1559 SDValue One = DAG.getConstant(1, DL, VecTy);
Daniel Sandersa5bc99f2013-11-12 10:31:49 +0000[diff] [blame]1560
1561 return DAG.getNode(ISD::OR, DL, VecTy, Op->getOperand(1),
1562 DAG.getNode(ISD::SHL, DL, VecTy, One,
Petar Jovanovic2b6fe3f2017-04-20 13:26:46 +0000[diff] [blame]1563 truncateVecElts(Op, DAG)));
Daniel Sandersa5bc99f2013-11-12 10:31:49 +0000[diff] [blame]1564 }
1565 case Intrinsic::mips_bseti_b:
1566 case Intrinsic::mips_bseti_h:
1567 case Intrinsic::mips_bseti_w:
1568 case Intrinsic::mips_bseti_d:
1569 return lowerMSABinaryBitImmIntr(Op, DAG, ISD::OR, Op->getOperand(2),
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]1570 !Subtarget.isLittle());
Daniel Sandersce09d072013-08-28 12:14:50 +0000[diff] [blame]1571 case Intrinsic::mips_bz_b:
1572 case Intrinsic::mips_bz_h:
1573 case Intrinsic::mips_bz_w:
1574 case Intrinsic::mips_bz_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1575 return DAG.getNode(MipsISD::VALL_ZERO, DL, Op->getValueType(0),
1576 Op->getOperand(1));
Daniel Sandersce09d072013-08-28 12:14:50 +0000[diff] [blame]1577 case Intrinsic::mips_bz_v:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1578 return DAG.getNode(MipsISD::VANY_ZERO, DL, Op->getValueType(0),
1579 Op->getOperand(1));
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1580 case Intrinsic::mips_ceq_b:
1581 case Intrinsic::mips_ceq_h:
1582 case Intrinsic::mips_ceq_w:
1583 case Intrinsic::mips_ceq_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1584 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1585 Op->getOperand(2), ISD::SETEQ);
1586 case Intrinsic::mips_ceqi_b:
1587 case Intrinsic::mips_ceqi_h:
1588 case Intrinsic::mips_ceqi_w:
1589 case Intrinsic::mips_ceqi_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1590 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Simon Dardis548a53f2017-01-10 16:40:57 +0000[diff] [blame]1591 lowerMSASplatImm(Op, 2, DAG, true), ISD::SETEQ);
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1592 case Intrinsic::mips_cle_s_b:
1593 case Intrinsic::mips_cle_s_h:
1594 case Intrinsic::mips_cle_s_w:
1595 case Intrinsic::mips_cle_s_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1596 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1597 Op->getOperand(2), ISD::SETLE);
1598 case Intrinsic::mips_clei_s_b:
1599 case Intrinsic::mips_clei_s_h:
1600 case Intrinsic::mips_clei_s_w:
1601 case Intrinsic::mips_clei_s_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1602 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Simon Dardis548a53f2017-01-10 16:40:57 +0000[diff] [blame]1603 lowerMSASplatImm(Op, 2, DAG, true), ISD::SETLE);
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1604 case Intrinsic::mips_cle_u_b:
1605 case Intrinsic::mips_cle_u_h:
1606 case Intrinsic::mips_cle_u_w:
1607 case Intrinsic::mips_cle_u_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1608 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1609 Op->getOperand(2), ISD::SETULE);
1610 case Intrinsic::mips_clei_u_b:
1611 case Intrinsic::mips_clei_u_h:
1612 case Intrinsic::mips_clei_u_w:
1613 case Intrinsic::mips_clei_u_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1614 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1615 lowerMSASplatImm(Op, 2, DAG), ISD::SETULE);
1616 case Intrinsic::mips_clt_s_b:
1617 case Intrinsic::mips_clt_s_h:
1618 case Intrinsic::mips_clt_s_w:
1619 case Intrinsic::mips_clt_s_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1620 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1621 Op->getOperand(2), ISD::SETLT);
1622 case Intrinsic::mips_clti_s_b:
1623 case Intrinsic::mips_clti_s_h:
1624 case Intrinsic::mips_clti_s_w:
1625 case Intrinsic::mips_clti_s_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1626 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Simon Dardis548a53f2017-01-10 16:40:57 +0000[diff] [blame]1627 lowerMSASplatImm(Op, 2, DAG, true), ISD::SETLT);
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1628 case Intrinsic::mips_clt_u_b:
1629 case Intrinsic::mips_clt_u_h:
1630 case Intrinsic::mips_clt_u_w:
1631 case Intrinsic::mips_clt_u_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1632 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1633 Op->getOperand(2), ISD::SETULT);
1634 case Intrinsic::mips_clti_u_b:
1635 case Intrinsic::mips_clti_u_h:
1636 case Intrinsic::mips_clti_u_w:
1637 case Intrinsic::mips_clti_u_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1638 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1639 lowerMSASplatImm(Op, 2, DAG), ISD::SETULT);
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000[diff] [blame]1640 case Intrinsic::mips_copy_s_b:
1641 case Intrinsic::mips_copy_s_h:
1642 case Intrinsic::mips_copy_s_w:
1643 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
Daniel Sanders7f3d9462013-09-27 13:04:21 +0000[diff] [blame]1644 case Intrinsic::mips_copy_s_d:
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]1645 if (Subtarget.hasMips64())
Matheus Almeida74070322014-01-29 14:05:28 +0000[diff] [blame]1646 // Lower directly into VEXTRACT_SEXT_ELT since i64 is legal on Mips64.
1647 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
1648 else {
1649 // Lower into the generic EXTRACT_VECTOR_ELT node and let the type
1650 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1651 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
1652 Op->getValueType(0), Op->getOperand(1),
1653 Op->getOperand(2));
1654 }
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000[diff] [blame]1655 case Intrinsic::mips_copy_u_b:
1656 case Intrinsic::mips_copy_u_h:
1657 case Intrinsic::mips_copy_u_w:
1658 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
Daniel Sanders7f3d9462013-09-27 13:04:21 +0000[diff] [blame]1659 case Intrinsic::mips_copy_u_d:
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]1660 if (Subtarget.hasMips64())
Matheus Almeida74070322014-01-29 14:05:28 +0000[diff] [blame]1661 // Lower directly into VEXTRACT_ZEXT_ELT since i64 is legal on Mips64.
1662 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
1663 else {
1664 // Lower into the generic EXTRACT_VECTOR_ELT node and let the type
1665 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1666 // Note: When i64 is illegal, this results in copy_s.w instructions
1667 // instead of copy_u.w instructions. This makes no difference to the
1668 // behaviour since i64 is only illegal when the register file is 32-bit.
1669 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
1670 Op->getValueType(0), Op->getOperand(1),
1671 Op->getOperand(2));
1672 }
Daniel Sanders607952b2013-09-11 10:38:58 +0000[diff] [blame]1673 case Intrinsic::mips_div_s_b:
1674 case Intrinsic::mips_div_s_h:
1675 case Intrinsic::mips_div_s_w:
1676 case Intrinsic::mips_div_s_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1677 return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1),
1678 Op->getOperand(2));
Daniel Sanders607952b2013-09-11 10:38:58 +0000[diff] [blame]1679 case Intrinsic::mips_div_u_b:
1680 case Intrinsic::mips_div_u_h:
1681 case Intrinsic::mips_div_u_w:
1682 case Intrinsic::mips_div_u_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1683 return DAG.getNode(ISD::UDIV, DL, Op->getValueType(0), Op->getOperand(1),
1684 Op->getOperand(2));
Daniel Sandersf5bd9372013-09-11 10:51:30 +0000[diff] [blame]1685 case Intrinsic::mips_fadd_w:
Sanjay Patela2607012015-09-16 16:31:21 +0000[diff] [blame]1686 case Intrinsic::mips_fadd_d: {
1687 // TODO: If intrinsics have fast-math-flags, propagate them.
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1688 return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1),
1689 Op->getOperand(2));
Sanjay Patela2607012015-09-16 16:31:21 +0000[diff] [blame]1690 }
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1691 // Don't lower mips_fcaf_[wd] since LLVM folds SETFALSE condcodes away
1692 case Intrinsic::mips_fceq_w:
1693 case Intrinsic::mips_fceq_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1694 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1695 Op->getOperand(2), ISD::SETOEQ);
1696 case Intrinsic::mips_fcle_w:
1697 case Intrinsic::mips_fcle_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1698 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1699 Op->getOperand(2), ISD::SETOLE);
1700 case Intrinsic::mips_fclt_w:
1701 case Intrinsic::mips_fclt_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1702 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1703 Op->getOperand(2), ISD::SETOLT);
1704 case Intrinsic::mips_fcne_w:
1705 case Intrinsic::mips_fcne_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1706 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1707 Op->getOperand(2), ISD::SETONE);
1708 case Intrinsic::mips_fcor_w:
1709 case Intrinsic::mips_fcor_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1710 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1711 Op->getOperand(2), ISD::SETO);
1712 case Intrinsic::mips_fcueq_w:
1713 case Intrinsic::mips_fcueq_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1714 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1715 Op->getOperand(2), ISD::SETUEQ);
1716 case Intrinsic::mips_fcule_w:
1717 case Intrinsic::mips_fcule_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1718 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1719 Op->getOperand(2), ISD::SETULE);
1720 case Intrinsic::mips_fcult_w:
1721 case Intrinsic::mips_fcult_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1722 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1723 Op->getOperand(2), ISD::SETULT);
1724 case Intrinsic::mips_fcun_w:
1725 case Intrinsic::mips_fcun_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1726 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1727 Op->getOperand(2), ISD::SETUO);
1728 case Intrinsic::mips_fcune_w:
1729 case Intrinsic::mips_fcune_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1730 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000[diff] [blame]1731 Op->getOperand(2), ISD::SETUNE);
Daniel Sandersf5bd9372013-09-11 10:51:30 +0000[diff] [blame]1732 case Intrinsic::mips_fdiv_w:
Sanjay Patela2607012015-09-16 16:31:21 +0000[diff] [blame]1733 case Intrinsic::mips_fdiv_d: {
1734 // TODO: If intrinsics have fast-math-flags, propagate them.
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1735 return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1),
1736 Op->getOperand(2));
Sanjay Patela2607012015-09-16 16:31:21 +0000[diff] [blame]1737 }
Daniel Sanders015972b2013-10-11 10:00:06 +0000[diff] [blame]1738 case Intrinsic::mips_ffint_u_w:
1739 case Intrinsic::mips_ffint_u_d:
1740 return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0),
1741 Op->getOperand(1));
1742 case Intrinsic::mips_ffint_s_w:
1743 case Intrinsic::mips_ffint_s_d:
1744 return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0),
1745 Op->getOperand(1));
Daniel Sanders7a289d02013-09-23 12:02:46 +0000[diff] [blame]1746 case Intrinsic::mips_fill_b:
1747 case Intrinsic::mips_fill_h:
Daniel Sandersc72593e2013-09-27 13:20:41 +0000[diff] [blame]1748 case Intrinsic::mips_fill_w:
1749 case Intrinsic::mips_fill_d: {
Daniel Sandersf49dd822013-09-24 13:33:07 +0000[diff] [blame]1750 EVT ResTy = Op->getValueType(0);
Benjamin Kramer6cd780f2015-02-17 15:29:18 +0000[diff] [blame]1751 SmallVector<SDValue, 16> Ops(ResTy.getVectorNumElements(),
1752 Op->getOperand(1));
Daniel Sandersf49dd822013-09-24 13:33:07 +0000[diff] [blame]1753
Daniel Sandersc72593e2013-09-27 13:20:41 +0000[diff] [blame]1754 // If ResTy is v2i64 then the type legalizer will break this node down into
1755 // an equivalent v4i32.
Ahmed Bougacha128f8732016-04-26 21:15:30 +0000[diff] [blame]1756 return DAG.getBuildVector(ResTy, DL, Ops);
Daniel Sandersf49dd822013-09-24 13:33:07 +0000[diff] [blame]1757 }
Daniel Sandersa9521602013-10-23 10:36:52 +0000[diff] [blame]1758 case Intrinsic::mips_fexp2_w:
1759 case Intrinsic::mips_fexp2_d: {
Sanjay Patela2607012015-09-16 16:31:21 +0000[diff] [blame]1760 // TODO: If intrinsics have fast-math-flags, propagate them.
Daniel Sandersa9521602013-10-23 10:36:52 +0000[diff] [blame]1761 EVT ResTy = Op->getValueType(0);
1762 return DAG.getNode(
1763 ISD::FMUL, SDLoc(Op), ResTy, Op->getOperand(1),
1764 DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2)));
1765 }
Daniel Sandersf5bd9372013-09-11 10:51:30 +0000[diff] [blame]1766 case Intrinsic::mips_flog2_w:
1767 case Intrinsic::mips_flog2_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1768 return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1));
Daniel Sandersd7103f32013-10-11 10:14:25 +0000[diff] [blame]1769 case Intrinsic::mips_fmadd_w:
1770 case Intrinsic::mips_fmadd_d:
1771 return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0),
1772 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
Daniel Sandersf5bd9372013-09-11 10:51:30 +0000[diff] [blame]1773 case Intrinsic::mips_fmul_w:
Sanjay Patela2607012015-09-16 16:31:21 +0000[diff] [blame]1774 case Intrinsic::mips_fmul_d: {
1775 // TODO: If intrinsics have fast-math-flags, propagate them.
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1776 return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1),
1777 Op->getOperand(2));
Sanjay Patela2607012015-09-16 16:31:21 +0000[diff] [blame]1778 }
Daniel Sanderse67bd872013-10-11 10:27:32 +0000[diff] [blame]1779 case Intrinsic::mips_fmsub_w:
1780 case Intrinsic::mips_fmsub_d: {
Sanjay Patela2607012015-09-16 16:31:21 +0000[diff] [blame]1781 // TODO: If intrinsics have fast-math-flags, propagate them.
Daniel Sanderse67bd872013-10-11 10:27:32 +0000[diff] [blame]1782 EVT ResTy = Op->getValueType(0);
1783 return DAG.getNode(ISD::FSUB, SDLoc(Op), ResTy, Op->getOperand(1),
1784 DAG.getNode(ISD::FMUL, SDLoc(Op), ResTy,
1785 Op->getOperand(2), Op->getOperand(3)));
1786 }
Daniel Sandersf5bd9372013-09-11 10:51:30 +0000[diff] [blame]1787 case Intrinsic::mips_frint_w:
1788 case Intrinsic::mips_frint_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1789 return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1));
Daniel Sandersf5bd9372013-09-11 10:51:30 +0000[diff] [blame]1790 case Intrinsic::mips_fsqrt_w:
1791 case Intrinsic::mips_fsqrt_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1792 return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1));
Daniel Sandersf5bd9372013-09-11 10:51:30 +0000[diff] [blame]1793 case Intrinsic::mips_fsub_w:
Sanjay Patela2607012015-09-16 16:31:21 +0000[diff] [blame]1794 case Intrinsic::mips_fsub_d: {
1795 // TODO: If intrinsics have fast-math-flags, propagate them.
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1796 return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1),
1797 Op->getOperand(2));
Sanjay Patela2607012015-09-16 16:31:21 +0000[diff] [blame]1798 }
Daniel Sanders015972b2013-10-11 10:00:06 +0000[diff] [blame]1799 case Intrinsic::mips_ftrunc_u_w:
1800 case Intrinsic::mips_ftrunc_u_d:
1801 return DAG.getNode(ISD::FP_TO_UINT, DL, Op->getValueType(0),
1802 Op->getOperand(1));
1803 case Intrinsic::mips_ftrunc_s_w:
1804 case Intrinsic::mips_ftrunc_s_d:
1805 return DAG.getNode(ISD::FP_TO_SINT, DL, Op->getValueType(0),
1806 Op->getOperand(1));
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]1807 case Intrinsic::mips_ilvev_b:
1808 case Intrinsic::mips_ilvev_h:
1809 case Intrinsic::mips_ilvev_w:
1810 case Intrinsic::mips_ilvev_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1811 return DAG.getNode(MipsISD::ILVEV, DL, Op->getValueType(0),
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]1812 Op->getOperand(1), Op->getOperand(2));
1813 case Intrinsic::mips_ilvl_b:
1814 case Intrinsic::mips_ilvl_h:
1815 case Intrinsic::mips_ilvl_w:
1816 case Intrinsic::mips_ilvl_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1817 return DAG.getNode(MipsISD::ILVL, DL, Op->getValueType(0),
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]1818 Op->getOperand(1), Op->getOperand(2));
1819 case Intrinsic::mips_ilvod_b:
1820 case Intrinsic::mips_ilvod_h:
1821 case Intrinsic::mips_ilvod_w:
1822 case Intrinsic::mips_ilvod_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1823 return DAG.getNode(MipsISD::ILVOD, DL, Op->getValueType(0),
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]1824 Op->getOperand(1), Op->getOperand(2));
1825 case Intrinsic::mips_ilvr_b:
1826 case Intrinsic::mips_ilvr_h:
1827 case Intrinsic::mips_ilvr_w:
1828 case Intrinsic::mips_ilvr_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1829 return DAG.getNode(MipsISD::ILVR, DL, Op->getValueType(0),
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]1830 Op->getOperand(1), Op->getOperand(2));
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000[diff] [blame]1831 case Intrinsic::mips_insert_b:
1832 case Intrinsic::mips_insert_h:
1833 case Intrinsic::mips_insert_w:
Daniel Sanders6098b332013-09-27 13:36:54 +0000[diff] [blame]1834 case Intrinsic::mips_insert_d:
1835 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
1836 Op->getOperand(1), Op->getOperand(3), Op->getOperand(2));
Daniel Sandersb50ccf82014-04-01 10:35:28 +0000[diff] [blame]1837 case Intrinsic::mips_insve_b:
1838 case Intrinsic::mips_insve_h:
1839 case Intrinsic::mips_insve_w:
Simon Dardis548a53f2017-01-10 16:40:57 +0000[diff] [blame]1840 case Intrinsic::mips_insve_d: {
1841 // Report an error for out of range values.
1842 int64_t Max;
1843 switch (Intrinsic) {
1844 case Intrinsic::mips_insve_b: Max = 15; break;
1845 case Intrinsic::mips_insve_h: Max = 7; break;
1846 case Intrinsic::mips_insve_w: Max = 3; break;
1847 case Intrinsic::mips_insve_d: Max = 1; break;
1848 default: llvm_unreachable("Unmatched intrinsic");
1849 }
1850 int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
1851 if (Value < 0 || Value > Max)
1852 report_fatal_error("Immediate out of range");
Daniel Sandersb50ccf82014-04-01 10:35:28 +0000[diff] [blame]1853 return DAG.getNode(MipsISD::INSVE, DL, Op->getValueType(0),
1854 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3),
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]1855 DAG.getConstant(0, DL, MVT::i32));
Simon Dardis548a53f2017-01-10 16:40:57 +0000[diff] [blame]1856 }
Daniel Sanders7a289d02013-09-23 12:02:46 +0000[diff] [blame]1857 case Intrinsic::mips_ldi_b:
1858 case Intrinsic::mips_ldi_h:
1859 case Intrinsic::mips_ldi_w:
1860 case Intrinsic::mips_ldi_d:
Simon Dardis548a53f2017-01-10 16:40:57 +0000[diff] [blame]1861 return lowerMSASplatImm(Op, 1, DAG, true);
Matheus Almeida4b27eb52014-02-10 12:05:17 +0000[diff] [blame]1862 case Intrinsic::mips_lsa:
1863 case Intrinsic::mips_dlsa: {
Daniel Sandersa4eaf592013-10-17 13:38:20 +0000[diff] [blame]1864 EVT ResTy = Op->getValueType(0);
1865 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1866 DAG.getNode(ISD::SHL, SDLoc(Op), ResTy,
1867 Op->getOperand(2), Op->getOperand(3)));
1868 }
Daniel Sanders50e5ed32013-10-11 10:50:42 +0000[diff] [blame]1869 case Intrinsic::mips_maddv_b:
1870 case Intrinsic::mips_maddv_h:
1871 case Intrinsic::mips_maddv_w:
1872 case Intrinsic::mips_maddv_d: {
1873 EVT ResTy = Op->getValueType(0);
1874 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1875 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
1876 Op->getOperand(2), Op->getOperand(3)));
1877 }
Daniel Sanders3ce56622013-09-24 12:18:31 +0000[diff] [blame]1878 case Intrinsic::mips_max_s_b:
1879 case Intrinsic::mips_max_s_h:
1880 case Intrinsic::mips_max_s_w:
1881 case Intrinsic::mips_max_s_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1882 return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0),
1883 Op->getOperand(1), Op->getOperand(2));
Daniel Sanders3ce56622013-09-24 12:18:31 +0000[diff] [blame]1884 case Intrinsic::mips_max_u_b:
1885 case Intrinsic::mips_max_u_h:
1886 case Intrinsic::mips_max_u_w:
1887 case Intrinsic::mips_max_u_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1888 return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0),
1889 Op->getOperand(1), Op->getOperand(2));
Daniel Sanders3ce56622013-09-24 12:18:31 +0000[diff] [blame]1890 case Intrinsic::mips_maxi_s_b:
1891 case Intrinsic::mips_maxi_s_h:
1892 case Intrinsic::mips_maxi_s_w:
1893 case Intrinsic::mips_maxi_s_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1894 return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0),
Simon Dardis548a53f2017-01-10 16:40:57 +0000[diff] [blame]1895 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG, true));
Daniel Sanders3ce56622013-09-24 12:18:31 +0000[diff] [blame]1896 case Intrinsic::mips_maxi_u_b:
1897 case Intrinsic::mips_maxi_u_h:
1898 case Intrinsic::mips_maxi_u_w:
1899 case Intrinsic::mips_maxi_u_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1900 return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0),
1901 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
Daniel Sanders3ce56622013-09-24 12:18:31 +0000[diff] [blame]1902 case Intrinsic::mips_min_s_b:
1903 case Intrinsic::mips_min_s_h:
1904 case Intrinsic::mips_min_s_w:
1905 case Intrinsic::mips_min_s_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1906 return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0),
1907 Op->getOperand(1), Op->getOperand(2));
Daniel Sanders3ce56622013-09-24 12:18:31 +0000[diff] [blame]1908 case Intrinsic::mips_min_u_b:
1909 case Intrinsic::mips_min_u_h:
1910 case Intrinsic::mips_min_u_w:
1911 case Intrinsic::mips_min_u_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1912 return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0),
1913 Op->getOperand(1), Op->getOperand(2));
Daniel Sanders3ce56622013-09-24 12:18:31 +0000[diff] [blame]1914 case Intrinsic::mips_mini_s_b:
1915 case Intrinsic::mips_mini_s_h:
1916 case Intrinsic::mips_mini_s_w:
1917 case Intrinsic::mips_mini_s_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1918 return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0),
Simon Dardis548a53f2017-01-10 16:40:57 +0000[diff] [blame]1919 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG, true));
Daniel Sanders3ce56622013-09-24 12:18:31 +0000[diff] [blame]1920 case Intrinsic::mips_mini_u_b:
1921 case Intrinsic::mips_mini_u_h:
1922 case Intrinsic::mips_mini_u_w:
1923 case Intrinsic::mips_mini_u_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1924 return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0),
1925 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
Daniel Sanders0210dd42013-10-01 10:22:35 +0000[diff] [blame]1926 case Intrinsic::mips_mod_s_b:
1927 case Intrinsic::mips_mod_s_h:
1928 case Intrinsic::mips_mod_s_w:
1929 case Intrinsic::mips_mod_s_d:
1930 return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1),
1931 Op->getOperand(2));
1932 case Intrinsic::mips_mod_u_b:
1933 case Intrinsic::mips_mod_u_h:
1934 case Intrinsic::mips_mod_u_w:
1935 case Intrinsic::mips_mod_u_d:
1936 return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1),
1937 Op->getOperand(2));
Daniel Sandersfbcb5822013-09-11 11:58:30 +0000[diff] [blame]1938 case Intrinsic::mips_mulv_b:
1939 case Intrinsic::mips_mulv_h:
1940 case Intrinsic::mips_mulv_w:
1941 case Intrinsic::mips_mulv_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1942 return DAG.getNode(ISD::MUL, DL, Op->getValueType(0), Op->getOperand(1),
1943 Op->getOperand(2));
Daniel Sanders50e5ed32013-10-11 10:50:42 +0000[diff] [blame]1944 case Intrinsic::mips_msubv_b:
1945 case Intrinsic::mips_msubv_h:
1946 case Intrinsic::mips_msubv_w:
1947 case Intrinsic::mips_msubv_d: {
1948 EVT ResTy = Op->getValueType(0);
1949 return DAG.getNode(ISD::SUB, SDLoc(Op), ResTy, Op->getOperand(1),
1950 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
1951 Op->getOperand(2), Op->getOperand(3)));
1952 }
Daniel Sandersfbcb5822013-09-11 11:58:30 +0000[diff] [blame]1953 case Intrinsic::mips_nlzc_b:
1954 case Intrinsic::mips_nlzc_h:
1955 case Intrinsic::mips_nlzc_w:
1956 case Intrinsic::mips_nlzc_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1957 return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1));
Daniel Sandersf7456c72013-09-23 13:22:24 +0000[diff] [blame]1958 case Intrinsic::mips_nor_v: {
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1959 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
1960 Op->getOperand(1), Op->getOperand(2));
1961 return DAG.getNOT(DL, Res, Res->getValueType(0));
Daniel Sandersf7456c72013-09-23 13:22:24 +0000[diff] [blame]1962 }
Daniel Sandersbfc39ce2013-09-24 12:32:47 +0000[diff] [blame]1963 case Intrinsic::mips_nori_b: {
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1964 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
1965 Op->getOperand(1),
1966 lowerMSASplatImm(Op, 2, DAG));
1967 return DAG.getNOT(DL, Res, Res->getValueType(0));
Daniel Sandersbfc39ce2013-09-24 12:32:47 +0000[diff] [blame]1968 }
Daniel Sanders8ca81e42013-09-23 12:57:42 +0000[diff] [blame]1969 case Intrinsic::mips_or_v:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1970 return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1),
1971 Op->getOperand(2));
Daniel Sandersbfc39ce2013-09-24 12:32:47 +0000[diff] [blame]1972 case Intrinsic::mips_ori_b:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1973 return DAG.getNode(ISD::OR, DL, Op->getValueType(0),
1974 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
Daniel Sandersfae5f2a2013-09-24 14:53:25 +0000[diff] [blame]1975 case Intrinsic::mips_pckev_b:
1976 case Intrinsic::mips_pckev_h:
1977 case Intrinsic::mips_pckev_w:
1978 case Intrinsic::mips_pckev_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1979 return DAG.getNode(MipsISD::PCKEV, DL, Op->getValueType(0),
Daniel Sandersfae5f2a2013-09-24 14:53:25 +0000[diff] [blame]1980 Op->getOperand(1), Op->getOperand(2));
1981 case Intrinsic::mips_pckod_b:
1982 case Intrinsic::mips_pckod_h:
1983 case Intrinsic::mips_pckod_w:
1984 case Intrinsic::mips_pckod_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1985 return DAG.getNode(MipsISD::PCKOD, DL, Op->getValueType(0),
Daniel Sandersfae5f2a2013-09-24 14:53:25 +0000[diff] [blame]1986 Op->getOperand(1), Op->getOperand(2));
Daniel Sanders766cb692013-09-23 13:40:21 +0000[diff] [blame]1987 case Intrinsic::mips_pcnt_b:
1988 case Intrinsic::mips_pcnt_h:
1989 case Intrinsic::mips_pcnt_w:
1990 case Intrinsic::mips_pcnt_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]1991 return DAG.getNode(ISD::CTPOP, DL, Op->getValueType(0), Op->getOperand(1));
Simon Dardis548a53f2017-01-10 16:40:57 +0000[diff] [blame]1992 case Intrinsic::mips_sat_s_b:
1993 case Intrinsic::mips_sat_s_h:
1994 case Intrinsic::mips_sat_s_w:
1995 case Intrinsic::mips_sat_s_d:
1996 case Intrinsic::mips_sat_u_b:
1997 case Intrinsic::mips_sat_u_h:
1998 case Intrinsic::mips_sat_u_w:
1999 case Intrinsic::mips_sat_u_d: {
2000 // Report an error for out of range values.
2001 int64_t Max;
2002 switch (Intrinsic) {
2003 case Intrinsic::mips_sat_s_b:
2004 case Intrinsic::mips_sat_u_b: Max = 7; break;
2005 case Intrinsic::mips_sat_s_h:
2006 case Intrinsic::mips_sat_u_h: Max = 15; break;
2007 case Intrinsic::mips_sat_s_w:
2008 case Intrinsic::mips_sat_u_w: Max = 31; break;
2009 case Intrinsic::mips_sat_s_d:
2010 case Intrinsic::mips_sat_u_d: Max = 63; break;
2011 default: llvm_unreachable("Unmatched intrinsic");
2012 }
2013 int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
2014 if (Value < 0 || Value > Max)
2015 report_fatal_error("Immediate out of range");
2016 return SDValue();
2017 }
Daniel Sanders26307182013-09-24 14:20:00 +0000[diff] [blame]2018 case Intrinsic::mips_shf_b:
2019 case Intrinsic::mips_shf_h:
Simon Dardis548a53f2017-01-10 16:40:57 +0000[diff] [blame]2020 case Intrinsic::mips_shf_w: {
2021 int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
2022 if (Value < 0 || Value > 255)
2023 report_fatal_error("Immediate out of range");
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]2024 return DAG.getNode(MipsISD::SHF, DL, Op->getValueType(0),
Daniel Sanders26307182013-09-24 14:20:00 +0000[diff] [blame]2025 Op->getOperand(2), Op->getOperand(1));
Simon Dardis548a53f2017-01-10 16:40:57 +0000[diff] [blame]2026 }
2027 case Intrinsic::mips_sldi_b:
2028 case Intrinsic::mips_sldi_h:
2029 case Intrinsic::mips_sldi_w:
2030 case Intrinsic::mips_sldi_d: {
2031 // Report an error for out of range values.
2032 int64_t Max;
2033 switch (Intrinsic) {
2034 case Intrinsic::mips_sldi_b: Max = 15; break;
2035 case Intrinsic::mips_sldi_h: Max = 7; break;
2036 case Intrinsic::mips_sldi_w: Max = 3; break;
2037 case Intrinsic::mips_sldi_d: Max = 1; break;
2038 default: llvm_unreachable("Unmatched intrinsic");
2039 }
2040 int64_t Value = cast<ConstantSDNode>(Op->getOperand(3))->getSExtValue();
2041 if (Value < 0 || Value > Max)
2042 report_fatal_error("Immediate out of range");
2043 return SDValue();
2044 }
Daniel Sandersfbcb5822013-09-11 11:58:30 +0000[diff] [blame]2045 case Intrinsic::mips_sll_b:
2046 case Intrinsic::mips_sll_h:
2047 case Intrinsic::mips_sll_w:
2048 case Intrinsic::mips_sll_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]2049 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1),
Petar Jovanovic2b6fe3f2017-04-20 13:26:46 +0000[diff] [blame]2050 truncateVecElts(Op, DAG));
Daniel Sanderscba19222013-09-24 10:28:18 +0000[diff] [blame]2051 case Intrinsic::mips_slli_b:
2052 case Intrinsic::mips_slli_h:
2053 case Intrinsic::mips_slli_w:
2054 case Intrinsic::mips_slli_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]2055 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0),
2056 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
Daniel Sanderse7ef0c82013-10-30 13:07:44 +0000[diff] [blame]2057 case Intrinsic::mips_splat_b:
2058 case Intrinsic::mips_splat_h:
2059 case Intrinsic::mips_splat_w:
2060 case Intrinsic::mips_splat_d:
2061 // We can't lower via VECTOR_SHUFFLE because it requires constant shuffle
2062 // masks, nor can we lower via BUILD_VECTOR & EXTRACT_VECTOR_ELT because
2063 // EXTRACT_VECTOR_ELT can't extract i64's on MIPS32.
2064 // Instead we lower to MipsISD::VSHF and match from there.
2065 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
Daniel Sanders50b80412013-11-15 12:56:49 +0000[diff] [blame]2066 lowerMSASplatZExt(Op, 2, DAG), Op->getOperand(1),
Daniel Sanderse7ef0c82013-10-30 13:07:44 +0000[diff] [blame]2067 Op->getOperand(1));
Daniel Sanders7e51fe12013-09-27 11:48:57 +0000[diff] [blame]2068 case Intrinsic::mips_splati_b:
2069 case Intrinsic::mips_splati_h:
2070 case Intrinsic::mips_splati_w:
2071 case Intrinsic::mips_splati_d:
2072 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
2073 lowerMSASplatImm(Op, 2, DAG), Op->getOperand(1),
2074 Op->getOperand(1));
Daniel Sandersfbcb5822013-09-11 11:58:30 +0000[diff] [blame]2075 case Intrinsic::mips_sra_b:
2076 case Intrinsic::mips_sra_h:
2077 case Intrinsic::mips_sra_w:
2078 case Intrinsic::mips_sra_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]2079 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1),
Petar Jovanovic2b6fe3f2017-04-20 13:26:46 +0000[diff] [blame]2080 truncateVecElts(Op, DAG));
Daniel Sanderscba19222013-09-24 10:28:18 +0000[diff] [blame]2081 case Intrinsic::mips_srai_b:
2082 case Intrinsic::mips_srai_h:
2083 case Intrinsic::mips_srai_w:
2084 case Intrinsic::mips_srai_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]2085 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0),
2086 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
Simon Dardis548a53f2017-01-10 16:40:57 +0000[diff] [blame]2087 case Intrinsic::mips_srari_b:
2088 case Intrinsic::mips_srari_h:
2089 case Intrinsic::mips_srari_w:
2090 case Intrinsic::mips_srari_d: {
2091 // Report an error for out of range values.
2092 int64_t Max;
2093 switch (Intrinsic) {
2094 case Intrinsic::mips_srari_b: Max = 7; break;
2095 case Intrinsic::mips_srari_h: Max = 15; break;
2096 case Intrinsic::mips_srari_w: Max = 31; break;
2097 case Intrinsic::mips_srari_d: Max = 63; break;
2098 default: llvm_unreachable("Unmatched intrinsic");
2099 }
2100 int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
2101 if (Value < 0 || Value > Max)
2102 report_fatal_error("Immediate out of range");
2103 return SDValue();
2104 }
Daniel Sandersfbcb5822013-09-11 11:58:30 +0000[diff] [blame]2105 case Intrinsic::mips_srl_b:
2106 case Intrinsic::mips_srl_h:
2107 case Intrinsic::mips_srl_w:
2108 case Intrinsic::mips_srl_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]2109 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1),
Petar Jovanovic2b6fe3f2017-04-20 13:26:46 +0000[diff] [blame]2110 truncateVecElts(Op, DAG));
Daniel Sanderscba19222013-09-24 10:28:18 +0000[diff] [blame]2111 case Intrinsic::mips_srli_b:
2112 case Intrinsic::mips_srli_h:
2113 case Intrinsic::mips_srli_w:
2114 case Intrinsic::mips_srli_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]2115 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0),
2116 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
Simon Dardis548a53f2017-01-10 16:40:57 +0000[diff] [blame]2117 case Intrinsic::mips_srlri_b:
2118 case Intrinsic::mips_srlri_h:
2119 case Intrinsic::mips_srlri_w:
2120 case Intrinsic::mips_srlri_d: {
2121 // Report an error for out of range values.
2122 int64_t Max;
2123 switch (Intrinsic) {
2124 case Intrinsic::mips_srlri_b: Max = 7; break;
2125 case Intrinsic::mips_srlri_h: Max = 15; break;
2126 case Intrinsic::mips_srlri_w: Max = 31; break;
2127 case Intrinsic::mips_srlri_d: Max = 63; break;
2128 default: llvm_unreachable("Unmatched intrinsic");
2129 }
2130 int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
2131 if (Value < 0 || Value > Max)
2132 report_fatal_error("Immediate out of range");
2133 return SDValue();
2134 }
Daniel Sandersfbcb5822013-09-11 11:58:30 +0000[diff] [blame]2135 case Intrinsic::mips_subv_b:
2136 case Intrinsic::mips_subv_h:
2137 case Intrinsic::mips_subv_w:
2138 case Intrinsic::mips_subv_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]2139 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1),
2140 Op->getOperand(2));
Daniel Sanders86d0c8d2013-09-23 14:29:55 +0000[diff] [blame]2141 case Intrinsic::mips_subvi_b:
2142 case Intrinsic::mips_subvi_h:
2143 case Intrinsic::mips_subvi_w:
2144 case Intrinsic::mips_subvi_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]2145 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0),
2146 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
Daniel Sanderse5087042013-09-24 14:02:15 +0000[diff] [blame]2147 case Intrinsic::mips_vshf_b:
2148 case Intrinsic::mips_vshf_h:
2149 case Intrinsic::mips_vshf_w:
2150 case Intrinsic::mips_vshf_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]2151 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
Daniel Sanderse5087042013-09-24 14:02:15 +0000[diff] [blame]2152 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
Daniel Sanders8ca81e42013-09-23 12:57:42 +0000[diff] [blame]2153 case Intrinsic::mips_xor_v:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]2154 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1),
2155 Op->getOperand(2));
Daniel Sandersbfc39ce2013-09-24 12:32:47 +0000[diff] [blame]2156 case Intrinsic::mips_xori_b:
Daniel Sanders84e7caf2013-09-27 10:25:41 +0000[diff] [blame]2157 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0),
2158 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
Marcin Koscielnicki7efdca52016-04-27 17:21:49 +0000[diff] [blame]2159 case Intrinsic::thread_pointer: {
2160 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2161 return DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT);
2162 }
Akira Hatanakaa6bbde52013-04-13 02:13:30 +0000[diff] [blame]2163 }
2164}
2165
Simon Dardis548a53f2017-01-10 16:40:57 +0000[diff] [blame]2166static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr,
2167 const MipsSubtarget &Subtarget) {
Daniel Sanderse6ed5b72013-08-28 12:04:29 +0000[diff] [blame]2168 SDLoc DL(Op);
2169 SDValue ChainIn = Op->getOperand(0);
2170 SDValue Address = Op->getOperand(2);
2171 SDValue Offset = Op->getOperand(3);
2172 EVT ResTy = Op->getValueType(0);
2173 EVT PtrTy = Address->getValueType(0);
2174
Simon Dardis548a53f2017-01-10 16:40:57 +0000[diff] [blame]2175 // For N64 addresses have the underlying type MVT::i64. This intrinsic
2176 // however takes an i32 signed constant offset. The actual type of the
2177 // intrinsic is a scaled signed i10.
2178 if (Subtarget.isABI_N64())
2179 Offset = DAG.getNode(ISD::SIGN_EXTEND, DL, PtrTy, Offset);
2180
Daniel Sanderse6ed5b72013-08-28 12:04:29 +0000[diff] [blame]2181 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
Justin Lebar9c375812016-07-15 18:27:10 +0000[diff] [blame]2182 return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(),
2183 /* Alignment = */ 16);
Daniel Sanderse6ed5b72013-08-28 12:04:29 +0000[diff] [blame]2184}
2185
Akira Hatanakaa6bbde52013-04-13 02:13:30 +0000[diff] [blame]2186SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
2187 SelectionDAG &DAG) const {
Daniel Sanderse6ed5b72013-08-28 12:04:29 +0000[diff] [blame]2188 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
2189 switch (Intr) {
Akira Hatanakaa6bbde52013-04-13 02:13:30 +0000[diff] [blame]2190 default:
2191 return SDValue();
2192 case Intrinsic::mips_extp:
2193 return lowerDSPIntr(Op, DAG, MipsISD::EXTP);
2194 case Intrinsic::mips_extpdp:
2195 return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP);
2196 case Intrinsic::mips_extr_w:
2197 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W);
2198 case Intrinsic::mips_extr_r_w:
2199 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W);
2200 case Intrinsic::mips_extr_rs_w:
2201 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W);
2202 case Intrinsic::mips_extr_s_h:
2203 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H);
2204 case Intrinsic::mips_mthlip:
2205 return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP);
2206 case Intrinsic::mips_mulsaq_s_w_ph:
2207 return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH);
2208 case Intrinsic::mips_maq_s_w_phl:
2209 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL);
2210 case Intrinsic::mips_maq_s_w_phr:
2211 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR);
2212 case Intrinsic::mips_maq_sa_w_phl:
2213 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL);
2214 case Intrinsic::mips_maq_sa_w_phr:
2215 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR);
2216 case Intrinsic::mips_dpaq_s_w_ph:
2217 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH);
2218 case Intrinsic::mips_dpsq_s_w_ph:
2219 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH);
2220 case Intrinsic::mips_dpaq_sa_l_w:
2221 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W);
2222 case Intrinsic::mips_dpsq_sa_l_w:
2223 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W);
2224 case Intrinsic::mips_dpaqx_s_w_ph:
2225 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH);
2226 case Intrinsic::mips_dpaqx_sa_w_ph:
2227 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH);
2228 case Intrinsic::mips_dpsqx_s_w_ph:
2229 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH);
2230 case Intrinsic::mips_dpsqx_sa_w_ph:
2231 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH);
Daniel Sanderse6ed5b72013-08-28 12:04:29 +0000[diff] [blame]2232 case Intrinsic::mips_ld_b:
2233 case Intrinsic::mips_ld_h:
2234 case Intrinsic::mips_ld_w:
2235 case Intrinsic::mips_ld_d:
Simon Dardis548a53f2017-01-10 16:40:57 +0000[diff] [blame]2236 return lowerMSALoadIntr(Op, DAG, Intr, Subtarget);
Daniel Sanderse6ed5b72013-08-28 12:04:29 +0000[diff] [blame]2237 }
2238}
2239
Simon Dardis548a53f2017-01-10 16:40:57 +0000[diff] [blame]2240static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr,
2241 const MipsSubtarget &Subtarget) {
Daniel Sanderse6ed5b72013-08-28 12:04:29 +0000[diff] [blame]2242 SDLoc DL(Op);
2243 SDValue ChainIn = Op->getOperand(0);
2244 SDValue Value = Op->getOperand(2);
2245 SDValue Address = Op->getOperand(3);
2246 SDValue Offset = Op->getOperand(4);
2247 EVT PtrTy = Address->getValueType(0);
2248
Simon Dardis548a53f2017-01-10 16:40:57 +0000[diff] [blame]2249 // For N64 addresses have the underlying type MVT::i64. This intrinsic
2250 // however takes an i32 signed constant offset. The actual type of the
2251 // intrinsic is a scaled signed i10.
2252 if (Subtarget.isABI_N64())
2253 Offset = DAG.getNode(ISD::SIGN_EXTEND, DL, PtrTy, Offset);
2254
Daniel Sanderse6ed5b72013-08-28 12:04:29 +0000[diff] [blame]2255 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
2256
Justin Lebar9c375812016-07-15 18:27:10 +0000[diff] [blame]2257 return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(),
2258 /* Alignment = */ 16);
Daniel Sanderse6ed5b72013-08-28 12:04:29 +0000[diff] [blame]2259}
2260
2261SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op,
2262 SelectionDAG &DAG) const {
2263 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
2264 switch (Intr) {
2265 default:
2266 return SDValue();
2267 case Intrinsic::mips_st_b:
2268 case Intrinsic::mips_st_h:
2269 case Intrinsic::mips_st_w:
2270 case Intrinsic::mips_st_d:
Simon Dardis548a53f2017-01-10 16:40:57 +0000[diff] [blame]2271 return lowerMSAStoreIntr(Op, DAG, Intr, Subtarget);
Akira Hatanakaa6bbde52013-04-13 02:13:30 +0000[diff] [blame]2272 }
2273}
2274
Daniel Sanders7a289d02013-09-23 12:02:46 +0000[diff] [blame]2275/// \brief Check if the given BuildVectorSDNode is a splat.
2276/// This method currently relies on DAG nodes being reused when equivalent,
2277/// so it's possible for this to return false even when isConstantSplat returns
2278/// true.
2279static bool isSplatVector(const BuildVectorSDNode *N) {
Daniel Sanders7a289d02013-09-23 12:02:46 +0000[diff] [blame]2280 unsigned int nOps = N->getNumOperands();
Daniel Sandersab94b532013-10-30 15:20:38 +0000[diff] [blame]2281 assert(nOps > 1 && "isSplatVector has 0 or 1 sized build vector");
Daniel Sanders7a289d02013-09-23 12:02:46 +0000[diff] [blame]2282
2283 SDValue Operand0 = N->getOperand(0);
2284
2285 for (unsigned int i = 1; i < nOps; ++i) {
2286 if (N->getOperand(i) != Operand0)
2287 return false;
2288 }
2289
2290 return true;
2291}
2292
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000[diff] [blame]2293// Lower ISD::EXTRACT_VECTOR_ELT into MipsISD::VEXTRACT_SEXT_ELT.
2294//
2295// The non-value bits resulting from ISD::EXTRACT_VECTOR_ELT are undefined. We
2296// choose to sign-extend but we could have equally chosen zero-extend. The
2297// DAGCombiner will fold any sign/zero extension of the ISD::EXTRACT_VECTOR_ELT
2298// result into this node later (possibly changing it to a zero-extend in the
2299// process).
2300SDValue MipsSETargetLowering::
2301lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
2302 SDLoc DL(Op);
2303 EVT ResTy = Op->getValueType(0);
2304 SDValue Op0 = Op->getOperand(0);
Daniel Sanders39bb8ba2013-09-27 12:17:32 +0000[diff] [blame]2305 EVT VecTy = Op0->getValueType(0);
2306
2307 if (!VecTy.is128BitVector())
2308 return SDValue();
2309
2310 if (ResTy.isInteger()) {
2311 SDValue Op1 = Op->getOperand(1);
2312 EVT EltTy = VecTy.getVectorElementType();
2313 return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1,
2314 DAG.getValueType(EltTy));
2315 }
2316
2317 return Op;
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000[diff] [blame]2318}
2319
Daniel Sandersf49dd822013-09-24 13:33:07 +0000[diff] [blame]2320static bool isConstantOrUndef(const SDValue Op) {
Sanjay Patel57195842016-03-14 17:28:46 +0000[diff] [blame]2321 if (Op->isUndef())
Daniel Sandersf49dd822013-09-24 13:33:07 +0000[diff] [blame]2322 return true;
Vasileios Kalintiris46963f62015-02-13 19:12:16 +0000[diff] [blame]2323 if (isa<ConstantSDNode>(Op))
Daniel Sandersf49dd822013-09-24 13:33:07 +0000[diff] [blame]2324 return true;
Vasileios Kalintiris46963f62015-02-13 19:12:16 +0000[diff] [blame]2325 if (isa<ConstantFPSDNode>(Op))
Daniel Sandersf49dd822013-09-24 13:33:07 +0000[diff] [blame]2326 return true;
2327 return false;
2328}
2329
2330static bool isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op) {
2331 for (unsigned i = 0; i < Op->getNumOperands(); ++i)
2332 if (isConstantOrUndef(Op->getOperand(i)))
2333 return true;
2334 return false;
2335}
2336
Daniel Sanders7a289d02013-09-23 12:02:46 +0000[diff] [blame]2337// Lowers ISD::BUILD_VECTOR into appropriate SelectionDAG nodes for the
2338// backend.
2339//
2340// Lowers according to the following rules:
Daniel Sandersf49dd822013-09-24 13:33:07 +0000[diff] [blame]2341// - Constant splats are legal as-is as long as the SplatBitSize is a power of
2342// 2 less than or equal to 64 and the value fits into a signed 10-bit
2343// immediate
2344// - Constant splats are lowered to bitconverted BUILD_VECTORs if SplatBitSize
2345// is a power of 2 less than or equal to 64 and the value does not fit into a
2346// signed 10-bit immediate
2347// - Non-constant splats are legal as-is.
2348// - Non-constant non-splats are lowered to sequences of INSERT_VECTOR_ELT.
2349// - All others are illegal and must be expanded.
Daniel Sanders7a289d02013-09-23 12:02:46 +0000[diff] [blame]2350SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op,
2351 SelectionDAG &DAG) const {
2352 BuildVectorSDNode *Node = cast<BuildVectorSDNode>(Op);
2353 EVT ResTy = Op->getValueType(0);
2354 SDLoc DL(Op);
2355 APInt SplatValue, SplatUndef;
2356 unsigned SplatBitSize;
2357 bool HasAnyUndefs;
2358
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]2359 if (!Subtarget.hasMSA() || !ResTy.is128BitVector())
Daniel Sanders7a289d02013-09-23 12:02:46 +0000[diff] [blame]2360 return SDValue();
2361
2362 if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
2363 HasAnyUndefs, 8,
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]2364 !Subtarget.isLittle()) && SplatBitSize <= 64) {
Daniel Sandersf49dd822013-09-24 13:33:07 +0000[diff] [blame]2365 // We can only cope with 8, 16, 32, or 64-bit elements
2366 if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 &&
2367 SplatBitSize != 64)
2368 return SDValue();
2369
Simon Dardis7090d142017-03-10 13:27:14 +0000[diff] [blame]2370 // If the value isn't an integer type we will have to bitcast
2371 // from an integer type first. Also, if there are any undefs, we must
2372 // lower them to defined values first.
2373 if (ResTy.isInteger() && !HasAnyUndefs)
Daniel Sandersf49dd822013-09-24 13:33:07 +0000[diff] [blame]2374 return Op;
2375
2376 EVT ViaVecTy;
Daniel Sanders7a289d02013-09-23 12:02:46 +0000[diff] [blame]2377
2378 switch (SplatBitSize) {
2379 default:
2380 return SDValue();
Daniel Sandersf49dd822013-09-24 13:33:07 +0000[diff] [blame]2381 case 8:
2382 ViaVecTy = MVT::v16i8;
Daniel Sanders7a289d02013-09-23 12:02:46 +0000[diff] [blame]2383 break;
2384 case 16:
Daniel Sandersf49dd822013-09-24 13:33:07 +0000[diff] [blame]2385 ViaVecTy = MVT::v8i16;
Daniel Sanders7a289d02013-09-23 12:02:46 +0000[diff] [blame]2386 break;
Daniel Sandersf49dd822013-09-24 13:33:07 +0000[diff] [blame]2387 case 32:
2388 ViaVecTy = MVT::v4i32;
Daniel Sanders7a289d02013-09-23 12:02:46 +0000[diff] [blame]2389 break;
Daniel Sandersf49dd822013-09-24 13:33:07 +0000[diff] [blame]2390 case 64:
2391 // There's no fill.d to fall back on for 64-bit values
2392 return SDValue();
Daniel Sanders7a289d02013-09-23 12:02:46 +0000[diff] [blame]2393 }
2394
Daniel Sanders50b80412013-11-15 12:56:49 +0000[diff] [blame]2395 // SelectionDAG::getConstant will promote SplatValue appropriately.
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]2396 SDValue Result = DAG.getConstant(SplatValue, DL, ViaVecTy);
Daniel Sandersf49dd822013-09-24 13:33:07 +0000[diff] [blame]2397
Daniel Sanders50b80412013-11-15 12:56:49 +0000[diff] [blame]2398 // Bitcast to the type we originally wanted
Daniel Sandersf49dd822013-09-24 13:33:07 +0000[diff] [blame]2399 if (ViaVecTy != ResTy)
2400 Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result);
Daniel Sanders7a289d02013-09-23 12:02:46 +0000[diff] [blame]2401
2402 return Result;
Daniel Sandersf49dd822013-09-24 13:33:07 +0000[diff] [blame]2403 } else if (isSplatVector(Node))
2404 return Op;
2405 else if (!isConstantOrUndefBUILD_VECTOR(Node)) {
Daniel Sandersf86622b2013-09-24 13:16:15 +0000[diff] [blame]2406 // Use INSERT_VECTOR_ELT operations rather than expand to stores.
2407 // The resulting code is the same length as the expansion, but it doesn't
2408 // use memory operations
2409 EVT ResTy = Node->getValueType(0);
2410
2411 assert(ResTy.isVector());
2412
2413 unsigned NumElts = ResTy.getVectorNumElements();
2414 SDValue Vector = DAG.getUNDEF(ResTy);
2415 for (unsigned i = 0; i < NumElts; ++i) {
2416 Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector,
2417 Node->getOperand(i),
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]2418 DAG.getConstant(i, DL, MVT::i32));
Daniel Sandersf86622b2013-09-24 13:16:15 +0000[diff] [blame]2419 }
2420 return Vector;
2421 }
Daniel Sanders7a289d02013-09-23 12:02:46 +0000[diff] [blame]2422
2423 return SDValue();
2424}
2425
Daniel Sanders26307182013-09-24 14:20:00 +0000[diff] [blame]2426// Lower VECTOR_SHUFFLE into SHF (if possible).
2427//
2428// SHF splits the vector into blocks of four elements, then shuffles these
2429// elements according to a <4 x i2> constant (encoded as an integer immediate).
2430//
2431// It is therefore possible to lower into SHF when the mask takes the form:
2432// <a, b, c, d, a+4, b+4, c+4, d+4, a+8, b+8, c+8, d+8, ...>
2433// When undef's appear they are treated as if they were whatever value is
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2434// necessary in order to fit the above forms.
Daniel Sanders26307182013-09-24 14:20:00 +0000[diff] [blame]2435//
2436// For example:
2437// %2 = shufflevector <8 x i16> %0, <8 x i16> undef,
2438// <8 x i32> <i32 3, i32 2, i32 1, i32 0,
2439// i32 7, i32 6, i32 5, i32 4>
2440// is lowered to:
2441// (SHF_H $w0, $w1, 27)
2442// where the 27 comes from:
2443// 3 + (2 << 2) + (1 << 4) + (0 << 6)
2444static SDValue lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy,
2445 SmallVector<int, 16> Indices,
2446 SelectionDAG &DAG) {
2447 int SHFIndices[4] = { -1, -1, -1, -1 };
2448
2449 if (Indices.size() < 4)
2450 return SDValue();
2451
2452 for (unsigned i = 0; i < 4; ++i) {
2453 for (unsigned j = i; j < Indices.size(); j += 4) {
2454 int Idx = Indices[j];
2455
2456 // Convert from vector index to 4-element subvector index
2457 // If an index refers to an element outside of the subvector then give up
2458 if (Idx != -1) {
2459 Idx -= 4 * (j / 4);
2460 if (Idx < 0 || Idx >= 4)
2461 return SDValue();
2462 }
2463
2464 // If the mask has an undef, replace it with the current index.
2465 // Note that it might still be undef if the current index is also undef
2466 if (SHFIndices[i] == -1)
2467 SHFIndices[i] = Idx;
2468
2469 // Check that non-undef values are the same as in the mask. If they
2470 // aren't then give up
2471 if (!(Idx == -1 || Idx == SHFIndices[i]))
2472 return SDValue();
2473 }
2474 }
2475
2476 // Calculate the immediate. Replace any remaining undefs with zero
2477 APInt Imm(32, 0);
2478 for (int i = 3; i >= 0; --i) {
2479 int Idx = SHFIndices[i];
2480
2481 if (Idx == -1)
2482 Idx = 0;
2483
2484 Imm <<= 2;
2485 Imm |= Idx & 0x3;
2486 }
2487
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]2488 SDLoc DL(Op);
2489 return DAG.getNode(MipsISD::SHF, DL, ResTy,
2490 DAG.getConstant(Imm, DL, MVT::i32), Op->getOperand(0));
Daniel Sanders26307182013-09-24 14:20:00 +0000[diff] [blame]2491}
2492
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2493/// Determine whether a range fits a regular pattern of values.
2494/// This function accounts for the possibility of jumping over the End iterator.
2495template <typename ValType>
2496static bool
2497fitsRegularPattern(typename SmallVectorImpl<ValType>::const_iterator Begin,
2498 unsigned CheckStride,
2499 typename SmallVectorImpl<ValType>::const_iterator End,
2500 ValType ExpectedIndex, unsigned ExpectedIndexStride) {
2501 auto &I = Begin;
2502
2503 while (I != End) {
2504 if (*I != -1 && *I != ExpectedIndex)
2505 return false;
2506 ExpectedIndex += ExpectedIndexStride;
2507
2508 // Incrementing past End is undefined behaviour so we must increment one
2509 // step at a time and check for End at each step.
2510 for (unsigned n = 0; n < CheckStride && I != End; ++n, ++I)
2511 ; // Empty loop body.
2512 }
2513 return true;
2514}
2515
2516// Determine whether VECTOR_SHUFFLE is a SPLATI.
2517//
2518// It is a SPLATI when the mask is:
2519// <x, x, x, ...>
2520// where x is any valid index.
2521//
2522// When undef's appear in the mask they are treated as if they were whatever
2523// value is necessary in order to fit the above form.
2524static bool isVECTOR_SHUFFLE_SPLATI(SDValue Op, EVT ResTy,
2525 SmallVector<int, 16> Indices,
2526 SelectionDAG &DAG) {
2527 assert((Indices.size() % 2) == 0);
2528
2529 int SplatIndex = -1;
2530 for (const auto &V : Indices) {
2531 if (V != -1) {
2532 SplatIndex = V;
2533 break;
2534 }
2535 }
2536
2537 return fitsRegularPattern<int>(Indices.begin(), 1, Indices.end(), SplatIndex,
2538 0);
2539}
2540
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2541// Lower VECTOR_SHUFFLE into ILVEV (if possible).
2542//
2543// ILVEV interleaves the even elements from each vector.
2544//
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2545// It is possible to lower into ILVEV when the mask consists of two of the
2546// following forms interleaved:
2547// <0, 2, 4, ...>
2548// <n, n+2, n+4, ...>
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2549// where n is the number of elements in the vector.
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2550// For example:
2551// <0, 0, 2, 2, 4, 4, ...>
2552// <0, n, 2, n+2, 4, n+4, ...>
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2553//
2554// When undef's appear in the mask they are treated as if they were whatever
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2555// value is necessary in order to fit the above forms.
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2556static SDValue lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy,
2557 SmallVector<int, 16> Indices,
2558 SelectionDAG &DAG) {
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2559 assert((Indices.size() % 2) == 0);
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2560
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2561 SDValue Wt;
2562 SDValue Ws;
2563 const auto &Begin = Indices.begin();
2564 const auto &End = Indices.end();
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2565
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2566 // Check even elements are taken from the even elements of one half or the
2567 // other and pick an operand accordingly.
2568 if (fitsRegularPattern<int>(Begin, 2, End, 0, 2))
2569 Wt = Op->getOperand(0);
2570 else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size(), 2))
2571 Wt = Op->getOperand(1);
2572 else
2573 return SDValue();
2574
2575 // Check odd elements are taken from the even elements of one half or the
2576 // other and pick an operand accordingly.
2577 if (fitsRegularPattern<int>(Begin + 1, 2, End, 0, 2))
2578 Ws = Op->getOperand(0);
2579 else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size(), 2))
2580 Ws = Op->getOperand(1);
2581 else
2582 return SDValue();
2583
2584 return DAG.getNode(MipsISD::ILVEV, SDLoc(Op), ResTy, Ws, Wt);
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2585}
2586
2587// Lower VECTOR_SHUFFLE into ILVOD (if possible).
2588//
2589// ILVOD interleaves the odd elements from each vector.
2590//
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2591// It is possible to lower into ILVOD when the mask consists of two of the
2592// following forms interleaved:
2593// <1, 3, 5, ...>
2594// <n+1, n+3, n+5, ...>
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2595// where n is the number of elements in the vector.
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2596// For example:
2597// <1, 1, 3, 3, 5, 5, ...>
2598// <1, n+1, 3, n+3, 5, n+5, ...>
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2599//
2600// When undef's appear in the mask they are treated as if they were whatever
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2601// value is necessary in order to fit the above forms.
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2602static SDValue lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy,
2603 SmallVector<int, 16> Indices,
2604 SelectionDAG &DAG) {
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2605 assert((Indices.size() % 2) == 0);
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2606
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2607 SDValue Wt;
2608 SDValue Ws;
2609 const auto &Begin = Indices.begin();
2610 const auto &End = Indices.end();
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2611
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2612 // Check even elements are taken from the odd elements of one half or the
2613 // other and pick an operand accordingly.
2614 if (fitsRegularPattern<int>(Begin, 2, End, 1, 2))
2615 Wt = Op->getOperand(0);
2616 else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size() + 1, 2))
2617 Wt = Op->getOperand(1);
2618 else
2619 return SDValue();
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2620
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2621 // Check odd elements are taken from the odd elements of one half or the
2622 // other and pick an operand accordingly.
2623 if (fitsRegularPattern<int>(Begin + 1, 2, End, 1, 2))
2624 Ws = Op->getOperand(0);
2625 else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size() + 1, 2))
2626 Ws = Op->getOperand(1);
2627 else
2628 return SDValue();
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2629
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2630 return DAG.getNode(MipsISD::ILVOD, SDLoc(Op), ResTy, Wt, Ws);
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2631}
2632
2633// Lower VECTOR_SHUFFLE into ILVR (if possible).
2634//
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2635// ILVR interleaves consecutive elements from the right (lowest-indexed) half of
2636// each vector.
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2637//
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2638// It is possible to lower into ILVR when the mask consists of two of the
2639// following forms interleaved:
2640// <0, 1, 2, ...>
2641// <n, n+1, n+2, ...>
2642// where n is the number of elements in the vector.
2643// For example:
2644// <0, 0, 1, 1, 2, 2, ...>
2645// <0, n, 1, n+1, 2, n+2, ...>
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2646//
2647// When undef's appear in the mask they are treated as if they were whatever
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2648// value is necessary in order to fit the above forms.
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2649static SDValue lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy,
2650 SmallVector<int, 16> Indices,
2651 SelectionDAG &DAG) {
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2652 assert((Indices.size() % 2) == 0);
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2653
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2654 SDValue Wt;
2655 SDValue Ws;
2656 const auto &Begin = Indices.begin();
2657 const auto &End = Indices.end();
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2658
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2659 // Check even elements are taken from the right (lowest-indexed) elements of
2660 // one half or the other and pick an operand accordingly.
2661 if (fitsRegularPattern<int>(Begin, 2, End, 0, 1))
2662 Wt = Op->getOperand(0);
2663 else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size(), 1))
2664 Wt = Op->getOperand(1);
2665 else
2666 return SDValue();
2667
2668 // Check odd elements are taken from the right (lowest-indexed) elements of
2669 // one half or the other and pick an operand accordingly.
2670 if (fitsRegularPattern<int>(Begin + 1, 2, End, 0, 1))
2671 Ws = Op->getOperand(0);
2672 else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size(), 1))
2673 Ws = Op->getOperand(1);
2674 else
2675 return SDValue();
2676
2677 return DAG.getNode(MipsISD::ILVR, SDLoc(Op), ResTy, Ws, Wt);
2678}
2679
2680// Lower VECTOR_SHUFFLE into ILVL (if possible).
2681//
2682// ILVL interleaves consecutive elements from the left (highest-indexed) half
2683// of each vector.
2684//
2685// It is possible to lower into ILVL when the mask consists of two of the
2686// following forms interleaved:
2687// <x, x+1, x+2, ...>
2688// <n+x, n+x+1, n+x+2, ...>
2689// where n is the number of elements in the vector and x is half n.
2690// For example:
2691// <x, x, x+1, x+1, x+2, x+2, ...>
2692// <x, n+x, x+1, n+x+1, x+2, n+x+2, ...>
2693//
2694// When undef's appear in the mask they are treated as if they were whatever
2695// value is necessary in order to fit the above forms.
2696static SDValue lowerVECTOR_SHUFFLE_ILVL(SDValue Op, EVT ResTy,
2697 SmallVector<int, 16> Indices,
2698 SelectionDAG &DAG) {
2699 assert((Indices.size() % 2) == 0);
2700
2701 unsigned HalfSize = Indices.size() / 2;
2702 SDValue Wt;
2703 SDValue Ws;
2704 const auto &Begin = Indices.begin();
2705 const auto &End = Indices.end();
2706
2707 // Check even elements are taken from the left (highest-indexed) elements of
2708 // one half or the other and pick an operand accordingly.
2709 if (fitsRegularPattern<int>(Begin, 2, End, HalfSize, 1))
2710 Wt = Op->getOperand(0);
2711 else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size() + HalfSize, 1))
2712 Wt = Op->getOperand(1);
2713 else
2714 return SDValue();
2715
2716 // Check odd elements are taken from the left (highest-indexed) elements of
2717 // one half or the other and pick an operand accordingly.
2718 if (fitsRegularPattern<int>(Begin + 1, 2, End, HalfSize, 1))
2719 Ws = Op->getOperand(0);
2720 else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size() + HalfSize,
2721 1))
2722 Ws = Op->getOperand(1);
2723 else
2724 return SDValue();
2725
2726 return DAG.getNode(MipsISD::ILVL, SDLoc(Op), ResTy, Ws, Wt);
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2727}
2728
Daniel Sandersfae5f2a2013-09-24 14:53:25 +0000[diff] [blame]2729// Lower VECTOR_SHUFFLE into PCKEV (if possible).
2730//
2731// PCKEV copies the even elements of each vector into the result vector.
2732//
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2733// It is possible to lower into PCKEV when the mask consists of two of the
2734// following forms concatenated:
2735// <0, 2, 4, ...>
2736// <n, n+2, n+4, ...>
Daniel Sandersfae5f2a2013-09-24 14:53:25 +0000[diff] [blame]2737// where n is the number of elements in the vector.
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2738// For example:
2739// <0, 2, 4, ..., 0, 2, 4, ...>
2740// <0, 2, 4, ..., n, n+2, n+4, ...>
Daniel Sandersfae5f2a2013-09-24 14:53:25 +0000[diff] [blame]2741//
2742// When undef's appear in the mask they are treated as if they were whatever
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2743// value is necessary in order to fit the above forms.
Daniel Sandersfae5f2a2013-09-24 14:53:25 +0000[diff] [blame]2744static SDValue lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy,
2745 SmallVector<int, 16> Indices,
2746 SelectionDAG &DAG) {
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2747 assert((Indices.size() % 2) == 0);
Daniel Sandersfae5f2a2013-09-24 14:53:25 +0000[diff] [blame]2748
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2749 SDValue Wt;
2750 SDValue Ws;
2751 const auto &Begin = Indices.begin();
2752 const auto &Mid = Indices.begin() + Indices.size() / 2;
2753 const auto &End = Indices.end();
Daniel Sandersfae5f2a2013-09-24 14:53:25 +0000[diff] [blame]2754
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2755 if (fitsRegularPattern<int>(Begin, 1, Mid, 0, 2))
2756 Wt = Op->getOperand(0);
2757 else if (fitsRegularPattern<int>(Begin, 1, Mid, Indices.size(), 2))
2758 Wt = Op->getOperand(1);
2759 else
2760 return SDValue();
2761
2762 if (fitsRegularPattern<int>(Mid, 1, End, 0, 2))
2763 Ws = Op->getOperand(0);
2764 else if (fitsRegularPattern<int>(Mid, 1, End, Indices.size(), 2))
2765 Ws = Op->getOperand(1);
2766 else
2767 return SDValue();
2768
2769 return DAG.getNode(MipsISD::PCKEV, SDLoc(Op), ResTy, Ws, Wt);
Daniel Sandersfae5f2a2013-09-24 14:53:25 +0000[diff] [blame]2770}
2771
2772// Lower VECTOR_SHUFFLE into PCKOD (if possible).
2773//
2774// PCKOD copies the odd elements of each vector into the result vector.
2775//
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2776// It is possible to lower into PCKOD when the mask consists of two of the
2777// following forms concatenated:
2778// <1, 3, 5, ...>
2779// <n+1, n+3, n+5, ...>
Daniel Sandersfae5f2a2013-09-24 14:53:25 +0000[diff] [blame]2780// where n is the number of elements in the vector.
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2781// For example:
2782// <1, 3, 5, ..., 1, 3, 5, ...>
2783// <1, 3, 5, ..., n+1, n+3, n+5, ...>
Daniel Sandersfae5f2a2013-09-24 14:53:25 +0000[diff] [blame]2784//
2785// When undef's appear in the mask they are treated as if they were whatever
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2786// value is necessary in order to fit the above forms.
Daniel Sandersfae5f2a2013-09-24 14:53:25 +0000[diff] [blame]2787static SDValue lowerVECTOR_SHUFFLE_PCKOD(SDValue Op, EVT ResTy,
2788 SmallVector<int, 16> Indices,
2789 SelectionDAG &DAG) {
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2790 assert((Indices.size() % 2) == 0);
Daniel Sandersfae5f2a2013-09-24 14:53:25 +0000[diff] [blame]2791
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2792 SDValue Wt;
2793 SDValue Ws;
2794 const auto &Begin = Indices.begin();
2795 const auto &Mid = Indices.begin() + Indices.size() / 2;
2796 const auto &End = Indices.end();
Daniel Sandersfae5f2a2013-09-24 14:53:25 +0000[diff] [blame]2797
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2798 if (fitsRegularPattern<int>(Begin, 1, Mid, 1, 2))
2799 Wt = Op->getOperand(0);
2800 else if (fitsRegularPattern<int>(Begin, 1, Mid, Indices.size() + 1, 2))
2801 Wt = Op->getOperand(1);
2802 else
2803 return SDValue();
2804
2805 if (fitsRegularPattern<int>(Mid, 1, End, 1, 2))
2806 Ws = Op->getOperand(0);
2807 else if (fitsRegularPattern<int>(Mid, 1, End, Indices.size() + 1, 2))
2808 Ws = Op->getOperand(1);
2809 else
2810 return SDValue();
2811
2812 return DAG.getNode(MipsISD::PCKOD, SDLoc(Op), ResTy, Ws, Wt);
Daniel Sandersfae5f2a2013-09-24 14:53:25 +0000[diff] [blame]2813}
2814
Daniel Sanderse5087042013-09-24 14:02:15 +0000[diff] [blame]2815// Lower VECTOR_SHUFFLE into VSHF.
2816//
2817// This mostly consists of converting the shuffle indices in Indices into a
2818// BUILD_VECTOR and adding it as an operand to the resulting VSHF. There is
2819// also code to eliminate unused operands of the VECTOR_SHUFFLE. For example,
2820// if the type is v8i16 and all the indices are less than 8 then the second
2821// operand is unused and can be replaced with anything. We choose to replace it
2822// with the used operand since this reduces the number of instructions overall.
2823static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy,
2824 SmallVector<int, 16> Indices,
2825 SelectionDAG &DAG) {
2826 SmallVector<SDValue, 16> Ops;
2827 SDValue Op0;
2828 SDValue Op1;
2829 EVT MaskVecTy = ResTy.changeVectorElementTypeToInteger();
2830 EVT MaskEltTy = MaskVecTy.getVectorElementType();
2831 bool Using1stVec = false;
2832 bool Using2ndVec = false;
2833 SDLoc DL(Op);
2834 int ResTyNumElts = ResTy.getVectorNumElements();
2835
2836 for (int i = 0; i < ResTyNumElts; ++i) {
2837 // Idx == -1 means UNDEF
2838 int Idx = Indices[i];
2839
2840 if (0 <= Idx && Idx < ResTyNumElts)
2841 Using1stVec = true;
2842 if (ResTyNumElts <= Idx && Idx < ResTyNumElts * 2)
2843 Using2ndVec = true;
2844 }
2845
2846 for (SmallVector<int, 16>::iterator I = Indices.begin(); I != Indices.end();
2847 ++I)
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]2848 Ops.push_back(DAG.getTargetConstant(*I, DL, MaskEltTy));
Daniel Sanderse5087042013-09-24 14:02:15 +0000[diff] [blame]2849
Ahmed Bougacha128f8732016-04-26 21:15:30 +0000[diff] [blame]2850 SDValue MaskVec = DAG.getBuildVector(MaskVecTy, DL, Ops);
Daniel Sanderse5087042013-09-24 14:02:15 +0000[diff] [blame]2851
2852 if (Using1stVec && Using2ndVec) {
2853 Op0 = Op->getOperand(0);
2854 Op1 = Op->getOperand(1);
2855 } else if (Using1stVec)
2856 Op0 = Op1 = Op->getOperand(0);
2857 else if (Using2ndVec)
2858 Op0 = Op1 = Op->getOperand(1);
2859 else
2860 llvm_unreachable("shuffle vector mask references neither vector operand?");
2861
Daniel Sandersf88a29e2014-03-21 16:56:51 +0000[diff] [blame]2862 // VECTOR_SHUFFLE concatenates the vectors in an vectorwise fashion.
2863 // <0b00, 0b01> + <0b10, 0b11> -> <0b00, 0b01, 0b10, 0b11>
2864 // VSHF concatenates the vectors in a bitwise fashion:
2865 // <0b00, 0b01> + <0b10, 0b11> ->
2866 // 0b0100 + 0b1110 -> 0b01001110
2867 // <0b10, 0b11, 0b00, 0b01>
2868 // We must therefore swap the operands to get the correct result.
2869 return DAG.getNode(MipsISD::VSHF, DL, ResTy, MaskVec, Op1, Op0);
Daniel Sanderse5087042013-09-24 14:02:15 +0000[diff] [blame]2870}
2871
2872// Lower VECTOR_SHUFFLE into one of a number of instructions depending on the
2873// indices in the shuffle.
2874SDValue MipsSETargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
2875 SelectionDAG &DAG) const {
2876 ShuffleVectorSDNode *Node = cast<ShuffleVectorSDNode>(Op);
2877 EVT ResTy = Op->getValueType(0);
2878
2879 if (!ResTy.is128BitVector())
2880 return SDValue();
2881
2882 int ResTyNumElts = ResTy.getVectorNumElements();
2883 SmallVector<int, 16> Indices;
2884
2885 for (int i = 0; i < ResTyNumElts; ++i)
2886 Indices.push_back(Node->getMaskElt(i));
2887
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2888 // splati.[bhwd] is preferable to the others but is matched from
2889 // MipsISD::VSHF.
2890 if (isVECTOR_SHUFFLE_SPLATI(Op, ResTy, Indices, DAG))
2891 return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG);
Ahmed Bougachaf8dfb472016-02-09 22:54:12 +0000[diff] [blame]2892 SDValue Result;
2893 if ((Result = lowerVECTOR_SHUFFLE_ILVEV(Op, ResTy, Indices, DAG)))
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2894 return Result;
Ahmed Bougachaf8dfb472016-02-09 22:54:12 +0000[diff] [blame]2895 if ((Result = lowerVECTOR_SHUFFLE_ILVOD(Op, ResTy, Indices, DAG)))
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2896 return Result;
Ahmed Bougachaf8dfb472016-02-09 22:54:12 +0000[diff] [blame]2897 if ((Result = lowerVECTOR_SHUFFLE_ILVL(Op, ResTy, Indices, DAG)))
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2898 return Result;
Ahmed Bougachaf8dfb472016-02-09 22:54:12 +0000[diff] [blame]2899 if ((Result = lowerVECTOR_SHUFFLE_ILVR(Op, ResTy, Indices, DAG)))
Daniel Sanders2ed228b2013-09-24 14:36:12 +0000[diff] [blame]2900 return Result;
Ahmed Bougachaf8dfb472016-02-09 22:54:12 +0000[diff] [blame]2901 if ((Result = lowerVECTOR_SHUFFLE_PCKEV(Op, ResTy, Indices, DAG)))
Daniel Sandersfae5f2a2013-09-24 14:53:25 +0000[diff] [blame]2902 return Result;
Ahmed Bougachaf8dfb472016-02-09 22:54:12 +0000[diff] [blame]2903 if ((Result = lowerVECTOR_SHUFFLE_PCKOD(Op, ResTy, Indices, DAG)))
Daniel Sandersfae5f2a2013-09-24 14:53:25 +0000[diff] [blame]2904 return Result;
Ahmed Bougachaf8dfb472016-02-09 22:54:12 +0000[diff] [blame]2905 if ((Result = lowerVECTOR_SHUFFLE_SHF(Op, ResTy, Indices, DAG)))
Daniel Sandersc8cd58f2015-05-19 12:24:52 +0000[diff] [blame]2906 return Result;
Daniel Sanderse5087042013-09-24 14:02:15 +0000[diff] [blame]2907 return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG);
2908}
2909
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]2910MachineBasicBlock *
2911MipsSETargetLowering::emitBPOSGE32(MachineInstr &MI,
2912 MachineBasicBlock *BB) const {
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]2913 // $bb:
2914 // bposge32_pseudo $vr0
2915 // =>
2916 // $bb:
2917 // bposge32 $tbb
2918 // $fbb:
2919 // li $vr2, 0
2920 // b $sink
2921 // $tbb:
2922 // li $vr1, 1
2923 // $sink:
2924 // $vr0 = phi($vr2, $fbb, $vr1, $tbb)
2925
2926 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
Eric Christopher96e72c62015-01-29 23:27:36 +0000[diff] [blame]2927 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
Akira Hatanaka13e6ccf2013-08-06 23:08:38 +0000[diff] [blame]2928 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]2929 DebugLoc DL = MI.getDebugLoc();
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]2930 const BasicBlock *LLVM_BB = BB->getBasicBlock();
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +0000[diff] [blame]2931 MachineFunction::iterator It = std::next(MachineFunction::iterator(BB));
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]2932 MachineFunction *F = BB->getParent();
2933 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
2934 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
2935 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
2936 F->insert(It, FBB);
2937 F->insert(It, TBB);
2938 F->insert(It, Sink);
2939
2940 // Transfer the remainder of BB and its successor edges to Sink.
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +0000[diff] [blame]2941 Sink->splice(Sink->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]2942 BB->end());
2943 Sink->transferSuccessorsAndUpdatePHIs(BB);
2944
2945 // Add successors.
2946 BB->addSuccessor(FBB);
2947 BB->addSuccessor(TBB);
2948 FBB->addSuccessor(Sink);
2949 TBB->addSuccessor(Sink);
2950
2951 // Insert the real bposge32 instruction to $BB.
2952 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
Hrvoje Varga6f09cdf2016-05-13 11:32:53 +0000[diff] [blame]2953 // Insert the real bposge32c instruction to $BB.
2954 BuildMI(BB, DL, TII->get(Mips::BPOSGE32C_MMR3)).addMBB(TBB);
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]2955
2956 // Fill $FBB.
2957 unsigned VR2 = RegInfo.createVirtualRegister(RC);
2958 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
2959 .addReg(Mips::ZERO).addImm(0);
2960 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
2961
2962 // Fill $TBB.
2963 unsigned VR1 = RegInfo.createVirtualRegister(RC);
2964 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
2965 .addReg(Mips::ZERO).addImm(1);
2966
2967 // Insert phi function to $Sink.
2968 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]2969 MI.getOperand(0).getReg())
2970 .addReg(VR2)
2971 .addMBB(FBB)
2972 .addReg(VR1)
2973 .addMBB(TBB);
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]2974
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]2975 MI.eraseFromParent(); // The pseudo instruction is gone now.
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000[diff] [blame]2976 return Sink;
2977}
Daniel Sandersce09d072013-08-28 12:14:50 +0000[diff] [blame]2978
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]2979MachineBasicBlock *MipsSETargetLowering::emitMSACBranchPseudo(
2980 MachineInstr &MI, MachineBasicBlock *BB, unsigned BranchOp) const {
Daniel Sandersce09d072013-08-28 12:14:50 +0000[diff] [blame]2981 // $bb:
2982 // vany_nonzero $rd, $ws
2983 // =>
2984 // $bb:
2985 // bnz.b $ws, $tbb
2986 // b $fbb
2987 // $fbb:
2988 // li $rd1, 0
2989 // b $sink
2990 // $tbb:
2991 // li $rd2, 1
2992 // $sink:
2993 // $rd = phi($rd1, $fbb, $rd2, $tbb)
2994
2995 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
Eric Christopher96e72c62015-01-29 23:27:36 +0000[diff] [blame]2996 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
Daniel Sandersce09d072013-08-28 12:14:50 +0000[diff] [blame]2997 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]2998 DebugLoc DL = MI.getDebugLoc();
Daniel Sandersce09d072013-08-28 12:14:50 +0000[diff] [blame]2999 const BasicBlock *LLVM_BB = BB->getBasicBlock();
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +0000[diff] [blame]3000 MachineFunction::iterator It = std::next(MachineFunction::iterator(BB));
Daniel Sandersce09d072013-08-28 12:14:50 +0000[diff] [blame]3001 MachineFunction *F = BB->getParent();
3002 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
3003 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
3004 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
3005 F->insert(It, FBB);
3006 F->insert(It, TBB);
3007 F->insert(It, Sink);
3008
3009 // Transfer the remainder of BB and its successor edges to Sink.
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +0000[diff] [blame]3010 Sink->splice(Sink->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
Daniel Sandersce09d072013-08-28 12:14:50 +0000[diff] [blame]3011 BB->end());
3012 Sink->transferSuccessorsAndUpdatePHIs(BB);
3013
3014 // Add successors.
3015 BB->addSuccessor(FBB);
3016 BB->addSuccessor(TBB);
3017 FBB->addSuccessor(Sink);
3018 TBB->addSuccessor(Sink);
3019
3020 // Insert the real bnz.b instruction to $BB.
3021 BuildMI(BB, DL, TII->get(BranchOp))
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3022 .addReg(MI.getOperand(1).getReg())
3023 .addMBB(TBB);
Daniel Sandersce09d072013-08-28 12:14:50 +0000[diff] [blame]3024
3025 // Fill $FBB.
3026 unsigned RD1 = RegInfo.createVirtualRegister(RC);
3027 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
3028 .addReg(Mips::ZERO).addImm(0);
3029 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
3030
3031 // Fill $TBB.
3032 unsigned RD2 = RegInfo.createVirtualRegister(RC);
3033 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
3034 .addReg(Mips::ZERO).addImm(1);
3035
3036 // Insert phi function to $Sink.
3037 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3038 MI.getOperand(0).getReg())
3039 .addReg(RD1)
3040 .addMBB(FBB)
3041 .addReg(RD2)
3042 .addMBB(TBB);
Daniel Sandersce09d072013-08-28 12:14:50 +0000[diff] [blame]3043
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3044 MI.eraseFromParent(); // The pseudo instruction is gone now.
Daniel Sandersce09d072013-08-28 12:14:50 +0000[diff] [blame]3045 return Sink;
3046}
Daniel Sanders39bb8ba2013-09-27 12:17:32 +0000[diff] [blame]3047
3048// Emit the COPY_FW pseudo instruction.
3049//
3050// copy_fw_pseudo $fd, $ws, n
3051// =>
3052// copy_u_w $rt, $ws, $n
3053// mtc1 $rt, $fd
3054//
3055// When n is zero, the equivalent operation can be performed with (potentially)
3056// zero instructions due to register overlaps. This optimization is never valid
3057// for lane 1 because it would require FR=0 mode which isn't supported by MSA.
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3058MachineBasicBlock *
3059MipsSETargetLowering::emitCOPY_FW(MachineInstr &MI,
3060 MachineBasicBlock *BB) const {
Eric Christopher96e72c62015-01-29 23:27:36 +0000[diff] [blame]3061 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
Daniel Sanders39bb8ba2013-09-27 12:17:32 +0000[diff] [blame]3062 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3063 DebugLoc DL = MI.getDebugLoc();
3064 unsigned Fd = MI.getOperand(0).getReg();
3065 unsigned Ws = MI.getOperand(1).getReg();
3066 unsigned Lane = MI.getOperand(2).getImm();
Daniel Sanders39bb8ba2013-09-27 12:17:32 +0000[diff] [blame]3067
Daniel Sandersafe27c72015-02-23 17:22:16 +0000[diff] [blame]3068 if (Lane == 0) {
3069 unsigned Wt = Ws;
3070 if (!Subtarget.useOddSPReg()) {
3071 // We must copy to an even-numbered MSA register so that the
3072 // single-precision sub-register is also guaranteed to be even-numbered.
3073 Wt = RegInfo.createVirtualRegister(&Mips::MSA128WEvensRegClass);
3074
3075 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Wt).addReg(Ws);
3076 }
3077
3078 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
3079 } else {
3080 unsigned Wt = RegInfo.createVirtualRegister(
3081 Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass :
3082 &Mips::MSA128WEvensRegClass);
Daniel Sanders39bb8ba2013-09-27 12:17:32 +0000[diff] [blame]3083
Daniel Sandersd9207702014-03-04 13:54:30 +0000[diff] [blame]3084 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(Lane);
Daniel Sanders39bb8ba2013-09-27 12:17:32 +0000[diff] [blame]3085 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
3086 }
3087
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3088 MI.eraseFromParent(); // The pseudo instruction is gone now.
Daniel Sanders39bb8ba2013-09-27 12:17:32 +0000[diff] [blame]3089 return BB;
3090}
3091
3092// Emit the COPY_FD pseudo instruction.
3093//
3094// copy_fd_pseudo $fd, $ws, n
3095// =>
3096// splati.d $wt, $ws, $n
3097// copy $fd, $wt:sub_64
3098//
3099// When n is zero, the equivalent operation can be performed with (potentially)
3100// zero instructions due to register overlaps. This optimization is always
3101// valid because FR=1 mode which is the only supported mode in MSA.
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3102MachineBasicBlock *
3103MipsSETargetLowering::emitCOPY_FD(MachineInstr &MI,
3104 MachineBasicBlock *BB) const {
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]3105 assert(Subtarget.isFP64bit());
Daniel Sanders39bb8ba2013-09-27 12:17:32 +0000[diff] [blame]3106
Eric Christopher96e72c62015-01-29 23:27:36 +0000[diff] [blame]3107 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
Daniel Sanders39bb8ba2013-09-27 12:17:32 +0000[diff] [blame]3108 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3109 unsigned Fd = MI.getOperand(0).getReg();
3110 unsigned Ws = MI.getOperand(1).getReg();
3111 unsigned Lane = MI.getOperand(2).getImm() * 2;
3112 DebugLoc DL = MI.getDebugLoc();
Daniel Sanders39bb8ba2013-09-27 12:17:32 +0000[diff] [blame]3113
3114 if (Lane == 0)
3115 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_64);
3116 else {
3117 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3118
3119 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wt).addReg(Ws).addImm(1);
3120 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_64);
3121 }
3122
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3123 MI.eraseFromParent(); // The pseudo instruction is gone now.
Daniel Sanders39bb8ba2013-09-27 12:17:32 +0000[diff] [blame]3124 return BB;
3125}
Daniel Sandersa5150702013-09-27 12:31:32 +0000[diff] [blame]3126
3127// Emit the INSERT_FW pseudo instruction.
3128//
3129// insert_fw_pseudo $wd, $wd_in, $n, $fs
3130// =>
3131// subreg_to_reg $wt:sub_lo, $fs
3132// insve_w $wd[$n], $wd_in, $wt[0]
Daniel Sanders1dfddc72013-10-15 13:14:41 +0000[diff] [blame]3133MachineBasicBlock *
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3134MipsSETargetLowering::emitINSERT_FW(MachineInstr &MI,
Daniel Sanders1dfddc72013-10-15 13:14:41 +0000[diff] [blame]3135 MachineBasicBlock *BB) const {
Eric Christopher96e72c62015-01-29 23:27:36 +0000[diff] [blame]3136 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
Daniel Sandersa5150702013-09-27 12:31:32 +0000[diff] [blame]3137 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3138 DebugLoc DL = MI.getDebugLoc();
3139 unsigned Wd = MI.getOperand(0).getReg();
3140 unsigned Wd_in = MI.getOperand(1).getReg();
3141 unsigned Lane = MI.getOperand(2).getImm();
3142 unsigned Fs = MI.getOperand(3).getReg();
Daniel Sandersafe27c72015-02-23 17:22:16 +0000[diff] [blame]3143 unsigned Wt = RegInfo.createVirtualRegister(
3144 Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass :
3145 &Mips::MSA128WEvensRegClass);
Daniel Sandersa5150702013-09-27 12:31:32 +0000[diff] [blame]3146
3147 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
Daniel Sanders1dfddc72013-10-15 13:14:41 +0000[diff] [blame]3148 .addImm(0)
3149 .addReg(Fs)
3150 .addImm(Mips::sub_lo);
Daniel Sandersa5150702013-09-27 12:31:32 +0000[diff] [blame]3151 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_W), Wd)
Daniel Sanders1dfddc72013-10-15 13:14:41 +0000[diff] [blame]3152 .addReg(Wd_in)
3153 .addImm(Lane)
Daniel Sandersb50ccf82014-04-01 10:35:28 +0000[diff] [blame]3154 .addReg(Wt)
3155 .addImm(0);
Daniel Sandersa5150702013-09-27 12:31:32 +0000[diff] [blame]3156
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3157 MI.eraseFromParent(); // The pseudo instruction is gone now.
Daniel Sandersa5150702013-09-27 12:31:32 +0000[diff] [blame]3158 return BB;
3159}
3160
3161// Emit the INSERT_FD pseudo instruction.
3162//
3163// insert_fd_pseudo $wd, $fs, n
3164// =>
3165// subreg_to_reg $wt:sub_64, $fs
3166// insve_d $wd[$n], $wd_in, $wt[0]
Daniel Sanders1dfddc72013-10-15 13:14:41 +0000[diff] [blame]3167MachineBasicBlock *
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3168MipsSETargetLowering::emitINSERT_FD(MachineInstr &MI,
Daniel Sanders1dfddc72013-10-15 13:14:41 +0000[diff] [blame]3169 MachineBasicBlock *BB) const {
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]3170 assert(Subtarget.isFP64bit());
Daniel Sandersa5150702013-09-27 12:31:32 +0000[diff] [blame]3171
Eric Christopher96e72c62015-01-29 23:27:36 +0000[diff] [blame]3172 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
Daniel Sandersa5150702013-09-27 12:31:32 +0000[diff] [blame]3173 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3174 DebugLoc DL = MI.getDebugLoc();
3175 unsigned Wd = MI.getOperand(0).getReg();
3176 unsigned Wd_in = MI.getOperand(1).getReg();
3177 unsigned Lane = MI.getOperand(2).getImm();
3178 unsigned Fs = MI.getOperand(3).getReg();
Daniel Sandersa5150702013-09-27 12:31:32 +0000[diff] [blame]3179 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3180
3181 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
Daniel Sanders1dfddc72013-10-15 13:14:41 +0000[diff] [blame]3182 .addImm(0)
3183 .addReg(Fs)
3184 .addImm(Mips::sub_64);
Daniel Sandersa5150702013-09-27 12:31:32 +0000[diff] [blame]3185 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_D), Wd)
Daniel Sanders1dfddc72013-10-15 13:14:41 +0000[diff] [blame]3186 .addReg(Wd_in)
3187 .addImm(Lane)
Daniel Sandersb50ccf82014-04-01 10:35:28 +0000[diff] [blame]3188 .addReg(Wt)
3189 .addImm(0);
Daniel Sanders1dfddc72013-10-15 13:14:41 +0000[diff] [blame]3190
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3191 MI.eraseFromParent(); // The pseudo instruction is gone now.
Daniel Sanders1dfddc72013-10-15 13:14:41 +0000[diff] [blame]3192 return BB;
3193}
3194
Daniel Sanderse296a0f2014-04-30 12:09:32 +0000[diff] [blame]3195// Emit the INSERT_([BHWD]|F[WD])_VIDX pseudo instruction.
3196//
3197// For integer:
3198// (INSERT_([BHWD]|F[WD])_PSEUDO $wd, $wd_in, $n, $rs)
3199// =>
3200// (SLL $lanetmp1, $lane, <log2size)
3201// (SLD_B $wdtmp1, $wd_in, $wd_in, $lanetmp1)
3202// (INSERT_[BHWD], $wdtmp2, $wdtmp1, 0, $rs)
3203// (NEG $lanetmp2, $lanetmp1)
3204// (SLD_B $wd, $wdtmp2, $wdtmp2, $lanetmp2)
3205//
3206// For floating point:
3207// (INSERT_([BHWD]|F[WD])_PSEUDO $wd, $wd_in, $n, $fs)
3208// =>
3209// (SUBREG_TO_REG $wt, $fs, <subreg>)
3210// (SLL $lanetmp1, $lane, <log2size)
3211// (SLD_B $wdtmp1, $wd_in, $wd_in, $lanetmp1)
3212// (INSVE_[WD], $wdtmp2, 0, $wdtmp1, 0)
3213// (NEG $lanetmp2, $lanetmp1)
3214// (SLD_B $wd, $wdtmp2, $wdtmp2, $lanetmp2)
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3215MachineBasicBlock *MipsSETargetLowering::emitINSERT_DF_VIDX(
3216 MachineInstr &MI, MachineBasicBlock *BB, unsigned EltSizeInBytes,
3217 bool IsFP) const {
Eric Christopher96e72c62015-01-29 23:27:36 +0000[diff] [blame]3218 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
Daniel Sanderse296a0f2014-04-30 12:09:32 +0000[diff] [blame]3219 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3220 DebugLoc DL = MI.getDebugLoc();
3221 unsigned Wd = MI.getOperand(0).getReg();
3222 unsigned SrcVecReg = MI.getOperand(1).getReg();
3223 unsigned LaneReg = MI.getOperand(2).getReg();
3224 unsigned SrcValReg = MI.getOperand(3).getReg();
Daniel Sanderse296a0f2014-04-30 12:09:32 +0000[diff] [blame]3225
3226 const TargetRegisterClass *VecRC = nullptr;
Daniel Sandersd3bb2082016-06-15 08:43:23 +0000[diff] [blame]3227 // FIXME: This should be true for N32 too.
Eric Christopherbf33a3c2014-07-02 23:18:40 +0000[diff] [blame]3228 const TargetRegisterClass *GPRRC =
Daniel Sanders4160c802015-05-05 08:48:35 +0000[diff] [blame]3229 Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
Daniel Sandersd3bb2082016-06-15 08:43:23 +0000[diff] [blame]3230 unsigned SubRegIdx = Subtarget.isABI_N64() ? Mips::sub_32 : 0;
3231 unsigned ShiftOp = Subtarget.isABI_N64() ? Mips::DSLL : Mips::SLL;
Daniel Sanderse296a0f2014-04-30 12:09:32 +0000[diff] [blame]3232 unsigned EltLog2Size;
3233 unsigned InsertOp = 0;
3234 unsigned InsveOp = 0;
3235 switch (EltSizeInBytes) {
3236 default:
3237 llvm_unreachable("Unexpected size");
3238 case 1:
3239 EltLog2Size = 0;
3240 InsertOp = Mips::INSERT_B;
3241 InsveOp = Mips::INSVE_B;
3242 VecRC = &Mips::MSA128BRegClass;
3243 break;
3244 case 2:
3245 EltLog2Size = 1;
3246 InsertOp = Mips::INSERT_H;
3247 InsveOp = Mips::INSVE_H;
3248 VecRC = &Mips::MSA128HRegClass;
3249 break;
3250 case 4:
3251 EltLog2Size = 2;
3252 InsertOp = Mips::INSERT_W;
3253 InsveOp = Mips::INSVE_W;
3254 VecRC = &Mips::MSA128WRegClass;
3255 break;
3256 case 8:
3257 EltLog2Size = 3;
3258 InsertOp = Mips::INSERT_D;
3259 InsveOp = Mips::INSVE_D;
3260 VecRC = &Mips::MSA128DRegClass;
3261 break;
3262 }
3263
3264 if (IsFP) {
3265 unsigned Wt = RegInfo.createVirtualRegister(VecRC);
3266 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
3267 .addImm(0)
3268 .addReg(SrcValReg)
3269 .addImm(EltSizeInBytes == 8 ? Mips::sub_64 : Mips::sub_lo);
3270 SrcValReg = Wt;
3271 }
3272
3273 // Convert the lane index into a byte index
3274 if (EltSizeInBytes != 1) {
3275 unsigned LaneTmp1 = RegInfo.createVirtualRegister(GPRRC);
Daniel Sandersd3bb2082016-06-15 08:43:23 +0000[diff] [blame]3276 BuildMI(*BB, MI, DL, TII->get(ShiftOp), LaneTmp1)
Daniel Sanderse296a0f2014-04-30 12:09:32 +0000[diff] [blame]3277 .addReg(LaneReg)
3278 .addImm(EltLog2Size);
3279 LaneReg = LaneTmp1;
3280 }
3281
3282 // Rotate bytes around so that the desired lane is element zero
3283 unsigned WdTmp1 = RegInfo.createVirtualRegister(VecRC);
3284 BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), WdTmp1)
3285 .addReg(SrcVecReg)
3286 .addReg(SrcVecReg)
Daniel Sandersd3bb2082016-06-15 08:43:23 +0000[diff] [blame]3287 .addReg(LaneReg, 0, SubRegIdx);
Daniel Sanderse296a0f2014-04-30 12:09:32 +0000[diff] [blame]3288
3289 unsigned WdTmp2 = RegInfo.createVirtualRegister(VecRC);
3290 if (IsFP) {
3291 // Use insve.df to insert to element zero
3292 BuildMI(*BB, MI, DL, TII->get(InsveOp), WdTmp2)
3293 .addReg(WdTmp1)
3294 .addImm(0)
3295 .addReg(SrcValReg)
3296 .addImm(0);
3297 } else {
3298 // Use insert.df to insert to element zero
3299 BuildMI(*BB, MI, DL, TII->get(InsertOp), WdTmp2)
3300 .addReg(WdTmp1)
3301 .addReg(SrcValReg)
3302 .addImm(0);
3303 }
3304
3305 // Rotate elements the rest of the way for a full rotation.
3306 // sld.df inteprets $rt modulo the number of columns so we only need to negate
3307 // the lane index to do this.
3308 unsigned LaneTmp2 = RegInfo.createVirtualRegister(GPRRC);
Daniel Sanders4160c802015-05-05 08:48:35 +0000[diff] [blame]3309 BuildMI(*BB, MI, DL, TII->get(Subtarget.isABI_N64() ? Mips::DSUB : Mips::SUB),
3310 LaneTmp2)
3311 .addReg(Subtarget.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO)
Daniel Sanderse296a0f2014-04-30 12:09:32 +0000[diff] [blame]3312 .addReg(LaneReg);
3313 BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), Wd)
3314 .addReg(WdTmp2)
3315 .addReg(WdTmp2)
Daniel Sandersd3bb2082016-06-15 08:43:23 +0000[diff] [blame]3316 .addReg(LaneTmp2, 0, SubRegIdx);
Daniel Sanderse296a0f2014-04-30 12:09:32 +0000[diff] [blame]3317
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3318 MI.eraseFromParent(); // The pseudo instruction is gone now.
Daniel Sanderse296a0f2014-04-30 12:09:32 +0000[diff] [blame]3319 return BB;
3320}
3321
Daniel Sanders1dfddc72013-10-15 13:14:41 +0000[diff] [blame]3322// Emit the FILL_FW pseudo instruction.
3323//
3324// fill_fw_pseudo $wd, $fs
3325// =>
3326// implicit_def $wt1
3327// insert_subreg $wt2:subreg_lo, $wt1, $fs
3328// splati.w $wd, $wt2[0]
3329MachineBasicBlock *
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3330MipsSETargetLowering::emitFILL_FW(MachineInstr &MI,
Daniel Sanders1dfddc72013-10-15 13:14:41 +0000[diff] [blame]3331 MachineBasicBlock *BB) const {
Eric Christopher96e72c62015-01-29 23:27:36 +0000[diff] [blame]3332 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
Daniel Sanders1dfddc72013-10-15 13:14:41 +0000[diff] [blame]3333 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3334 DebugLoc DL = MI.getDebugLoc();
3335 unsigned Wd = MI.getOperand(0).getReg();
3336 unsigned Fs = MI.getOperand(1).getReg();
Simon Dardis0e9e2372017-01-10 15:53:10 +0000[diff] [blame]3337 unsigned Wt1 = RegInfo.createVirtualRegister(
3338 Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass
3339 : &Mips::MSA128WEvensRegClass);
3340 unsigned Wt2 = RegInfo.createVirtualRegister(
3341 Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass
3342 : &Mips::MSA128WEvensRegClass);
Daniel Sanders1dfddc72013-10-15 13:14:41 +0000[diff] [blame]3343
3344 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
3345 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
3346 .addReg(Wt1)
3347 .addReg(Fs)
3348 .addImm(Mips::sub_lo);
3349 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wd).addReg(Wt2).addImm(0);
3350
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3351 MI.eraseFromParent(); // The pseudo instruction is gone now.
Daniel Sanders1dfddc72013-10-15 13:14:41 +0000[diff] [blame]3352 return BB;
3353}
3354
3355// Emit the FILL_FD pseudo instruction.
3356//
3357// fill_fd_pseudo $wd, $fs
3358// =>
3359// implicit_def $wt1
3360// insert_subreg $wt2:subreg_64, $wt1, $fs
3361// splati.d $wd, $wt2[0]
3362MachineBasicBlock *
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3363MipsSETargetLowering::emitFILL_FD(MachineInstr &MI,
Daniel Sanders1dfddc72013-10-15 13:14:41 +0000[diff] [blame]3364 MachineBasicBlock *BB) const {
Eric Christopher1c29a652014-07-18 22:55:25 +0000[diff] [blame]3365 assert(Subtarget.isFP64bit());
Daniel Sanders1dfddc72013-10-15 13:14:41 +0000[diff] [blame]3366
Eric Christopher96e72c62015-01-29 23:27:36 +0000[diff] [blame]3367 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
Daniel Sanders1dfddc72013-10-15 13:14:41 +0000[diff] [blame]3368 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3369 DebugLoc DL = MI.getDebugLoc();
3370 unsigned Wd = MI.getOperand(0).getReg();
3371 unsigned Fs = MI.getOperand(1).getReg();
Daniel Sanders1dfddc72013-10-15 13:14:41 +0000[diff] [blame]3372 unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3373 unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3374
3375 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
3376 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
3377 .addReg(Wt1)
3378 .addReg(Fs)
3379 .addImm(Mips::sub_64);
3380 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wd).addReg(Wt2).addImm(0);
Daniel Sandersa5150702013-09-27 12:31:32 +0000[diff] [blame]3381
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3382 MI.eraseFromParent(); // The pseudo instruction is gone now.
Daniel Sandersa5150702013-09-27 12:31:32 +0000[diff] [blame]3383 return BB;
3384}
Daniel Sandersa9521602013-10-23 10:36:52 +0000[diff] [blame]3385
Simon Dardis0e2ee3b2016-11-18 16:17:44 +0000[diff] [blame]3386// Emit the ST_F16_PSEDUO instruction to store a f16 value from an MSA
3387// register.
3388//
3389// STF16 MSA128F16:$wd, mem_simm10:$addr
3390// =>
3391// copy_u.h $rtemp,$wd[0]
3392// sh $rtemp, $addr
3393//
3394// Safety: We can't use st.h & co as they would over write the memory after
3395// the destination. It would require half floats be allocated 16 bytes(!) of
3396// space.
3397MachineBasicBlock *
3398MipsSETargetLowering::emitST_F16_PSEUDO(MachineInstr &MI,
3399 MachineBasicBlock *BB) const {
3400
3401 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3402 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3403 DebugLoc DL = MI.getDebugLoc();
3404 unsigned Ws = MI.getOperand(0).getReg();
3405 unsigned Rt = MI.getOperand(1).getReg();
3406 const MachineMemOperand &MMO = **MI.memoperands_begin();
3407 unsigned Imm = MMO.getOffset();
3408
3409 // Caution: A load via the GOT can expand to a GPR32 operand, a load via
3410 // spill and reload can expand as a GPR64 operand. Examine the
3411 // operand in detail and default to ABI.
3412 const TargetRegisterClass *RC =
3413 MI.getOperand(1).isReg() ? RegInfo.getRegClass(MI.getOperand(1).getReg())
3414 : (Subtarget.isABI_O32() ? &Mips::GPR32RegClass
3415 : &Mips::GPR64RegClass);
3416 const bool UsingMips32 = RC == &Mips::GPR32RegClass;
3417 unsigned Rs = RegInfo.createVirtualRegister(RC);
3418
3419 BuildMI(*BB, MI, DL, TII->get(Mips::COPY_U_H), Rs).addReg(Ws).addImm(0);
3420 BuildMI(*BB, MI, DL, TII->get(UsingMips32 ? Mips::SH : Mips::SH64))
3421 .addReg(Rs)
3422 .addReg(Rt)
3423 .addImm(Imm)
3424 .addMemOperand(BB->getParent()->getMachineMemOperand(
3425 &MMO, MMO.getOffset(), MMO.getSize()));
3426
3427 MI.eraseFromParent();
3428 return BB;
3429}
3430
3431// Emit the LD_F16_PSEDUO instruction to load a f16 value into an MSA register.
3432//
3433// LD_F16 MSA128F16:$wd, mem_simm10:$addr
3434// =>
3435// lh $rtemp, $addr
3436// fill.h $wd, $rtemp
3437//
3438// Safety: We can't use ld.h & co as they over-read from the source.
3439// Additionally, if the address is not modulo 16, 2 cases can occur:
3440// a) Segmentation fault as the load instruction reads from a memory page
3441// memory it's not supposed to.
3442// b) The load crosses an implementation specific boundary, requiring OS
3443// intervention.
3444//
3445MachineBasicBlock *
3446MipsSETargetLowering::emitLD_F16_PSEUDO(MachineInstr &MI,
3447 MachineBasicBlock *BB) const {
3448
3449 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3450 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3451 DebugLoc DL = MI.getDebugLoc();
3452 unsigned Wd = MI.getOperand(0).getReg();
3453
3454 // Caution: A load via the GOT can expand to a GPR32 operand, a load via
3455 // spill and reload can expand as a GPR64 operand. Examine the
3456 // operand in detail and default to ABI.
3457 const TargetRegisterClass *RC =
3458 MI.getOperand(1).isReg() ? RegInfo.getRegClass(MI.getOperand(1).getReg())
3459 : (Subtarget.isABI_O32() ? &Mips::GPR32RegClass
3460 : &Mips::GPR64RegClass);
3461
3462 const bool UsingMips32 = RC == &Mips::GPR32RegClass;
3463 unsigned Rt = RegInfo.createVirtualRegister(RC);
3464
3465 MachineInstrBuilder MIB =
3466 BuildMI(*BB, MI, DL, TII->get(UsingMips32 ? Mips::LH : Mips::LH64), Rt);
3467 for (unsigned i = 1; i < MI.getNumOperands(); i++)
Diana Picus116bbab2017-01-13 09:58:52 +0000[diff] [blame]3468 MIB.add(MI.getOperand(i));
Simon Dardis0e2ee3b2016-11-18 16:17:44 +0000[diff] [blame]3469
3470 BuildMI(*BB, MI, DL, TII->get(Mips::FILL_H), Wd).addReg(Rt);
3471
3472 MI.eraseFromParent();
3473 return BB;
3474}
3475
3476// Emit the FPROUND_PSEUDO instruction.
3477//
3478// Round an FGR64Opnd, FGR32Opnd to an f16.
3479//
3480// Safety: Cycle the operand through the GPRs so the result always ends up
3481// the correct MSA register.
3482//
3483// FIXME: This copying is strictly unnecessary. If we could tie FGR32Opnd:$Fs
3484// / FGR64Opnd:$Fs and MSA128F16:$Wd to the same physical register
3485// (which they can be, as the MSA registers are defined to alias the
3486// FPU's 64 bit and 32 bit registers) the result can be accessed using
3487// the correct register class. That requires operands be tie-able across
3488// register classes which have a sub/super register class relationship.
3489//
3490// For FPG32Opnd:
3491//
3492// FPROUND MSA128F16:$wd, FGR32Opnd:$fs
3493// =>
3494// mfc1 $rtemp, $fs
3495// fill.w $rtemp, $wtemp
3496// fexdo.w $wd, $wtemp, $wtemp
3497//
3498// For FPG64Opnd on mips32r2+:
3499//
3500// FPROUND MSA128F16:$wd, FGR64Opnd:$fs
3501// =>
3502// mfc1 $rtemp, $fs
3503// fill.w $rtemp, $wtemp
3504// mfhc1 $rtemp2, $fs
3505// insert.w $wtemp[1], $rtemp2
3506// insert.w $wtemp[3], $rtemp2
3507// fexdo.w $wtemp2, $wtemp, $wtemp
3508// fexdo.h $wd, $temp2, $temp2
3509//
3510// For FGR64Opnd on mips64r2+:
3511//
3512// FPROUND MSA128F16:$wd, FGR64Opnd:$fs
3513// =>
3514// dmfc1 $rtemp, $fs
3515// fill.d $rtemp, $wtemp
3516// fexdo.w $wtemp2, $wtemp, $wtemp
3517// fexdo.h $wd, $wtemp2, $wtemp2
3518//
3519// Safety note: As $wtemp is UNDEF, we may provoke a spurious exception if the
3520// undef bits are "just right" and the exception enable bits are
3521// set. By using fill.w to replicate $fs into all elements over
3522// insert.w for one element, we avoid that potiential case. If
3523// fexdo.[hw] causes an exception in, the exception is valid and it
3524// occurs for all elements.
3525//
3526MachineBasicBlock *
3527MipsSETargetLowering::emitFPROUND_PSEUDO(MachineInstr &MI,
3528 MachineBasicBlock *BB,
3529 bool IsFGR64) const {
3530
3531 // Strictly speaking, we need MIPS32R5 to support MSA. We'll be generous
3532 // here. It's technically doable to support MIPS32 here, but the ISA forbids
3533 // it.
3534 assert(Subtarget.hasMSA() && Subtarget.hasMips32r2());
3535
3536 bool IsFGR64onMips64 = Subtarget.hasMips64() && IsFGR64;
3537
3538 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3539 DebugLoc DL = MI.getDebugLoc();
3540 unsigned Wd = MI.getOperand(0).getReg();
3541 unsigned Fs = MI.getOperand(1).getReg();
3542
3543 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3544 unsigned Wtemp = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3545 const TargetRegisterClass *GPRRC =
3546 IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
3547 unsigned MFC1Opc = IsFGR64onMips64 ? Mips::DMFC1 : Mips::MFC1;
3548 unsigned FILLOpc = IsFGR64onMips64 ? Mips::FILL_D : Mips::FILL_W;
3549
3550 // Perform the register class copy as mentioned above.
3551 unsigned Rtemp = RegInfo.createVirtualRegister(GPRRC);
3552 BuildMI(*BB, MI, DL, TII->get(MFC1Opc), Rtemp).addReg(Fs);
3553 BuildMI(*BB, MI, DL, TII->get(FILLOpc), Wtemp).addReg(Rtemp);
3554 unsigned WPHI = Wtemp;
3555
3556 if (!Subtarget.hasMips64() && IsFGR64) {
3557 unsigned Rtemp2 = RegInfo.createVirtualRegister(GPRRC);
3558 BuildMI(*BB, MI, DL, TII->get(Mips::MFHC1_D64), Rtemp2).addReg(Fs);
3559 unsigned Wtemp2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3560 unsigned Wtemp3 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3561 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_W), Wtemp2)
3562 .addReg(Wtemp)
3563 .addReg(Rtemp2)
3564 .addImm(1);
3565 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_W), Wtemp3)
3566 .addReg(Wtemp2)
3567 .addReg(Rtemp2)
3568 .addImm(3);
3569 WPHI = Wtemp3;
3570 }
3571
3572 if (IsFGR64) {
3573 unsigned Wtemp2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3574 BuildMI(*BB, MI, DL, TII->get(Mips::FEXDO_W), Wtemp2)
3575 .addReg(WPHI)
3576 .addReg(WPHI);
3577 WPHI = Wtemp2;
3578 }
3579
3580 BuildMI(*BB, MI, DL, TII->get(Mips::FEXDO_H), Wd).addReg(WPHI).addReg(WPHI);
3581
3582 MI.eraseFromParent();
3583 return BB;
3584}
3585
3586// Emit the FPEXTEND_PSEUDO instruction.
3587//
3588// Expand an f16 to either a FGR32Opnd or FGR64Opnd.
3589//
3590// Safety: Cycle the result through the GPRs so the result always ends up
3591// the correct floating point register.
3592//
3593// FIXME: This copying is strictly unnecessary. If we could tie FGR32Opnd:$Fd
3594// / FGR64Opnd:$Fd and MSA128F16:$Ws to the same physical register
3595// (which they can be, as the MSA registers are defined to alias the
3596// FPU's 64 bit and 32 bit registers) the result can be accessed using
3597// the correct register class. That requires operands be tie-able across
3598// register classes which have a sub/super register class relationship. I
3599// haven't checked.
3600//
3601// For FGR32Opnd:
3602//
3603// FPEXTEND FGR32Opnd:$fd, MSA128F16:$ws
3604// =>
3605// fexupr.w $wtemp, $ws
3606// copy_s.w $rtemp, $ws[0]
3607// mtc1 $rtemp, $fd
3608//
3609// For FGR64Opnd on Mips64:
3610//
3611// FPEXTEND FGR64Opnd:$fd, MSA128F16:$ws
3612// =>
3613// fexupr.w $wtemp, $ws
3614// fexupr.d $wtemp2, $wtemp
3615// copy_s.d $rtemp, $wtemp2s[0]
3616// dmtc1 $rtemp, $fd
3617//
3618// For FGR64Opnd on Mips32:
3619//
3620// FPEXTEND FGR64Opnd:$fd, MSA128F16:$ws
3621// =>
3622// fexupr.w $wtemp, $ws
3623// fexupr.d $wtemp2, $wtemp
3624// copy_s.w $rtemp, $wtemp2[0]
3625// mtc1 $rtemp, $ftemp
3626// copy_s.w $rtemp2, $wtemp2[1]
3627// $fd = mthc1 $rtemp2, $ftemp
3628//
3629MachineBasicBlock *
3630MipsSETargetLowering::emitFPEXTEND_PSEUDO(MachineInstr &MI,
3631 MachineBasicBlock *BB,
3632 bool IsFGR64) const {
3633
3634 // Strictly speaking, we need MIPS32R5 to support MSA. We'll be generous
3635 // here. It's technically doable to support MIPS32 here, but the ISA forbids
3636 // it.
3637 assert(Subtarget.hasMSA() && Subtarget.hasMips32r2());
3638
3639 bool IsFGR64onMips64 = Subtarget.hasMips64() && IsFGR64;
3640 bool IsFGR64onMips32 = !Subtarget.hasMips64() && IsFGR64;
3641
3642 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
3643 DebugLoc DL = MI.getDebugLoc();
3644 unsigned Fd = MI.getOperand(0).getReg();
3645 unsigned Ws = MI.getOperand(1).getReg();
3646
3647 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3648 const TargetRegisterClass *GPRRC =
3649 IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
3650 unsigned MTC1Opc = IsFGR64onMips64 ? Mips::DMTC1 : Mips::MTC1;
3651 unsigned COPYOpc = IsFGR64onMips64 ? Mips::COPY_S_D : Mips::COPY_S_W;
3652
3653 unsigned Wtemp = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3654 unsigned WPHI = Wtemp;
3655
3656 BuildMI(*BB, MI, DL, TII->get(Mips::FEXUPR_W), Wtemp).addReg(Ws);
3657 if (IsFGR64) {
3658 WPHI = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3659 BuildMI(*BB, MI, DL, TII->get(Mips::FEXUPR_D), WPHI).addReg(Wtemp);
3660 }
3661
3662 // Perform the safety regclass copy mentioned above.
3663 unsigned Rtemp = RegInfo.createVirtualRegister(GPRRC);
3664 unsigned FPRPHI = IsFGR64onMips32
3665 ? RegInfo.createVirtualRegister(&Mips::FGR64RegClass)
3666 : Fd;
3667 BuildMI(*BB, MI, DL, TII->get(COPYOpc), Rtemp).addReg(WPHI).addImm(0);
3668 BuildMI(*BB, MI, DL, TII->get(MTC1Opc), FPRPHI).addReg(Rtemp);
3669
3670 if (IsFGR64onMips32) {
3671 unsigned Rtemp2 = RegInfo.createVirtualRegister(GPRRC);
3672 BuildMI(*BB, MI, DL, TII->get(Mips::COPY_S_W), Rtemp2)
3673 .addReg(WPHI)
3674 .addImm(1);
3675 BuildMI(*BB, MI, DL, TII->get(Mips::MTHC1_D64), Fd)
3676 .addReg(FPRPHI)
3677 .addReg(Rtemp2);
3678 }
3679
3680 MI.eraseFromParent();
3681 return BB;
3682}
3683
Daniel Sandersa9521602013-10-23 10:36:52 +0000[diff] [blame]3684// Emit the FEXP2_W_1 pseudo instructions.
3685//
3686// fexp2_w_1_pseudo $wd, $wt
3687// =>
3688// ldi.w $ws, 1
3689// fexp2.w $wd, $ws, $wt
3690MachineBasicBlock *
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3691MipsSETargetLowering::emitFEXP2_W_1(MachineInstr &MI,
Daniel Sandersa9521602013-10-23 10:36:52 +0000[diff] [blame]3692 MachineBasicBlock *BB) const {
Eric Christopher96e72c62015-01-29 23:27:36 +0000[diff] [blame]3693 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
Daniel Sandersa9521602013-10-23 10:36:52 +0000[diff] [blame]3694 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3695 const TargetRegisterClass *RC = &Mips::MSA128WRegClass;
3696 unsigned Ws1 = RegInfo.createVirtualRegister(RC);
3697 unsigned Ws2 = RegInfo.createVirtualRegister(RC);
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3698 DebugLoc DL = MI.getDebugLoc();
Daniel Sandersa9521602013-10-23 10:36:52 +0000[diff] [blame]3699
3700 // Splat 1.0 into a vector
3701 BuildMI(*BB, MI, DL, TII->get(Mips::LDI_W), Ws1).addImm(1);
3702 BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_W), Ws2).addReg(Ws1);
3703
3704 // Emit 1.0 * fexp2(Wt)
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3705 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_W), MI.getOperand(0).getReg())
Daniel Sandersa9521602013-10-23 10:36:52 +0000[diff] [blame]3706 .addReg(Ws2)
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3707 .addReg(MI.getOperand(1).getReg());
Daniel Sandersa9521602013-10-23 10:36:52 +0000[diff] [blame]3708
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3709 MI.eraseFromParent(); // The pseudo instruction is gone now.
Daniel Sandersa9521602013-10-23 10:36:52 +0000[diff] [blame]3710 return BB;
3711}
3712
3713// Emit the FEXP2_D_1 pseudo instructions.
3714//
3715// fexp2_d_1_pseudo $wd, $wt
3716// =>
3717// ldi.d $ws, 1
3718// fexp2.d $wd, $ws, $wt
3719MachineBasicBlock *
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3720MipsSETargetLowering::emitFEXP2_D_1(MachineInstr &MI,
Daniel Sandersa9521602013-10-23 10:36:52 +0000[diff] [blame]3721 MachineBasicBlock *BB) const {
Eric Christopher96e72c62015-01-29 23:27:36 +0000[diff] [blame]3722 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
Daniel Sandersa9521602013-10-23 10:36:52 +0000[diff] [blame]3723 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3724 const TargetRegisterClass *RC = &Mips::MSA128DRegClass;
3725 unsigned Ws1 = RegInfo.createVirtualRegister(RC);
3726 unsigned Ws2 = RegInfo.createVirtualRegister(RC);
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3727 DebugLoc DL = MI.getDebugLoc();
Daniel Sandersa9521602013-10-23 10:36:52 +0000[diff] [blame]3728
3729 // Splat 1.0 into a vector
3730 BuildMI(*BB, MI, DL, TII->get(Mips::LDI_D), Ws1).addImm(1);
3731 BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_D), Ws2).addReg(Ws1);
3732
3733 // Emit 1.0 * fexp2(Wt)
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3734 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_D), MI.getOperand(0).getReg())
Daniel Sandersa9521602013-10-23 10:36:52 +0000[diff] [blame]3735 .addReg(Ws2)
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3736 .addReg(MI.getOperand(1).getReg());
Daniel Sandersa9521602013-10-23 10:36:52 +0000[diff] [blame]3737
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +0000[diff] [blame]3738 MI.eraseFromParent(); // The pseudo instruction is gone now.
Daniel Sandersa9521602013-10-23 10:36:52 +0000[diff] [blame]3739 return BB;
3740}