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gerrit-public.fairphone.software / toolchain / llvm-project / e85b06d65f695c576df1e529ee37cb15e6902401 / . / llvm / test / CodeGen / PowerPC / testComparesilesi.ll
blob: 72439bd9aa3a859e19474ba406b3d13e33d2f7b0 [file] [log] [blame]
Nemanja Ivanovicd6f93f52017-09-22 11:50:25 +0000[diff] [blame]1; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
Nemanja Ivanovicdb7e7702017-11-30 13:39:10 +0000[diff] [blame]2; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
Nemanja Ivanovicd6f93f52017-09-22 11:50:25 +0000[diff] [blame]3; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
4; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
Nemanja Ivanovicdb7e7702017-11-30 13:39:10 +0000[diff] [blame]5; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
Nemanja Ivanovicd6f93f52017-09-22 11:50:25 +0000[diff] [blame]6; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
7; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
8@glob = common local_unnamed_addr global i32 0, align 4
9
10define signext i32 @test_ilesi(i32 signext %a, i32 signext %b) {
11; CHECK-LABEL: test_ilesi:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]12; CHECK: # %bb.0: # %entry
Nemanja Ivanovicd6f93f52017-09-22 11:50:25 +0000[diff] [blame]13; CHECK-NEXT: sub r3, r4, r3
14; CHECK-NEXT: rldicl r3, r3, 1, 63
15; CHECK-NEXT: xori r3, r3, 1
16; CHECK-NEXT: blr
17entry:
18 %cmp = icmp sle i32 %a, %b
19 %conv = zext i1 %cmp to i32
20 ret i32 %conv
21}
22
23define signext i32 @test_ilesi_sext(i32 signext %a, i32 signext %b) {
24; CHECK-LABEL: test_ilesi_sext:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]25; CHECK: # %bb.0: # %entry
Nemanja Ivanovicd6f93f52017-09-22 11:50:25 +0000[diff] [blame]26; CHECK-NEXT: sub r3, r4, r3
27; CHECK-NEXT: rldicl r3, r3, 1, 63
28; CHECK-NEXT: addi r3, r3, -1
29; CHECK-NEXT: blr
30entry:
31 %cmp = icmp sle i32 %a, %b
32 %sub = sext i1 %cmp to i32
33 ret i32 %sub
34}
35
36define void @test_ilesi_store(i32 signext %a, i32 signext %b) {
37; CHECK-LABEL: test_ilesi_store:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]38; CHECK: # %bb.0: # %entry
Nemanja Ivanovicd6f93f52017-09-22 11:50:25 +0000[diff] [blame]39; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
40; CHECK-NEXT: sub r3, r4, r3
41; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
42; CHECK-NEXT: rldicl r3, r3, 1, 63
43; CHECK-NEXT: xori r3, r3, 1
44; CHECK-NEXT: stw r3, 0(r12)
45; CHECK-NEXT: blr
46entry:
47 %cmp = icmp sle i32 %a, %b
48 %conv = zext i1 %cmp to i32
49 store i32 %conv, i32* @glob, align 4
50 ret void
51}
52
53define void @test_ilesi_sext_store(i32 signext %a, i32 signext %b) {
54; CHECK-LABEL: test_ilesi_sext_store:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]55; CHECK: # %bb.0: # %entry
Nemanja Ivanovicd6f93f52017-09-22 11:50:25 +0000[diff] [blame]56; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
57; CHECK-NEXT: sub r3, r4, r3
58; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
59; CHECK-NEXT: rldicl r3, r3, 1, 63
60; CHECK-NEXT: addi r3, r3, -1
61; CHECK-NEXT: stw r3, 0(r12)
62; CHECK-NEXT: blr
63entry:
64 %cmp = icmp sle i32 %a, %b
65 %sub = sext i1 %cmp to i32
66 store i32 %sub, i32* @glob, align 4
67 ret void
68}