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Jakob Stoklund Olesend0d78602012-10-11 16:46:07 +00001; RUN: llc < %s -x86-early-ifcvt -verify-machineinstrs
2; RUN: llc < %s -x86-early-ifcvt -stress-early-ifcvt -verify-machineinstrs
Jakob Stoklund Olesen8fbfc592013-04-02 18:26:45 +00003; CPU without a scheduling model:
4; RUN: llc < %s -x86-early-ifcvt -mcpu=pentium3 -verify-machineinstrs
Jakob Stoklund Olesend0d78602012-10-11 16:46:07 +00005;
6; Run these tests with and without -stress-early-ifcvt to exercise heuristics.
7;
8target triple = "x86_64-apple-macosx10.8.0"
9
10; MachineTraceMetrics::Ensemble::addLiveIns crashes because the first operand
11; on an inline asm instruction is not a vreg def.
12; <rdar://problem/12472811>
13define void @f1() nounwind {
14entry:
15 br i1 undef, label %if.then6.i, label %if.end.i
16
17if.then6.i:
18 br label %if.end.i
19
20if.end.i:
21 br i1 undef, label %if.end25.i, label %if.else17.i
22
23if.else17.i:
24 %shl24.i = shl i32 undef, undef
25 br label %if.end25.i
26
27if.end25.i:
28 %storemerge31.i = phi i32 [ %shl24.i, %if.else17.i ], [ 0, %if.end.i ]
29 store i32 %storemerge31.i, i32* undef, align 4
30 %0 = tail call i32 asm sideeffect "", "=r,r,i,i"(i32 undef, i32 15, i32 1) nounwind
31 %conv = trunc i32 %0 to i8
32 store i8 %conv, i8* undef, align 1
33 unreachable
34}