Matt Arsenault | a202538 | 2017-08-03 23:24:05 +0000 | [diff] [blame] | 1 | ; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,HSA,HSA-NOENV %s |
| 2 | ; RUN: llc -mtriple=amdgcn-amd-amdhsa-opencl -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,HSA,HSA-OPENCL %s |
| 3 | ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,MESA %s |
Matt Arsenault | 9166ce8 | 2017-07-28 15:52:08 +0000 | [diff] [blame] | 4 | |
| 5 | ; GCN-LABEL: {{^}}kernel_implicitarg_ptr_empty: |
| 6 | ; GCN: enable_sgpr_kernarg_segment_ptr = 1 |
| 7 | |
| 8 | ; HSA-NOENV: kernarg_segment_byte_size = 0 |
| 9 | ; HSA-OPENCL: kernarg_segment_byte_size = 32 |
| 10 | ; MESA: kernarg_segment_byte_size = 16 |
| 11 | |
| 12 | ; HSA: s_load_dword s0, s[4:5], 0x0 |
| 13 | define amdgpu_kernel void @kernel_implicitarg_ptr_empty() #0 { |
| 14 | %implicitarg.ptr = call i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr() |
| 15 | %cast = bitcast i8 addrspace(2)* %implicitarg.ptr to i32 addrspace(2)* |
| 16 | %load = load volatile i32, i32 addrspace(2)* %cast |
| 17 | ret void |
| 18 | } |
| 19 | |
| 20 | ; GCN-LABEL: {{^}}kernel_implicitarg_ptr: |
| 21 | ; GCN: enable_sgpr_kernarg_segment_ptr = 1 |
| 22 | |
| 23 | ; HSA-NOENV: kernarg_segment_byte_size = 112 |
| 24 | ; HSA-OPENCL: kernarg_segment_byte_size = 144 |
| 25 | ; MESA: kernarg_segment_byte_size = 464 |
| 26 | |
| 27 | ; HSA: s_load_dword s0, s[4:5], 0x1c |
| 28 | define amdgpu_kernel void @kernel_implicitarg_ptr([112 x i8]) #0 { |
| 29 | %implicitarg.ptr = call i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr() |
| 30 | %cast = bitcast i8 addrspace(2)* %implicitarg.ptr to i32 addrspace(2)* |
| 31 | %load = load volatile i32, i32 addrspace(2)* %cast |
| 32 | ret void |
| 33 | } |
| 34 | |
Matt Arsenault | 817c253 | 2017-08-03 23:12:44 +0000 | [diff] [blame] | 35 | ; GCN-LABEL: {{^}}func_implicitarg_ptr: |
| 36 | ; GCN: s_waitcnt |
| 37 | ; GCN-NEXT: s_load_dword s{{[0-9]+}}, s[6:7], 0x0{{$}} |
| 38 | ; GCN-NEXT: s_waitcnt |
| 39 | ; GCN-NEXT: s_setpc_b64 |
| 40 | define void @func_implicitarg_ptr() #1 { |
| 41 | %implicitarg.ptr = call i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr() |
| 42 | %cast = bitcast i8 addrspace(2)* %implicitarg.ptr to i32 addrspace(2)* |
| 43 | %load = load volatile i32, i32 addrspace(2)* %cast |
| 44 | ret void |
| 45 | } |
| 46 | |
| 47 | ; GCN-LABEL: {{^}}kernel_call_implicitarg_ptr_func_empty: |
| 48 | ; GCN: enable_sgpr_kernarg_segment_ptr = 1 |
| 49 | ; HSA-NOENV: kernarg_segment_byte_size = 0 |
| 50 | ; HSA-OPENCL: kernarg_segment_byte_size = 32 |
| 51 | ; MESA: kernarg_segment_byte_size = 16 |
| 52 | ; GCN: s_mov_b64 s[6:7], s[4:5] |
| 53 | ; GCN: s_swappc_b64 |
| 54 | define amdgpu_kernel void @kernel_call_implicitarg_ptr_func_empty() #0 { |
| 55 | call void @func_implicitarg_ptr() |
| 56 | ret void |
| 57 | } |
| 58 | |
| 59 | ; GCN-LABEL: {{^}}kernel_call_implicitarg_ptr_func: |
| 60 | ; GCN: enable_sgpr_kernarg_segment_ptr = 1 |
| 61 | ; HSA-OPENCL: kernarg_segment_byte_size = 144 |
| 62 | ; HSA-NOENV: kernarg_segment_byte_size = 112 |
| 63 | ; MESA: kernarg_segment_byte_size = 464 |
| 64 | |
| 65 | ; HSA: s_add_u32 s6, s4, 0x70 |
| 66 | ; MESA: s_add_u32 s6, s4, 0x1c0 |
| 67 | |
| 68 | ; GCN: s_addc_u32 s7, s5, 0{{$}} |
| 69 | ; GCN: s_swappc_b64 |
| 70 | define amdgpu_kernel void @kernel_call_implicitarg_ptr_func([112 x i8]) #0 { |
| 71 | call void @func_implicitarg_ptr() |
| 72 | ret void |
| 73 | } |
| 74 | |
| 75 | ; GCN-LABEL: {{^}}func_call_implicitarg_ptr_func: |
| 76 | ; GCN-NOT: s6 |
| 77 | ; GCN-NOT: s7 |
| 78 | ; GCN-NOT: s[6:7] |
| 79 | define void @func_call_implicitarg_ptr_func() #1 { |
| 80 | call void @func_implicitarg_ptr() |
| 81 | ret void |
| 82 | } |
| 83 | |
| 84 | ; GCN-LABEL: {{^}}func_kernarg_implicitarg_ptr: |
| 85 | ; GCN: s_waitcnt |
| 86 | ; GCN: s_load_dword s{{[0-9]+}}, s[6:7], 0x0{{$}} |
| 87 | ; GCN: s_load_dword s{{[0-9]+}}, s[8:9], 0x0{{$}} |
| 88 | define void @func_kernarg_implicitarg_ptr() #1 { |
| 89 | %kernarg.segment.ptr = call i8 addrspace(2)* @llvm.amdgcn.kernarg.segment.ptr() |
| 90 | %implicitarg.ptr = call i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr() |
| 91 | %cast.kernarg.segment.ptr = bitcast i8 addrspace(2)* %kernarg.segment.ptr to i32 addrspace(2)* |
| 92 | %cast.implicitarg = bitcast i8 addrspace(2)* %implicitarg.ptr to i32 addrspace(2)* |
| 93 | %load0 = load volatile i32, i32 addrspace(2)* %cast.kernarg.segment.ptr |
| 94 | %load1 = load volatile i32, i32 addrspace(2)* %cast.implicitarg |
| 95 | ret void |
| 96 | } |
| 97 | |
| 98 | ; GCN-LABEL: {{^}}kernel_call_kernarg_implicitarg_ptr_func: |
| 99 | ; GCN: s_mov_b64 s[6:7], s[4:5] |
| 100 | ; HSA: s_add_u32 s8, s6, 0x70 |
| 101 | ; MESA: s_add_u32 s8, s6, 0x1c0 |
| 102 | ; GCN: s_addc_u32 s9, s7, 0 |
| 103 | ; GCN: s_swappc_b64 |
| 104 | define amdgpu_kernel void @kernel_call_kernarg_implicitarg_ptr_func([112 x i8]) #0 { |
| 105 | call void @func_kernarg_implicitarg_ptr() |
| 106 | ret void |
| 107 | } |
| 108 | |
Matt Arsenault | 9166ce8 | 2017-07-28 15:52:08 +0000 | [diff] [blame] | 109 | declare i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr() #2 |
Matt Arsenault | 817c253 | 2017-08-03 23:12:44 +0000 | [diff] [blame] | 110 | declare i8 addrspace(2)* @llvm.amdgcn.kernarg.segment.ptr() #2 |
Matt Arsenault | 9166ce8 | 2017-07-28 15:52:08 +0000 | [diff] [blame] | 111 | |
| 112 | attributes #0 = { nounwind noinline } |
| 113 | attributes #1 = { nounwind noinline } |
| 114 | attributes #2 = { nounwind readnone speculatable } |