blob: e14b30680ba1d895f6f8fb4e0e419e44e05e124b [file] [log] [blame]
Marek Olsak37cd4d02015-02-03 21:53:27 +00001; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=redwood | FileCheck --check-prefix=EG %s
2; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=rs880 | FileCheck --check-prefix=R600 %s
Tom Stellardecc2ad12013-05-17 15:23:21 +00003
4; The earliest R600 GPUs have a slightly different encoding than the rest of
5; the VLIW4/5 GPUs.
6
Marek Olsak37cd4d02015-02-03 21:53:27 +00007; EG: {{^}}test:
8; EG: MUL_IEEE {{[ *TXYZWPVxyzw.,0-9]+}} ; encoding: [{{0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x10,0x01,0x[0-9a-f]+,0x[0-9a-f]+}}]
Tom Stellardecc2ad12013-05-17 15:23:21 +00009
Marek Olsak37cd4d02015-02-03 21:53:27 +000010; R600: {{^}}test:
11; R600: MUL_IEEE {{[ *TXYZWPVxyzw.,0-9]+}} ; encoding: [{{0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x10,0x02,0x[0-9a-f]+,0x[0-9a-f]+}}]
Tom Stellardecc2ad12013-05-17 15:23:21 +000012
Nicolai Haehnledf3a20c2016-04-06 19:40:20 +000013define amdgpu_ps void @test(<4 x float> inreg %reg0) {
Tom Stellardecc2ad12013-05-17 15:23:21 +000014entry:
Vincent Lejeunef143af32013-11-11 22:10:24 +000015 %r0 = extractelement <4 x float> %reg0, i32 0
16 %r1 = extractelement <4 x float> %reg0, i32 1
17 %r2 = fmul float %r0, %r1
18 %vec = insertelement <4 x float> undef, float %r2, i32 0
Matt Arsenault82e5e1e2016-07-15 21:27:08 +000019 call void @llvm.r600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
Tom Stellardecc2ad12013-05-17 15:23:21 +000020 ret void
21}
22
Matt Arsenault82e5e1e2016-07-15 21:27:08 +000023declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32)