Michel Danzer | ee7b608 | 2013-08-27 10:28:26 +0000 | [diff] [blame^] | 1 | ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s |
| 2 | ; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s |
Michel Danzer | 49812b5 | 2013-07-10 16:37:07 +0000 | [diff] [blame] | 3 | |
| 4 | @local_memory_two_objects.local_mem0 = internal addrspace(3) unnamed_addr global [4 x i32] zeroinitializer, align 4 |
| 5 | @local_memory_two_objects.local_mem1 = internal addrspace(3) unnamed_addr global [4 x i32] zeroinitializer, align 4 |
| 6 | |
Michel Danzer | ee7b608 | 2013-08-27 10:28:26 +0000 | [diff] [blame^] | 7 | ; EG-CHECK: @local_memory_two_objects |
Michel Danzer | 49812b5 | 2013-07-10 16:37:07 +0000 | [diff] [blame] | 8 | |
| 9 | ; Check that the LDS size emitted correctly |
Michel Danzer | ee7b608 | 2013-08-27 10:28:26 +0000 | [diff] [blame^] | 10 | ; EG-CHECK: .long 166120 |
| 11 | ; EG-CHECK-NEXT: .long 8 |
| 12 | ; SI-CHECK: .long 47180 |
| 13 | ; SI-CHECK-NEXT: .long 32768 |
Michel Danzer | 49812b5 | 2013-07-10 16:37:07 +0000 | [diff] [blame] | 14 | |
| 15 | ; Make sure the lds writes are using different addresses. |
Michel Danzer | ee7b608 | 2013-08-27 10:28:26 +0000 | [diff] [blame^] | 16 | ; EG-CHECK: LDS_WRITE {{[*]*}} {{PV|T}}[[ADDRW:[0-9]*\.[XYZW]]] |
| 17 | ; EG-CHECK-NOT: LDS_WRITE {{[*]*}} T[[ADDRW]] |
| 18 | ; SI-CHECK: DS_WRITE_B32 0, {{VGPR[0-9]*}}, VGPR[[ADDRW:[0-9]*]] |
| 19 | ; SI-CHECK-NOT: DS_WRITE_B32 0, {{VGPR[0-9]*}}, VGPR[[ADDRW]] |
Michel Danzer | 49812b5 | 2013-07-10 16:37:07 +0000 | [diff] [blame] | 20 | |
| 21 | ; GROUP_BARRIER must be the last instruction in a clause |
Michel Danzer | ee7b608 | 2013-08-27 10:28:26 +0000 | [diff] [blame^] | 22 | ; EG-CHECK: GROUP_BARRIER |
| 23 | ; EG-CHECK-NEXT: ALU clause |
Michel Danzer | 49812b5 | 2013-07-10 16:37:07 +0000 | [diff] [blame] | 24 | |
| 25 | ; Make sure the lds reads are using different addresses. |
Michel Danzer | ee7b608 | 2013-08-27 10:28:26 +0000 | [diff] [blame^] | 26 | ; EG-CHECK: LDS_READ_RET {{[*]*}} OQAP, {{PV|T}}[[ADDRR:[0-9]*\.[XYZW]]] |
| 27 | ; EG-CHECK-NOT: LDS_READ_RET {{[*]*}} OQAP, T[[ADDRR]] |
| 28 | ; SI-CHECK: DS_READ_B32 {{VGPR[0-9]+}}, 0, [[ADDRR:VGPR[0-9]+]] |
| 29 | ; SI-CHECK-NOT: DS_READ_B32 {{VGPR[0-9]+}}, 0, [[ADDRR]] |
Michel Danzer | 49812b5 | 2013-07-10 16:37:07 +0000 | [diff] [blame] | 30 | |
| 31 | define void @local_memory_two_objects(i32 addrspace(1)* %out) { |
| 32 | entry: |
| 33 | %x.i = call i32 @llvm.r600.read.tidig.x() #0 |
| 34 | %arrayidx = getelementptr inbounds [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem0, i32 0, i32 %x.i |
| 35 | store i32 %x.i, i32 addrspace(3)* %arrayidx, align 4 |
| 36 | %mul = shl nsw i32 %x.i, 1 |
| 37 | %arrayidx1 = getelementptr inbounds [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem1, i32 0, i32 %x.i |
| 38 | store i32 %mul, i32 addrspace(3)* %arrayidx1, align 4 |
| 39 | %sub = sub nsw i32 3, %x.i |
| 40 | call void @llvm.AMDGPU.barrier.local() |
| 41 | %arrayidx2 = getelementptr inbounds [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem0, i32 0, i32 %sub |
| 42 | %0 = load i32 addrspace(3)* %arrayidx2, align 4 |
| 43 | %arrayidx3 = getelementptr inbounds i32 addrspace(1)* %out, i32 %x.i |
| 44 | store i32 %0, i32 addrspace(1)* %arrayidx3, align 4 |
| 45 | %arrayidx4 = getelementptr inbounds [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem1, i32 0, i32 %sub |
| 46 | %1 = load i32 addrspace(3)* %arrayidx4, align 4 |
| 47 | %add = add nsw i32 %x.i, 4 |
| 48 | %arrayidx5 = getelementptr inbounds i32 addrspace(1)* %out, i32 %add |
| 49 | store i32 %1, i32 addrspace(1)* %arrayidx5, align 4 |
| 50 | ret void |
| 51 | } |
| 52 | |
| 53 | declare i32 @llvm.r600.read.tidig.x() #0 |
| 54 | declare void @llvm.AMDGPU.barrier.local() |
| 55 | |
| 56 | attributes #0 = { readnone } |