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Dan Gohman10e730a2015-06-29 23:51:55 +00001//===-- WebAssemblyInstrInfo.cpp - WebAssembly Instruction Information ----===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9///
10/// \file
11/// \brief This file contains the WebAssembly implementation of the
12/// TargetInstrInfo class.
13///
14//===----------------------------------------------------------------------===//
15
16#include "WebAssemblyInstrInfo.h"
17#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
18#include "WebAssemblySubtarget.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/MachineMemOperand.h"
22#include "llvm/CodeGen/MachineRegisterInfo.h"
23using namespace llvm;
24
25#define DEBUG_TYPE "wasm-instr-info"
26
JF Bastienb9073fb2015-07-22 21:28:15 +000027#define GET_INSTRINFO_CTOR_DTOR
28#include "WebAssemblyGenInstrInfo.inc"
29
Dan Gohman10e730a2015-06-29 23:51:55 +000030WebAssemblyInstrInfo::WebAssemblyInstrInfo(const WebAssemblySubtarget &STI)
Dan Gohman35bfb242015-12-04 23:22:35 +000031 : WebAssemblyGenInstrInfo(WebAssembly::ADJCALLSTACKDOWN,
32 WebAssembly::ADJCALLSTACKUP),
33 RI(STI.getTargetTriple()) {}
Dan Gohman4f52e002015-09-09 00:52:47 +000034
35void WebAssemblyInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
36 MachineBasicBlock::iterator I,
37 DebugLoc DL, unsigned DestReg,
38 unsigned SrcReg, bool KillSrc) const {
Dan Gohman4ba48162015-11-18 16:12:01 +000039 const TargetRegisterClass *RC =
40 MBB.getParent()->getRegInfo().getRegClass(SrcReg);
41
Dan Gohmanaa0a4bd2015-11-23 19:30:43 +000042 unsigned CopyLocalOpcode;
Dan Gohman4ba48162015-11-18 16:12:01 +000043 if (RC == &WebAssembly::I32RegClass)
Dan Gohmanaa0a4bd2015-11-23 19:30:43 +000044 CopyLocalOpcode = WebAssembly::COPY_LOCAL_I32;
Dan Gohman4ba48162015-11-18 16:12:01 +000045 else if (RC == &WebAssembly::I64RegClass)
Dan Gohmanaa0a4bd2015-11-23 19:30:43 +000046 CopyLocalOpcode = WebAssembly::COPY_LOCAL_I64;
Dan Gohman4ba48162015-11-18 16:12:01 +000047 else if (RC == &WebAssembly::F32RegClass)
Dan Gohmanaa0a4bd2015-11-23 19:30:43 +000048 CopyLocalOpcode = WebAssembly::COPY_LOCAL_F32;
Dan Gohman4ba48162015-11-18 16:12:01 +000049 else if (RC == &WebAssembly::F64RegClass)
Dan Gohmanaa0a4bd2015-11-23 19:30:43 +000050 CopyLocalOpcode = WebAssembly::COPY_LOCAL_F64;
Dan Gohman4ba48162015-11-18 16:12:01 +000051 else
52 llvm_unreachable("Unexpected register class");
53
Dan Gohmanaa0a4bd2015-11-23 19:30:43 +000054 BuildMI(MBB, I, DL, get(CopyLocalOpcode), DestReg)
Dan Gohman4f52e002015-09-09 00:52:47 +000055 .addReg(SrcReg, KillSrc ? RegState::Kill : 0);
56}
Dan Gohman950a13c2015-09-16 16:51:30 +000057
58// Branch analysis.
59bool WebAssemblyInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
60 MachineBasicBlock *&TBB,
61 MachineBasicBlock *&FBB,
62 SmallVectorImpl<MachineOperand> &Cond,
Dan Gohman7a6b9822015-11-29 22:32:02 +000063 bool /*AllowModify*/) const {
Dan Gohman950a13c2015-09-16 16:51:30 +000064 bool HaveCond = false;
65 for (MachineInstr &MI : iterator_range<MachineBasicBlock::instr_iterator>(
66 MBB.getFirstInstrTerminator(), MBB.instr_end())) {
67 switch (MI.getOpcode()) {
68 default:
69 // Unhandled instruction; bail out.
70 return true;
Dan Gohman231244c2015-11-13 00:46:31 +000071 case WebAssembly::BR_IF:
Dan Gohman950a13c2015-09-16 16:51:30 +000072 if (HaveCond)
73 return true;
Dan Gohmanf0b165a2015-12-05 03:03:35 +000074 Cond.push_back(MachineOperand::CreateImm(true));
75 Cond.push_back(MI.getOperand(0));
76 TBB = MI.getOperand(1).getMBB();
77 HaveCond = true;
78 break;
79 case WebAssembly::BR_UNLESS:
80 if (HaveCond)
81 return true;
82 Cond.push_back(MachineOperand::CreateImm(false));
Derek Schuff4ed47782015-11-16 21:04:51 +000083 Cond.push_back(MI.getOperand(0));
84 TBB = MI.getOperand(1).getMBB();
Dan Gohman950a13c2015-09-16 16:51:30 +000085 HaveCond = true;
86 break;
87 case WebAssembly::BR:
88 if (!HaveCond)
89 TBB = MI.getOperand(0).getMBB();
90 else
91 FBB = MI.getOperand(0).getMBB();
92 break;
93 }
94 if (MI.isBarrier())
95 break;
96 }
97
98 return false;
99}
100
101unsigned WebAssemblyInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
102 MachineBasicBlock::instr_iterator I = MBB.instr_end();
103 unsigned Count = 0;
104
105 while (I != MBB.instr_begin()) {
106 --I;
107 if (I->isDebugValue())
108 continue;
109 if (!I->isTerminator())
110 break;
111 // Remove the branch.
112 I->eraseFromParent();
113 I = MBB.instr_end();
114 ++Count;
115 }
116
117 return Count;
118}
119
Dan Gohman7a6b9822015-11-29 22:32:02 +0000120unsigned WebAssemblyInstrInfo::InsertBranch(MachineBasicBlock &MBB,
121 MachineBasicBlock *TBB,
122 MachineBasicBlock *FBB,
123 ArrayRef<MachineOperand> Cond,
124 DebugLoc DL) const {
Dan Gohman950a13c2015-09-16 16:51:30 +0000125 if (Cond.empty()) {
126 if (!TBB)
127 return 0;
128
129 BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(TBB);
130 return 1;
131 }
132
Dan Gohmanf0b165a2015-12-05 03:03:35 +0000133 assert(Cond.size() == 2 && "Expected a flag and a successor block");
134
135 if (Cond[0].getImm()) {
136 BuildMI(&MBB, DL, get(WebAssembly::BR_IF))
137 .addOperand(Cond[1])
138 .addMBB(TBB);
139 } else {
140 BuildMI(&MBB, DL, get(WebAssembly::BR_UNLESS))
141 .addOperand(Cond[1])
142 .addMBB(TBB);
143 }
Dan Gohman950a13c2015-09-16 16:51:30 +0000144 if (!FBB)
145 return 1;
146
147 BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(FBB);
148 return 2;
149}
150
151bool WebAssemblyInstrInfo::ReverseBranchCondition(
152 SmallVectorImpl<MachineOperand> &Cond) const {
Dan Gohmanf0b165a2015-12-05 03:03:35 +0000153 assert(Cond.size() == 2 && "Expected a flag and a successor block");
154 Cond.front() = MachineOperand::CreateImm(!Cond.front().getImm());
155 return false;
Dan Gohman950a13c2015-09-16 16:51:30 +0000156}