Blame - llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp - toolchain/llvm-project

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Jia Liu	b22310f	2012-02-18 12:03:15 +0000	[diff] [blame]	1	//===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	2	//
				3	// The LLVM Compiler Infrastructure
				4	//
				5	// This file is distributed under the University of Illinois Open Source
				6	// License. See LICENSE.TXT for details.
				7	//
				8	//===----------------------------------------------------------------------===//
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	9
Benjamin Kramer	f57c197	2016-01-26 16:44:37 +0000	[diff] [blame]	10	#include "llvm/MC/MCDisassembler/MCDisassembler.h"
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	11	#include "MCTargetDesc/ARMAddressingModes.h"
				12	#include "MCTargetDesc/ARMBaseInfo.h"
Chandler Carruth	ed0881b	2012-12-03 16:50:05 +0000	[diff] [blame]	13	#include "MCTargetDesc/ARMMCExpr.h"
Chandler Carruth	ed0881b	2012-12-03 16:50:05 +0000	[diff] [blame]	14	#include "llvm/MC/MCContext.h"
				15	#include "llvm/MC/MCExpr.h"
				16	#include "llvm/MC/MCFixedLenDisassembler.h"
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	17	#include "llvm/MC/MCInst.h"
Benjamin Kramer	48b5bbf	2011-11-11 12:39:41 +0000	[diff] [blame]	18	#include "llvm/MC/MCInstrDesc.h"
Dylan Noblesmith	7a3973d	2012-04-03 15:48:14 +0000	[diff] [blame]	19	#include "llvm/MC/MCSubtargetInfo.h"
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	20	#include "llvm/Support/Debug.h"
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	21	#include "llvm/Support/ErrorHandling.h"
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	22	#include "llvm/Support/LEB128.h"
Evan Cheng	2bb4035	2011-08-24 18:08:43 +0000	[diff] [blame]	23	#include "llvm/Support/TargetRegistry.h"
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	24	#include "llvm/Support/raw_ostream.h"
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	25	#include <vector>
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	26
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	27	using namespace llvm;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	28
Chandler Carruth	84e68b2	2014-04-22 02:41:26 +0000	[diff] [blame]	29	#define DEBUG_TYPE "arm-disassembler"
				30
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	31	typedef MCDisassembler::DecodeStatus DecodeStatus;
				32
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	33	namespace {
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	34	// Handles the condition code status of instructions in IT blocks
				35	class ITStatus
				36	{
				37	public:
				38	// Returns the condition code for instruction in IT block
				39	unsigned getITCC() {
				40	unsigned CC = ARMCC::AL;
				41	if (instrInITBlock())
				42	CC = ITStates.back();
				43	return CC;
				44	}
				45
				46	// Advances the IT block state to the next T or E
				47	void advanceITState() {
				48	ITStates.pop_back();
				49	}
				50
				51	// Returns true if the current instruction is in an IT block
				52	bool instrInITBlock() {
				53	return !ITStates.empty();
				54	}
				55
				56	// Returns true if current instruction is the last instruction in an IT block
				57	bool instrLastInITBlock() {
				58	return ITStates.size() == 1;
				59	}
				60
				61	// Called when decoding an IT instruction. Sets the IT state for the following
Vinicius Tinti	67cf33d	2015-11-20 23:20:12 +0000	[diff] [blame]	62	// instructions that for the IT block. Firstcond and Mask correspond to the
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	63	// fields in the IT instruction encoding.
				64	void setITState(char Firstcond, char Mask) {
				65	// (3 - the number of trailing zeros) is the number of then / else.
Richard Barton	f435b09	2012-04-27 08:42:59 +0000	[diff] [blame]	66	unsigned CondBit0 = Firstcond & 1;
Michael J. Spencer	df1ecbd7	2013-05-24 22:23:49 +0000	[diff] [blame]	67	unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	68	unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
				69	assert(NumTZ <= 3 && "Invalid IT mask!");
				70	// push condition codes onto the stack the correct order for the pops
				71	for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
				72	bool T = ((Mask >> Pos) & 1) == CondBit0;
				73	if (T)
				74	ITStates.push_back(CCBits);
				75	else
				76	ITStates.push_back(CCBits ^ 1);
				77	}
				78	ITStates.push_back(CCBits);
				79	}
				80
				81	private:
				82	std::vector<unsigned char> ITStates;
				83	};
Alexander Kornienko	f00654e	2015-06-23 09:49:53 +0000	[diff] [blame]	84	}
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	85
				86	namespace {
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	87	/// ARM disassembler for all ARM platforms.
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	88	class ARMDisassembler : public MCDisassembler {
				89	public:
Lang Hames	a1bc0f5	2014-04-15 04:40:56 +0000	[diff] [blame]	90	ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
				91	MCDisassembler(STI, Ctx) {
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	92	}
				93
Alexander Kornienko	f817c1c	2015-04-11 02:11:45 +0000	[diff] [blame]	94	~ARMDisassembler() override {}
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	95
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	96	DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
Rafael Espindola	7fc5b87	2014-11-12 02:04:27 +0000	[diff] [blame]	97	ArrayRef<uint8_t> Bytes, uint64_t Address,
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	98	raw_ostream &VStream,
				99	raw_ostream &CStream) const override;
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	100	};
				101
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	102	/// Thumb disassembler for all Thumb platforms.
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	103	class ThumbDisassembler : public MCDisassembler {
				104	public:
Lang Hames	a1bc0f5	2014-04-15 04:40:56 +0000	[diff] [blame]	105	ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
				106	MCDisassembler(STI, Ctx) {
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	107	}
				108
Alexander Kornienko	f817c1c	2015-04-11 02:11:45 +0000	[diff] [blame]	109	~ThumbDisassembler() override {}
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	110
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	111	DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
Rafael Espindola	7fc5b87	2014-11-12 02:04:27 +0000	[diff] [blame]	112	ArrayRef<uint8_t> Bytes, uint64_t Address,
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	113	raw_ostream &VStream,
				114	raw_ostream &CStream) const override;
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	115
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	116	private:
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	117	mutable ITStatus ITBlock;
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	118	DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	119	void UpdateThumbVFPPredicate(MCInst&) const;
				120	};
Alexander Kornienko	f00654e	2015-06-23 09:49:53 +0000	[diff] [blame]	121	}
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	122
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	123	static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	124	switch (In) {
				125	case MCDisassembler::Success:
				126	// Out stays the same.
				127	return true;
				128	case MCDisassembler::SoftFail:
				129	Out = In;
				130	return true;
				131	case MCDisassembler::Fail:
				132	Out = In;
				133	return false;
				134	}
David Blaikie	46a9f01	2012-01-20 21:51:11 +0000	[diff] [blame]	135	llvm_unreachable("Invalid DecodeStatus!");
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	136	}
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	137
James Molloy	8067df9	2011-09-07 19:42:28 +0000	[diff] [blame]	138
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	139	// Forward declare these because the autogenerated code will reference them.
				140	// Definitions are further down.
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	141	static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	142	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	143	static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	144	unsigned RegNo, uint64_t Address,
				145	const void *Decoder);
Mihai Popa	dc1764c5	2013-05-13 14:10:04 +0000	[diff] [blame]	146	static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
				147	unsigned RegNo, uint64_t Address,
				148	const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	149	static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	150	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	151	static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	152	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	153	static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	154	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	155	static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
				156	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	157	static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	158	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	159	static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	160	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	161	static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	162	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	163	static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	164	unsigned RegNo,
				165	uint64_t Address,
				166	const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	167	static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	168	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	169	static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	170	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	171	static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	172	unsigned RegNo, uint64_t Address,
				173	const void *Decoder);
Johnny Chen	74491bb	2010-08-12 01:40:54 +0000	[diff] [blame]	174
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	175	static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	176	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	177	static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	178	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	179	static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	180	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	181	static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	182	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	183	static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	184	uint64_t Address, const void *Decoder);
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	185
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	186	static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	187	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	188	static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	189	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	190	static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	191	unsigned Insn,
				192	uint64_t Address,
				193	const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	194	static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	195	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	196	static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	197	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	198	static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	199	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	200	static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	201	uint64_t Address, const void *Decoder);
				202
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	203	static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	204	unsigned Insn,
				205	uint64_t Adddress,
				206	const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	207	static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	208	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	209	static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	210	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	211	static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	212	uint64_t Address, const void *Decoder);
Sjoerd Meijer	d906bf1	2016-06-03 14:03:27 +0000	[diff] [blame]	213	static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
				214	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	215	static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	3d2e0e9d	2011-08-09 23:05:39 +0000	[diff] [blame]	216	uint64_t Address, const void *Decoder);
Vladimir Sukharev	0e0f8d2	2015-04-16 11:34:25 +0000	[diff] [blame]	217	static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
				218	uint64_t Address, const void *Decoder);
				219	static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
				220	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	221	static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	222	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	223	static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	224	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	225	static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	226	uint64_t Address, const void *Decoder);
Oliver Stannard	65b8538	2016-01-25 10:26:26 +0000	[diff] [blame]	227	static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
				228	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	229	static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	230	uint64_t Address, const void *Decoder);
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	231	static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
				232	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	233	static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	234	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	235	static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	236	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	237	static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
				238	uint64_t Address, const void *Decoder);
				239	static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
				240	uint64_t Address, const void *Decoder);
				241	static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
				242	uint64_t Address, const void *Decoder);
				243	static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
				244	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	245	static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	246	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	247	static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	248	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	249	static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	250	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	251	static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	252	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	253	static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	254	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	255	static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	256	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	257	static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	258	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	259	static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	260	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	261	static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	262	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	263	static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	264	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	265	static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	266	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	267	static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	268	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	269	static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	270	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	271	static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	272	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	273	static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	274	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	275	static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	276	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	43cb13a	2013-06-10 14:17:08 +0000	[diff] [blame]	277	static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
				278	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	279	static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	280	uint64_t Address, const void *Decoder);
Tim Northover	ee843ef	2014-08-15 10:47:12 +0000	[diff] [blame]	281	static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn,
				282	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	283	static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	284	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	285	static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	286	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	287	static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	288	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	289	static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	290	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	291	static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	292	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	293	static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	294	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	295	static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	296	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	297	static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	298	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	299	static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	300	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	301	static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	302	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	303	static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	304	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	305	static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	306	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	307	static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	308	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	309	static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	310	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	311	static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	312	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	313	static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	314	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	315	static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Anderson	dde461c	2011-10-28 18:02:13 +0000	[diff] [blame]	316	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	317	static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	318	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	319	static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	320	uint64_t Address, const void *Decoder);
				321
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	322
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	323	static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	324	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	325	static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	326	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	327	static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	328	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	329	static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	330	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	331	static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	332	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	333	static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	334	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	335	static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	336	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	337	static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	338	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	339	static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	340	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	341	static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	342	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	343	static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
				344	uint64_t Address, const void* Decoder);
				345	static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
				346	uint64_t Address, const void* Decoder);
				347	static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
				348	uint64_t Address, const void* Decoder);
				349	static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
				350	uint64_t Address, const void* Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	351	static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	352	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	353	static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	354	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	355	static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbach	a05627e	2011-09-09 18:37:27 +0000	[diff] [blame]	356	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	357	static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	358	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	359	static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	360	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	361	static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	362	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	363	static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	364	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	365	static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	366	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	631df63	2013-06-08 13:38:52 +0000	[diff] [blame]	367	static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
				368	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	369	static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	370	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	371	static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	372	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	373	static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
Jim Grosbach	05541f4	2011-09-19 22:21:13 +0000	[diff] [blame]	374	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	375	static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	376	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	377	static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	378	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	379	static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	380	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	381	static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	382	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	383	static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
Owen Anderson	37612a3	2011-08-24 22:40:22 +0000	[diff] [blame]	384	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	385	static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	386	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	387	static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	388	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	389	static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	390	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	391	static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	392	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	393	static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	f01e2de	2011-09-26 21:06:22 +0000	[diff] [blame]	394	uint64_t Address, const void *Decoder);
				395
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	396	static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	397	uint64_t Address, const void *Decoder);
Ranjeet Singh	39d2d09	2016-06-17 00:52:41 +0000	[diff] [blame]	398	static DecodeStatus DecoderForMRRC2AndMCRR2(llvm::MCInst &Inst, unsigned Val,
				399	uint64_t Address, const void *Decoder);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	400	#include "ARMGenDisassemblerTables.inc"
Sean Callanan	814e69b	2010-04-13 21:21:57 +0000	[diff] [blame]	401
Lang Hames	a1bc0f5	2014-04-15 04:40:56 +0000	[diff] [blame]	402	static MCDisassembler *createARMDisassembler(const Target &T,
				403	const MCSubtargetInfo &STI,
				404	MCContext &Ctx) {
				405	return new ARMDisassembler(STI, Ctx);
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	406	}
				407
Lang Hames	a1bc0f5	2014-04-15 04:40:56 +0000	[diff] [blame]	408	static MCDisassembler *createThumbDisassembler(const Target &T,
				409	const MCSubtargetInfo &STI,
				410	MCContext &Ctx) {
				411	return new ThumbDisassembler(STI, Ctx);
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	412	}
				413
Charlie Turner	30895f9	2014-12-01 08:50:27 +0000	[diff] [blame]	414	// Post-decoding checks
				415	static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size,
				416	uint64_t Address, raw_ostream &OS,
				417	raw_ostream &CS,
				418	uint32_t Insn,
				419	DecodeStatus Result)
				420	{
				421	switch (MI.getOpcode()) {
				422	case ARM::HVC: {
				423	// HVC is undefined if condition = 0xf otherwise upredictable
				424	// if condition != 0xe
				425	uint32_t Cond = (Insn >> 28) & 0xF;
				426	if (Cond == 0xF)
				427	return MCDisassembler::Fail;
				428	if (Cond != 0xE)
				429	return MCDisassembler::SoftFail;
				430	return Result;
				431	}
				432	default: return Result;
				433	}
				434	}
				435
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	436	DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Rafael Espindola	7fc5b87	2014-11-12 02:04:27 +0000	[diff] [blame]	437	ArrayRef<uint8_t> Bytes,
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	438	uint64_t Address, raw_ostream &OS,
				439	raw_ostream &CS) const {
				440	CommentStream = &CS;
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	441
Michael Kuperstein	db0712f	2015-05-26 10:47:10 +0000	[diff] [blame]	442	assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	443	"Asked to disassemble an ARM instruction but Subtarget is in Thumb "
				444	"mode!");
James Molloy	8067df9	2011-09-07 19:42:28 +0000	[diff] [blame]	445
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	446	// We want to read exactly 4 bytes of data.
Rafael Espindola	7fc5b87	2014-11-12 02:04:27 +0000	[diff] [blame]	447	if (Bytes.size() < 4) {
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	448	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	449	return MCDisassembler::Fail;
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	450	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	451
				452	// Encoded as a small-endian 32-bit word in the stream.
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	453	uint32_t Insn =
				454	(Bytes[3] << 24) \| (Bytes[2] << 16) \| (Bytes[1] << 8) \| (Bytes[0] << 0);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	455
				456	// Calling the auto-generated decoder function.
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	457	DecodeStatus Result =
				458	decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI);
				459	if (Result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	460	Size = 4;
Charlie Turner	30895f9	2014-12-01 08:50:27 +0000	[diff] [blame]	461	return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	462	}
				463
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	464	// VFP and NEON instructions, similarly, are shared between ARM
				465	// and Thumb modes.
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	466	Result = decodeInstruction(DecoderTableVFP32, MI, Insn, Address, this, STI);
				467	if (Result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	468	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	469	return Result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	470	}
				471
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	472	Result = decodeInstruction(DecoderTableVFPV832, MI, Insn, Address, this, STI);
				473	if (Result != MCDisassembler::Fail) {
Joey Gouly	cc4ff9e	2013-07-04 14:57:20 +0000	[diff] [blame]	474	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	475	return Result;
Joey Gouly	cc4ff9e	2013-07-04 14:57:20 +0000	[diff] [blame]	476	}
				477
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	478	Result =
				479	decodeInstruction(DecoderTableNEONData32, MI, Insn, Address, this, STI);
				480	if (Result != MCDisassembler::Fail) {
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	481	Size = 4;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	482	// Add a fake predicate operand, because we share these instruction
				483	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	484	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				485	return MCDisassembler::Fail;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	486	return Result;
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	487	}
				488
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	489	Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, Insn, Address,
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	490	this, STI);
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	491	if (Result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	492	Size = 4;
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	493	// Add a fake predicate operand, because we share these instruction
				494	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	495	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				496	return MCDisassembler::Fail;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	497	return Result;
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	498	}
				499
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	500	Result =
				501	decodeInstruction(DecoderTableNEONDup32, MI, Insn, Address, this, STI);
				502	if (Result != MCDisassembler::Fail) {
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	503	Size = 4;
				504	// Add a fake predicate operand, because we share these instruction
				505	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	506	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				507	return MCDisassembler::Fail;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	508	return Result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	509	}
				510
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	511	Result =
				512	decodeInstruction(DecoderTablev8NEON32, MI, Insn, Address, this, STI);
				513	if (Result != MCDisassembler::Fail) {
Joey Gouly	df68600	2013-07-17 13:59:38 +0000	[diff] [blame]	514	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	515	return Result;
Joey Gouly	df68600	2013-07-17 13:59:38 +0000	[diff] [blame]	516	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	517
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	518	Result =
				519	decodeInstruction(DecoderTablev8Crypto32, MI, Insn, Address, this, STI);
				520	if (Result != MCDisassembler::Fail) {
Amara Emerson	3308909	2013-09-19 11:59:01 +0000	[diff] [blame]	521	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	522	return Result;
Amara Emerson	3308909	2013-09-19 11:59:01 +0000	[diff] [blame]	523	}
				524
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	525	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	526	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	527	}
				528
				529	namespace llvm {
Benjamin Kramer	0d6d098	2011-10-22 16:50:00 +0000	[diff] [blame]	530	extern const MCInstrDesc ARMInsts[];
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	531	}
				532
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	533	/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
				534	/// immediate Value in the MCInst. The immediate Value has had any PC
				535	/// adjustment made by the caller. If the instruction is a branch instruction
				536	/// then isBranch is true, else false. If the getOpInfo() function was set as
				537	/// part of the setupForSymbolicDisassembly() call then that function is called
				538	/// to get any symbolic information at the Address for this instruction. If
				539	/// that returns non-zero then the symbolic information it returns is used to
				540	/// create an MCExpr and that is added as an operand to the MCInst. If
				541	/// getOpInfo() returns zero and isBranch is true then a symbol look up for
				542	/// Value is done and if a symbol is found an MCExpr is created with that, else
				543	/// an MCExpr with Value is created. This function returns true if it adds an
				544	/// operand to the MCInst and false otherwise.
				545	static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
				546	bool isBranch, uint64_t InstSize,
				547	MCInst &MI, const void *Decoder) {
				548	const MCDisassembler Dis = static_cast<const MCDisassembler>(Decoder);
Ahmed Bougacha	ad1084d	2013-05-24 00:39:57 +0000	[diff] [blame]	549	// FIXME: Does it make sense for value to be negative?
				550	return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
				551	/* Offset */ 0, InstSize);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	552	}
				553
				554	/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
				555	/// referenced by a load instruction with the base register that is the Pc.
				556	/// These can often be values in a literal pool near the Address of the
				557	/// instruction. The Address of the instruction and its immediate Value are
				558	/// used as a possible literal pool entry. The SymbolLookUp call back will
Sylvestre Ledru	35521e2	2012-07-23 08:51:15 +0000	[diff] [blame]	559	/// return the name of a symbol referenced by the literal pool's entry if
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	560	/// the referenced address is that of a symbol. Or it will return a pointer to
				561	/// a literal 'C' string if the referenced address of the literal pool's entry
				562	/// is an address into a section with 'C' string literals.
				563	static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
Kevin Enderby	6fbcd8d	2012-02-23 18:18:17 +0000	[diff] [blame]	564	const void *Decoder) {
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	565	const MCDisassembler Dis = static_cast<const MCDisassembler>(Decoder);
Ahmed Bougacha	ad1084d	2013-05-24 00:39:57 +0000	[diff] [blame]	566	Dis->tryAddingPcLoadReferenceComment(Value, Address);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	567	}
				568
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	569	// Thumb1 instructions don't have explicit S bits. Rather, they
				570	// implicitly set CPSR. Since it's not represented in the encoding, the
				571	// auto-generated decoder won't inject the CPSR operand. We need to fix
				572	// that as a post-pass.
				573	static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
				574	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	575	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	576	MCInst::iterator I = MI.begin();
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	577	for (unsigned i = 0; i < NumOps; ++i, ++I) {
				578	if (I == MI.end()) break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	579	if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	580	if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	581	MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	582	return;
				583	}
				584	}
				585
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	586	MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	587	}
				588
				589	// Most Thumb instructions don't have explicit predicates in the
				590	// encoding, but rather get their predicates from IT context. We need
				591	// to fix up the predicate operands using this context information as a
				592	// post-pass.
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	593	MCDisassembler::DecodeStatus
				594	ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	595	MCDisassembler::DecodeStatus S = Success;
				596
Sjoerd Meijer	d906bf1	2016-06-03 14:03:27 +0000	[diff] [blame]	597	const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits();
				598
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	599	// A few instructions actually have predicates encoded in them. Don't
				600	// try to overwrite it if we're seeing one of those.
				601	switch (MI.getOpcode()) {
				602	case ARM::tBcc:
				603	case ARM::t2Bcc:
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	604	case ARM::tCBZ:
				605	case ARM::tCBNZ:
Owen Anderson	61e4604	2011-09-19 23:47:10 +0000	[diff] [blame]	606	case ARM::tCPS:
				607	case ARM::t2CPS3p:
				608	case ARM::t2CPS2p:
				609	case ARM::t2CPS1p:
Owen Anderson	163be01	2011-09-19 23:57:20 +0000	[diff] [blame]	610	case ARM::tMOVSr:
Owen Anderson	44f76ea	2011-10-13 17:58:39 +0000	[diff] [blame]	611	case ARM::tSETEND:
Owen Anderson	33d3953	2011-09-08 22:48:37 +0000	[diff] [blame]	612	// Some instructions (mostly conditional branches) are not
				613	// allowed in IT blocks.
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	614	if (ITBlock.instrInITBlock())
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	615	S = SoftFail;
				616	else
				617	return Success;
				618	break;
Sjoerd Meijer	d906bf1	2016-06-03 14:03:27 +0000	[diff] [blame]	619	case ARM::t2HINT:
				620	if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)
				621	S = SoftFail;
				622	break;
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	623	case ARM::tB:
				624	case ARM::t2B:
Owen Anderson	f902d92	2011-09-19 22:34:23 +0000	[diff] [blame]	625	case ARM::t2TBB:
				626	case ARM::t2TBH:
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	627	// Some instructions (mostly unconditional branches) can
				628	// only appears at the end of, or outside of, an IT.
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	629	if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	630	S = SoftFail;
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	631	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	632	default:
				633	break;
				634	}
				635
				636	// If we're in an IT block, base the predicate on that. Otherwise,
				637	// assume a predicate of AL.
				638	unsigned CC;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	639	CC = ITBlock.getITCC();
				640	if (CC == 0xF)
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	641	CC = ARMCC::AL;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	642	if (ITBlock.instrInITBlock())
				643	ITBlock.advanceITState();
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	644
				645	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	646	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	647	MCInst::iterator I = MI.begin();
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	648	for (unsigned i = 0; i < NumOps; ++i, ++I) {
				649	if (I == MI.end()) break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	650	if (OpInfo[i].isPredicate()) {
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	651	I = MI.insert(I, MCOperand::createImm(CC));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	652	++I;
				653	if (CC == ARMCC::AL)
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	654	MI.insert(I, MCOperand::createReg(0));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	655	else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	656	MI.insert(I, MCOperand::createReg(ARM::CPSR));
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	657	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	658	}
				659	}
				660
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	661	I = MI.insert(I, MCOperand::createImm(CC));
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	662	++I;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	663	if (CC == ARMCC::AL)
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	664	MI.insert(I, MCOperand::createReg(0));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	665	else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	666	MI.insert(I, MCOperand::createReg(ARM::CPSR));
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	667
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	668	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	669	}
				670
				671	// Thumb VFP instructions are a special case. Because we share their
				672	// encodings between ARM and Thumb modes, and they are predicable in ARM
				673	// mode, the auto-generated decoder will give them an (incorrect)
				674	// predicate operand. We need to rewrite these operands based on the IT
				675	// context as a post-pass.
				676	void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
				677	unsigned CC;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	678	CC = ITBlock.getITCC();
				679	if (ITBlock.instrInITBlock())
				680	ITBlock.advanceITState();
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	681
				682	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
				683	MCInst::iterator I = MI.begin();
Owen Anderson	216cfaa	2011-08-24 21:35:46 +0000	[diff] [blame]	684	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
				685	for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	686	if (OpInfo[i].isPredicate() ) {
				687	I->setImm(CC);
				688	++I;
				689	if (CC == ARMCC::AL)
				690	I->setReg(0);
				691	else
				692	I->setReg(ARM::CPSR);
				693	return;
				694	}
				695	}
				696	}
				697
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	698	DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Rafael Espindola	7fc5b87	2014-11-12 02:04:27 +0000	[diff] [blame]	699	ArrayRef<uint8_t> Bytes,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	700	uint64_t Address,
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	701	raw_ostream &OS,
				702	raw_ostream &CS) const {
				703	CommentStream = &CS;
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	704
Michael Kuperstein	db0712f	2015-05-26 10:47:10 +0000	[diff] [blame]	705	assert(STI.getFeatureBits()[ARM::ModeThumb] &&
James Molloy	8067df9	2011-09-07 19:42:28 +0000	[diff] [blame]	706	"Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
				707
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	708	// We want to read exactly 2 bytes of data.
Rafael Espindola	7fc5b87	2014-11-12 02:04:27 +0000	[diff] [blame]	709	if (Bytes.size() < 2) {
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	710	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	711	return MCDisassembler::Fail;
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	712	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	713
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	714	uint16_t Insn16 = (Bytes[1] << 8) \| Bytes[0];
				715	DecodeStatus Result =
				716	decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI);
				717	if (Result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	718	Size = 2;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	719	Check(Result, AddThumbPredicate(MI));
				720	return Result;
Owen Anderson	91a8f9b	2011-08-16 23:45:44 +0000	[diff] [blame]	721	}
				722
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	723	Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this,
				724	STI);
				725	if (Result) {
Owen Anderson	91a8f9b	2011-08-16 23:45:44 +0000	[diff] [blame]	726	Size = 2;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	727	bool InITBlock = ITBlock.instrInITBlock();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	728	Check(Result, AddThumbPredicate(MI));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	729	AddThumb1SBit(MI, InITBlock);
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	730	return Result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	731	}
				732
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	733	Result =
				734	decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI);
				735	if (Result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	736	Size = 2;
Owen Anderson	6a5c150	2011-10-06 23:33:11 +0000	[diff] [blame]	737
				738	// Nested IT blocks are UNPREDICTABLE. Must be checked before we add
				739	// the Thumb predicate.
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	740	if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	741	Result = MCDisassembler::SoftFail;
Owen Anderson	6a5c150	2011-10-06 23:33:11 +0000	[diff] [blame]	742
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	743	Check(Result, AddThumbPredicate(MI));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	744
				745	// If we find an IT instruction, we need to parse its condition
				746	// code and mask operands so that we can apply them correctly
				747	// to the subsequent instructions.
				748	if (MI.getOpcode() == ARM::t2IT) {
Owen Anderson	f1e3844	2011-09-14 21:06:21 +0000	[diff] [blame]	749
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	750	unsigned Firstcond = MI.getOperand(0).getImm();
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	751	unsigned Mask = MI.getOperand(1).getImm();
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	752	ITBlock.setITState(Firstcond, Mask);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	753	}
				754
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	755	return Result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	756	}
				757
				758	// We want to read exactly 4 bytes of data.
Rafael Espindola	7fc5b87	2014-11-12 02:04:27 +0000	[diff] [blame]	759	if (Bytes.size() < 4) {
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	760	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	761	return MCDisassembler::Fail;
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	762	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	763
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	764	uint32_t Insn32 =
				765	(Bytes[3] << 8) \| (Bytes[2] << 0) \| (Bytes[1] << 24) \| (Bytes[0] << 16);
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	766	Result =
				767	decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI);
				768	if (Result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	769	Size = 4;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	770	bool InITBlock = ITBlock.instrInITBlock();
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	771	Check(Result, AddThumbPredicate(MI));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	772	AddThumb1SBit(MI, InITBlock);
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	773	return Result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	774	}
				775
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	776	Result =
				777	decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI);
				778	if (Result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	779	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	780	Check(Result, AddThumbPredicate(MI));
				781	return Result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	782	}
				783
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	784	if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	785	Result =
				786	decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI);
				787	if (Result != MCDisassembler::Fail) {
Amaury de la Vieuville	8449c0d	2013-06-24 09:15:01 +0000	[diff] [blame]	788	Size = 4;
				789	UpdateThumbVFPPredicate(MI);
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	790	return Result;
Amaury de la Vieuville	8449c0d	2013-06-24 09:15:01 +0000	[diff] [blame]	791	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	792	}
				793
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	794	Result =
				795	decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI);
				796	if (Result != MCDisassembler::Fail) {
Joey Gouly	cc4ff9e	2013-07-04 14:57:20 +0000	[diff] [blame]	797	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	798	return Result;
Joey Gouly	cc4ff9e	2013-07-04 14:57:20 +0000	[diff] [blame]	799	}
				800
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	801	if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	802	Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this,
				803	STI);
				804	if (Result != MCDisassembler::Fail) {
Amaury de la Vieuville	8449c0d	2013-06-24 09:15:01 +0000	[diff] [blame]	805	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	806	Check(Result, AddThumbPredicate(MI));
				807	return Result;
Amaury de la Vieuville	8449c0d	2013-06-24 09:15:01 +0000	[diff] [blame]	808	}
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	809	}
				810
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	811	if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	812	uint32_t NEONLdStInsn = Insn32;
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	813	NEONLdStInsn &= 0xF0FFFFFF;
				814	NEONLdStInsn \|= 0x04000000;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	815	Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	816	Address, this, STI);
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	817	if (Result != MCDisassembler::Fail) {
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	818	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	819	Check(Result, AddThumbPredicate(MI));
				820	return Result;
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	821	}
				822	}
				823
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	824	if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	825	uint32_t NEONDataInsn = Insn32;
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	826	NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
				827	NEONDataInsn \|= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
				828	NEONDataInsn \|= 0x12000000; // Set bits 28 and 25
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	829	Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	830	Address, this, STI);
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	831	if (Result != MCDisassembler::Fail) {
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	832	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	833	Check(Result, AddThumbPredicate(MI));
				834	return Result;
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	835	}
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	836
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	837	uint32_t NEONCryptoInsn = Insn32;
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	838	NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
				839	NEONCryptoInsn \|= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
				840	NEONCryptoInsn \|= 0x12000000; // Set bits 28 and 25
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	841	Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	842	Address, this, STI);
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	843	if (Result != MCDisassembler::Fail) {
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	844	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	845	return Result;
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	846	}
Amara Emerson	3308909	2013-09-19 11:59:01 +0000	[diff] [blame]	847
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	848	uint32_t NEONv8Insn = Insn32;
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	849	NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	850	Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	851	this, STI);
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	852	if (Result != MCDisassembler::Fail) {
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	853	Size = 4;
Rafael Espindola	4aa6bea	2014-11-10 18:11:10 +0000	[diff] [blame]	854	return Result;
Artyom Skrobov	c1be9c1	2013-10-30 18:10:09 +0000	[diff] [blame]	855	}
Joey Gouly	df68600	2013-07-17 13:59:38 +0000	[diff] [blame]	856	}
				857
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	858	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	859	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	860	}
				861
				862
				863	extern "C" void LLVMInitializeARMDisassembler() {
Mehdi Amini	f42454b	2016-10-09 23:00:34 +0000	[diff] [blame^]	864	TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(),
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	865	createARMDisassembler);
Mehdi Amini	f42454b	2016-10-09 23:00:34 +0000	[diff] [blame^]	866	TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(),
Christian Pirker	2a11160	2014-03-28 14:35:30 +0000	[diff] [blame]	867	createARMDisassembler);
Mehdi Amini	f42454b	2016-10-09 23:00:34 +0000	[diff] [blame^]	868	TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(),
Christian Pirker	2a11160	2014-03-28 14:35:30 +0000	[diff] [blame]	869	createThumbDisassembler);
Mehdi Amini	f42454b	2016-10-09 23:00:34 +0000	[diff] [blame^]	870	TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(),
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	871	createThumbDisassembler);
				872	}
				873
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	874	static const uint16_t GPRDecoderTable[] = {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	875	ARM::R0, ARM::R1, ARM::R2, ARM::R3,
				876	ARM::R4, ARM::R5, ARM::R6, ARM::R7,
				877	ARM::R8, ARM::R9, ARM::R10, ARM::R11,
				878	ARM::R12, ARM::SP, ARM::LR, ARM::PC
				879	};
				880
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	881	static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	882	uint64_t Address, const void *Decoder) {
				883	if (RegNo > 15)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	884	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	885
				886	unsigned Register = GPRDecoderTable[RegNo];
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	887	Inst.addOperand(MCOperand::createReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	888	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	889	}
				890
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	891	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	892	DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	893	uint64_t Address, const void *Decoder) {
Silviu Baranga	32a4933	2012-03-20 15:54:56 +0000	[diff] [blame]	894	DecodeStatus S = MCDisassembler::Success;
Vinicius Tinti	67cf33d	2015-11-20 23:20:12 +0000	[diff] [blame]	895
Silviu Baranga	32a4933	2012-03-20 15:54:56 +0000	[diff] [blame]	896	if (RegNo == 15)
				897	S = MCDisassembler::SoftFail;
				898
				899	Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
				900
				901	return S;
Owen Anderson	042619f	2011-08-09 22:48:45 +0000	[diff] [blame]	902	}
				903
Mihai Popa	dc1764c5	2013-05-13 14:10:04 +0000	[diff] [blame]	904	static DecodeStatus
				905	DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
				906	uint64_t Address, const void *Decoder) {
				907	DecodeStatus S = MCDisassembler::Success;
				908
				909	if (RegNo == 15)
				910	{
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	911	Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
Mihai Popa	dc1764c5	2013-05-13 14:10:04 +0000	[diff] [blame]	912	return MCDisassembler::Success;
				913	}
				914
				915	Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
				916	return S;
				917	}
				918
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	919	static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	920	uint64_t Address, const void *Decoder) {
				921	if (RegNo > 7)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	922	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	923	return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
				924	}
				925
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	926	static const uint16_t GPRPairDecoderTable[] = {
				927	ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
				928	ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
				929	};
				930
				931	static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
				932	uint64_t Address, const void *Decoder) {
				933	DecodeStatus S = MCDisassembler::Success;
				934
				935	if (RegNo > 13)
				936	return MCDisassembler::Fail;
				937
				938	if ((RegNo & 1) \|\| RegNo == 0xe)
				939	S = MCDisassembler::SoftFail;
				940
				941	unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	942	Inst.addOperand(MCOperand::createReg(RegisterPair));
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	943	return S;
				944	}
				945
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	946	static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	947	uint64_t Address, const void *Decoder) {
				948	unsigned Register = 0;
				949	switch (RegNo) {
				950	case 0:
				951	Register = ARM::R0;
				952	break;
				953	case 1:
				954	Register = ARM::R1;
				955	break;
				956	case 2:
				957	Register = ARM::R2;
				958	break;
				959	case 3:
				960	Register = ARM::R3;
				961	break;
				962	case 9:
				963	Register = ARM::R9;
				964	break;
				965	case 12:
				966	Register = ARM::R12;
				967	break;
				968	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	969	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	970	}
				971
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	972	Inst.addOperand(MCOperand::createReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	973	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	974	}
				975
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	976	static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	977	uint64_t Address, const void *Decoder) {
Amaury de la Vieuville	8175bda	2013-06-24 09:14:54 +0000	[diff] [blame]	978	DecodeStatus S = MCDisassembler::Success;
Artyom Skrobov	b4398107	2015-10-28 13:58:36 +0000	[diff] [blame]	979
				980	const FeatureBitset &featureBits =
				981	((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
				982
				983	if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) \|\| RegNo == 15)
Amaury de la Vieuville	8175bda	2013-06-24 09:14:54 +0000	[diff] [blame]	984	S = MCDisassembler::SoftFail;
Artyom Skrobov	b4398107	2015-10-28 13:58:36 +0000	[diff] [blame]	985
Amaury de la Vieuville	8175bda	2013-06-24 09:14:54 +0000	[diff] [blame]	986	Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
				987	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	988	}
				989
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	990	static const uint16_t SPRDecoderTable[] = {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	991	ARM::S0, ARM::S1, ARM::S2, ARM::S3,
				992	ARM::S4, ARM::S5, ARM::S6, ARM::S7,
				993	ARM::S8, ARM::S9, ARM::S10, ARM::S11,
				994	ARM::S12, ARM::S13, ARM::S14, ARM::S15,
				995	ARM::S16, ARM::S17, ARM::S18, ARM::S19,
				996	ARM::S20, ARM::S21, ARM::S22, ARM::S23,
				997	ARM::S24, ARM::S25, ARM::S26, ARM::S27,
				998	ARM::S28, ARM::S29, ARM::S30, ARM::S31
				999	};
				1000
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1001	static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1002	uint64_t Address, const void *Decoder) {
				1003	if (RegNo > 31)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1004	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1005
				1006	unsigned Register = SPRDecoderTable[RegNo];
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1007	Inst.addOperand(MCOperand::createReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1008	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1009	}
				1010
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	1011	static const uint16_t DPRDecoderTable[] = {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1012	ARM::D0, ARM::D1, ARM::D2, ARM::D3,
				1013	ARM::D4, ARM::D5, ARM::D6, ARM::D7,
				1014	ARM::D8, ARM::D9, ARM::D10, ARM::D11,
				1015	ARM::D12, ARM::D13, ARM::D14, ARM::D15,
				1016	ARM::D16, ARM::D17, ARM::D18, ARM::D19,
				1017	ARM::D20, ARM::D21, ARM::D22, ARM::D23,
				1018	ARM::D24, ARM::D25, ARM::D26, ARM::D27,
				1019	ARM::D28, ARM::D29, ARM::D30, ARM::D31
				1020	};
				1021
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1022	static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1023	uint64_t Address, const void *Decoder) {
Michael Kuperstein	db0712f	2015-05-26 10:47:10 +0000	[diff] [blame]	1024	const FeatureBitset &featureBits =
				1025	((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
				1026
				1027	bool hasD16 = featureBits[ARM::FeatureD16];
Oliver Stannard	9e89d8c	2014-11-05 12:06:39 +0000	[diff] [blame]	1028
				1029	if (RegNo > 31 \|\| (hasD16 && RegNo > 15))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1030	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1031
				1032	unsigned Register = DPRDecoderTable[RegNo];
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1033	Inst.addOperand(MCOperand::createReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1034	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1035	}
				1036
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1037	static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1038	uint64_t Address, const void *Decoder) {
				1039	if (RegNo > 7)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1040	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1041	return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
				1042	}
				1043
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1044	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1045	DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	1046	uint64_t Address, const void *Decoder) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1047	if (RegNo > 15)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1048	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1049	return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
				1050	}
				1051
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	1052	static const uint16_t QPRDecoderTable[] = {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1053	ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
				1054	ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
				1055	ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
				1056	ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
				1057	};
				1058
				1059
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1060	static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1061	uint64_t Address, const void *Decoder) {
Mihai Popa	dcf0922	2013-05-20 14:42:43 +0000	[diff] [blame]	1062	if (RegNo > 31 \|\| (RegNo & 1) != 0)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1063	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1064	RegNo >>= 1;
				1065
				1066	unsigned Register = QPRDecoderTable[RegNo];
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1067	Inst.addOperand(MCOperand::createReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1068	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1069	}
				1070
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	1071	static const uint16_t DPairDecoderTable[] = {
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	1072	ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
				1073	ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
				1074	ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
				1075	ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
				1076	ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
				1077	ARM::Q15
				1078	};
				1079
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1080	static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	1081	uint64_t Address, const void *Decoder) {
				1082	if (RegNo > 30)
				1083	return MCDisassembler::Fail;
				1084
				1085	unsigned Register = DPairDecoderTable[RegNo];
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1086	Inst.addOperand(MCOperand::createReg(Register));
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	1087	return MCDisassembler::Success;
				1088	}
				1089
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	1090	static const uint16_t DPairSpacedDecoderTable[] = {
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	1091	ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
				1092	ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
				1093	ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
				1094	ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
				1095	ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
				1096	ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
				1097	ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
				1098	ARM::D28_D30, ARM::D29_D31
				1099	};
				1100
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1101	static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	1102	unsigned RegNo,
				1103	uint64_t Address,
				1104	const void *Decoder) {
				1105	if (RegNo > 29)
				1106	return MCDisassembler::Fail;
				1107
				1108	unsigned Register = DPairSpacedDecoderTable[RegNo];
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1109	Inst.addOperand(MCOperand::createReg(Register));
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	1110	return MCDisassembler::Success;
				1111	}
				1112
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1113	static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1114	uint64_t Address, const void *Decoder) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1115	if (Val == 0xF) return MCDisassembler::Fail;
Owen Anderson	7a2401d	2011-08-09 21:07:45 +0000	[diff] [blame]	1116	// AL predicate is not allowed on Thumb1 branches.
				1117	if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1118	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1119	Inst.addOperand(MCOperand::createImm(Val));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1120	if (Val == ARMCC::AL) {
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1121	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1122	} else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1123	Inst.addOperand(MCOperand::createReg(ARM::CPSR));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1124	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1125	}
				1126
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1127	static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1128	uint64_t Address, const void *Decoder) {
				1129	if (Val)
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1130	Inst.addOperand(MCOperand::createReg(ARM::CPSR));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1131	else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1132	Inst.addOperand(MCOperand::createReg(0));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1133	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1134	}
				1135
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1136	static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1137	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1138	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1139
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1140	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				1141	unsigned type = fieldFromInstruction(Val, 5, 2);
				1142	unsigned imm = fieldFromInstruction(Val, 7, 5);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1143
				1144	// Register-immediate
Artyom Skrobov	b4398107	2015-10-28 13:58:36 +0000	[diff] [blame]	1145	if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1146	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1147
				1148	ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
				1149	switch (type) {
				1150	case 0:
				1151	Shift = ARM_AM::lsl;
				1152	break;
				1153	case 1:
				1154	Shift = ARM_AM::lsr;
				1155	break;
				1156	case 2:
				1157	Shift = ARM_AM::asr;
				1158	break;
				1159	case 3:
				1160	Shift = ARM_AM::ror;
				1161	break;
				1162	}
				1163
				1164	if (Shift == ARM_AM::ror && imm == 0)
				1165	Shift = ARM_AM::rrx;
				1166
				1167	unsigned Op = Shift \| (imm << 3);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1168	Inst.addOperand(MCOperand::createImm(Op));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1169
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1170	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1171	}
				1172
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1173	static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1174	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1175	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1176
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1177	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				1178	unsigned type = fieldFromInstruction(Val, 5, 2);
				1179	unsigned Rs = fieldFromInstruction(Val, 8, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1180
				1181	// Register-register
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1182	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1183	return MCDisassembler::Fail;
				1184	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
				1185	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1186
				1187	ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
				1188	switch (type) {
				1189	case 0:
				1190	Shift = ARM_AM::lsl;
				1191	break;
				1192	case 1:
				1193	Shift = ARM_AM::lsr;
				1194	break;
				1195	case 2:
				1196	Shift = ARM_AM::asr;
				1197	break;
				1198	case 3:
				1199	Shift = ARM_AM::ror;
				1200	break;
				1201	}
				1202
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1203	Inst.addOperand(MCOperand::createImm(Shift));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1204
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1205	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1206	}
				1207
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1208	static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1209	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1210	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1211
Tim Northover	08a8660	2013-10-22 19:00:39 +0000	[diff] [blame]	1212	bool NeedDisjointWriteback = false;
				1213	unsigned WritebackReg = 0;
Owen Anderson	53db43b	2011-09-09 23:13:33 +0000	[diff] [blame]	1214	switch (Inst.getOpcode()) {
Tim Northover	08a8660	2013-10-22 19:00:39 +0000	[diff] [blame]	1215	default:
				1216	break;
				1217	case ARM::LDMIA_UPD:
				1218	case ARM::LDMDB_UPD:
				1219	case ARM::LDMIB_UPD:
				1220	case ARM::LDMDA_UPD:
				1221	case ARM::t2LDMIA_UPD:
				1222	case ARM::t2LDMDB_UPD:
				1223	case ARM::t2STMIA_UPD:
				1224	case ARM::t2STMDB_UPD:
				1225	NeedDisjointWriteback = true;
				1226	WritebackReg = Inst.getOperand(0).getReg();
				1227	break;
Owen Anderson	53db43b	2011-09-09 23:13:33 +0000	[diff] [blame]	1228	}
				1229
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	1230	// Empty register lists are not allowed.
Benjamin Kramer	8bad66e	2013-05-19 22:01:57 +0000	[diff] [blame]	1231	if (Val == 0) return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1232	for (unsigned i = 0; i < 16; ++i) {
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1233	if (Val & (1 << i)) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1234	if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
				1235	return MCDisassembler::Fail;
Owen Anderson	53db43b	2011-09-09 23:13:33 +0000	[diff] [blame]	1236	// Writeback not allowed if Rn is in the target list.
Tim Northover	08a8660	2013-10-22 19:00:39 +0000	[diff] [blame]	1237	if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
Owen Anderson	53db43b	2011-09-09 23:13:33 +0000	[diff] [blame]	1238	Check(S, MCDisassembler::SoftFail);
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1239	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1240	}
				1241
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1242	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1243	}
				1244
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1245	static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1246	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1247	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1248
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1249	unsigned Vd = fieldFromInstruction(Val, 8, 5);
				1250	unsigned regs = fieldFromInstruction(Val, 0, 8);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1251
Tim Northover	4173e29	2013-05-31 15:55:51 +0000	[diff] [blame]	1252	// In case of unpredictable encoding, tweak the operands.
				1253	if (regs == 0 \|\| (Vd + regs) > 32) {
				1254	regs = Vd + regs > 32 ? 32 - Vd : regs;
				1255	regs = std::max( 1u, regs);
				1256	S = MCDisassembler::SoftFail;
				1257	}
				1258
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1259	if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
				1260	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1261	for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1262	if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
				1263	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1264	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1265
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1266	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1267	}
				1268
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1269	static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1270	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1271	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1272
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1273	unsigned Vd = fieldFromInstruction(Val, 8, 5);
Tim Northover	4173e29	2013-05-31 15:55:51 +0000	[diff] [blame]	1274	unsigned regs = fieldFromInstruction(Val, 1, 7);
Silviu Baranga	9560af8	2012-05-03 16:38:40 +0000	[diff] [blame]	1275
Tim Northover	4173e29	2013-05-31 15:55:51 +0000	[diff] [blame]	1276	// In case of unpredictable encoding, tweak the operands.
				1277	if (regs == 0 \|\| regs > 16 \|\| (Vd + regs) > 32) {
				1278	regs = Vd + regs > 32 ? 32 - Vd : regs;
				1279	regs = std::max( 1u, regs);
				1280	regs = std::min(16u, regs);
				1281	S = MCDisassembler::SoftFail;
				1282	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1283
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1284	if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
				1285	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1286	for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1287	if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
				1288	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1289	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1290
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1291	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1292	}
				1293
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1294	static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1295	uint64_t Address, const void *Decoder) {
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	1296	// This operand encodes a mask of contiguous zeros between a specified MSB
				1297	// and LSB. To decode it, we create the mask of all bits MSB-and-lower,
				1298	// the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	1299	// the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	1300	// create the final mask.
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1301	unsigned msb = fieldFromInstruction(Val, 5, 5);
				1302	unsigned lsb = fieldFromInstruction(Val, 0, 5);
Owen Anderson	3ca958c	2011-09-16 22:29:48 +0000	[diff] [blame]	1303
Owen Anderson	502cd9d	2011-09-16 23:30:01 +0000	[diff] [blame]	1304	DecodeStatus S = MCDisassembler::Success;
Kevin Enderby	136d674	2012-11-29 23:47:11 +0000	[diff] [blame]	1305	if (lsb > msb) {
				1306	Check(S, MCDisassembler::SoftFail);
				1307	// The check above will cause the warning for the "potentially undefined
				1308	// instruction encoding" but we can't build a bad MCOperand value here
				1309	// with a lsb > msb or else printing the MCInst will cause a crash.
				1310	lsb = msb;
				1311	}
Owen Anderson	502cd9d	2011-09-16 23:30:01 +0000	[diff] [blame]	1312
Owen Anderson	b925e93	2011-09-16 23:04:48 +0000	[diff] [blame]	1313	uint32_t msb_mask = 0xFFFFFFFF;
				1314	if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
				1315	uint32_t lsb_mask = (1U << lsb) - 1;
Owen Anderson	3ca958c	2011-09-16 22:29:48 +0000	[diff] [blame]	1316
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1317	Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask)));
Owen Anderson	502cd9d	2011-09-16 23:30:01 +0000	[diff] [blame]	1318	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1319	}
				1320
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1321	static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1322	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1323	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1324
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1325	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1326	unsigned CRd = fieldFromInstruction(Insn, 12, 4);
				1327	unsigned coproc = fieldFromInstruction(Insn, 8, 4);
				1328	unsigned imm = fieldFromInstruction(Insn, 0, 8);
				1329	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1330	unsigned U = fieldFromInstruction(Insn, 23, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1331
				1332	switch (Inst.getOpcode()) {
				1333	case ARM::LDC_OFFSET:
				1334	case ARM::LDC_PRE:
				1335	case ARM::LDC_POST:
				1336	case ARM::LDC_OPTION:
				1337	case ARM::LDCL_OFFSET:
				1338	case ARM::LDCL_PRE:
				1339	case ARM::LDCL_POST:
				1340	case ARM::LDCL_OPTION:
				1341	case ARM::STC_OFFSET:
				1342	case ARM::STC_PRE:
				1343	case ARM::STC_POST:
				1344	case ARM::STC_OPTION:
				1345	case ARM::STCL_OFFSET:
				1346	case ARM::STCL_PRE:
				1347	case ARM::STCL_POST:
				1348	case ARM::STCL_OPTION:
Owen Anderson	18d17aa	2011-09-07 21:10:42 +0000	[diff] [blame]	1349	case ARM::t2LDC_OFFSET:
				1350	case ARM::t2LDC_PRE:
				1351	case ARM::t2LDC_POST:
				1352	case ARM::t2LDC_OPTION:
				1353	case ARM::t2LDCL_OFFSET:
				1354	case ARM::t2LDCL_PRE:
				1355	case ARM::t2LDCL_POST:
				1356	case ARM::t2LDCL_OPTION:
				1357	case ARM::t2STC_OFFSET:
				1358	case ARM::t2STC_PRE:
				1359	case ARM::t2STC_POST:
				1360	case ARM::t2STC_OPTION:
				1361	case ARM::t2STCL_OFFSET:
				1362	case ARM::t2STCL_PRE:
				1363	case ARM::t2STCL_POST:
				1364	case ARM::t2STCL_OPTION:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1365	if (coproc == 0xA \|\| coproc == 0xB)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1366	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1367	break;
				1368	default:
				1369	break;
				1370	}
				1371
Michael Kuperstein	db0712f	2015-05-26 10:47:10 +0000	[diff] [blame]	1372	const FeatureBitset &featureBits =
				1373	((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
				1374	if (featureBits[ARM::HasV8Ops] && (coproc != 14))
Artyom Skrobov	e686cec	2013-11-08 16:16:30 +0000	[diff] [blame]	1375	return MCDisassembler::Fail;
				1376
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1377	Inst.addOperand(MCOperand::createImm(coproc));
				1378	Inst.addOperand(MCOperand::createImm(CRd));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1379	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1380	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1381
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1382	switch (Inst.getOpcode()) {
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1383	case ARM::t2LDC2_OFFSET:
				1384	case ARM::t2LDC2L_OFFSET:
				1385	case ARM::t2LDC2_PRE:
				1386	case ARM::t2LDC2L_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1387	case ARM::t2STC2_OFFSET:
				1388	case ARM::t2STC2L_OFFSET:
				1389	case ARM::t2STC2_PRE:
				1390	case ARM::t2STC2L_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1391	case ARM::LDC2_OFFSET:
				1392	case ARM::LDC2L_OFFSET:
				1393	case ARM::LDC2_PRE:
				1394	case ARM::LDC2L_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1395	case ARM::STC2_OFFSET:
				1396	case ARM::STC2L_OFFSET:
				1397	case ARM::STC2_PRE:
				1398	case ARM::STC2L_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1399	case ARM::t2LDC_OFFSET:
				1400	case ARM::t2LDCL_OFFSET:
				1401	case ARM::t2LDC_PRE:
				1402	case ARM::t2LDCL_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1403	case ARM::t2STC_OFFSET:
				1404	case ARM::t2STCL_OFFSET:
				1405	case ARM::t2STC_PRE:
				1406	case ARM::t2STCL_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1407	case ARM::LDC_OFFSET:
				1408	case ARM::LDCL_OFFSET:
				1409	case ARM::LDC_PRE:
				1410	case ARM::LDCL_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1411	case ARM::STC_OFFSET:
				1412	case ARM::STCL_OFFSET:
				1413	case ARM::STC_PRE:
				1414	case ARM::STCL_PRE:
Jim Grosbach	a098a89	2011-10-12 21:59:02 +0000	[diff] [blame]	1415	imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1416	Inst.addOperand(MCOperand::createImm(imm));
Jim Grosbach	a098a89	2011-10-12 21:59:02 +0000	[diff] [blame]	1417	break;
				1418	case ARM::t2LDC2_POST:
				1419	case ARM::t2LDC2L_POST:
				1420	case ARM::t2STC2_POST:
				1421	case ARM::t2STC2L_POST:
				1422	case ARM::LDC2_POST:
				1423	case ARM::LDC2L_POST:
				1424	case ARM::STC2_POST:
				1425	case ARM::STC2L_POST:
				1426	case ARM::t2LDC_POST:
				1427	case ARM::t2LDCL_POST:
				1428	case ARM::t2STC_POST:
				1429	case ARM::t2STCL_POST:
				1430	case ARM::LDC_POST:
				1431	case ARM::LDCL_POST:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1432	case ARM::STC_POST:
				1433	case ARM::STCL_POST:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1434	imm \|= U << 8;
Justin Bogner	cd1d5aa	2016-08-17 20:30:52 +0000	[diff] [blame]	1435	LLVM_FALLTHROUGH;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1436	default:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1437	// The 'option' variant doesn't encode 'U' in the immediate since
				1438	// the immediate is unsigned [0,255].
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1439	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1440	break;
				1441	}
				1442
				1443	switch (Inst.getOpcode()) {
				1444	case ARM::LDC_OFFSET:
				1445	case ARM::LDC_PRE:
				1446	case ARM::LDC_POST:
				1447	case ARM::LDC_OPTION:
				1448	case ARM::LDCL_OFFSET:
				1449	case ARM::LDCL_PRE:
				1450	case ARM::LDCL_POST:
				1451	case ARM::LDCL_OPTION:
				1452	case ARM::STC_OFFSET:
				1453	case ARM::STC_PRE:
				1454	case ARM::STC_POST:
				1455	case ARM::STC_OPTION:
				1456	case ARM::STCL_OFFSET:
				1457	case ARM::STCL_PRE:
				1458	case ARM::STCL_POST:
				1459	case ARM::STCL_OPTION:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1460	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1461	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1462	break;
				1463	default:
				1464	break;
				1465	}
				1466
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1467	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1468	}
				1469
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1470	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1471	DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	1472	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1473	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1474
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1475	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1476	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				1477	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				1478	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				1479	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1480	unsigned reg = fieldFromInstruction(Insn, 25, 1);
				1481	unsigned P = fieldFromInstruction(Insn, 24, 1);
				1482	unsigned W = fieldFromInstruction(Insn, 21, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1483
				1484	// On stores, the writeback operand precedes Rt.
				1485	switch (Inst.getOpcode()) {
				1486	case ARM::STR_POST_IMM:
				1487	case ARM::STR_POST_REG:
Owen Anderson	3a850f2	2011-08-11 20:47:56 +0000	[diff] [blame]	1488	case ARM::STRB_POST_IMM:
				1489	case ARM::STRB_POST_REG:
Jim Grosbach	e259421	2011-08-11 22:18:00 +0000	[diff] [blame]	1490	case ARM::STRT_POST_REG:
				1491	case ARM::STRT_POST_IMM:
Jim Grosbach	2a50260	2011-08-11 20:04:56 +0000	[diff] [blame]	1492	case ARM::STRBT_POST_REG:
				1493	case ARM::STRBT_POST_IMM:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1494	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1495	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1496	break;
				1497	default:
				1498	break;
				1499	}
				1500
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1501	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				1502	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1503
				1504	// On loads, the writeback operand comes after Rt.
				1505	switch (Inst.getOpcode()) {
				1506	case ARM::LDR_POST_IMM:
				1507	case ARM::LDR_POST_REG:
Owen Anderson	3a850f2	2011-08-11 20:47:56 +0000	[diff] [blame]	1508	case ARM::LDRB_POST_IMM:
				1509	case ARM::LDRB_POST_REG:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1510	case ARM::LDRBT_POST_REG:
				1511	case ARM::LDRBT_POST_IMM:
Jim Grosbach	d5d6359	2011-08-10 23:43:54 +0000	[diff] [blame]	1512	case ARM::LDRT_POST_REG:
				1513	case ARM::LDRT_POST_IMM:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1514	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1515	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1516	break;
				1517	default:
				1518	break;
				1519	}
				1520
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1521	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1522	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1523
				1524	ARM_AM::AddrOpc Op = ARM_AM::add;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1525	if (!fieldFromInstruction(Insn, 23, 1))
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1526	Op = ARM_AM::sub;
				1527
				1528	bool writeback = (P == 0) \|\| (W == 1);
				1529	unsigned idx_mode = 0;
				1530	if (P && writeback)
				1531	idx_mode = ARMII::IndexModePre;
				1532	else if (!P && writeback)
				1533	idx_mode = ARMII::IndexModePost;
				1534
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1535	if (writeback && (Rn == 15 \|\| Rn == Rt))
				1536	S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson	3477f2c	2011-08-11 19:00:18 +0000	[diff] [blame]	1537
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1538	if (reg) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1539	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1540	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1541	ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1542	switch( fieldFromInstruction(Insn, 5, 2)) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1543	case 0:
				1544	Opc = ARM_AM::lsl;
				1545	break;
				1546	case 1:
				1547	Opc = ARM_AM::lsr;
				1548	break;
				1549	case 2:
				1550	Opc = ARM_AM::asr;
				1551	break;
				1552	case 3:
				1553	Opc = ARM_AM::ror;
				1554	break;
				1555	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1556	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1557	}
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1558	unsigned amt = fieldFromInstruction(Insn, 7, 5);
Tim Northover	0c97e76	2012-09-22 11:18:12 +0000	[diff] [blame]	1559	if (Opc == ARM_AM::ror && amt == 0)
				1560	Opc = ARM_AM::rrx;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1561	unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
				1562
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1563	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1564	} else {
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1565	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1566	unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1567	Inst.addOperand(MCOperand::createImm(tmp));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1568	}
				1569
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1570	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1571	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1572
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1573	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1574	}
				1575
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1576	static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1577	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1578	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1579
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1580	unsigned Rn = fieldFromInstruction(Val, 13, 4);
				1581	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				1582	unsigned type = fieldFromInstruction(Val, 5, 2);
				1583	unsigned imm = fieldFromInstruction(Val, 7, 5);
				1584	unsigned U = fieldFromInstruction(Val, 12, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1585
Owen Anderson	d151b09	2011-08-09 21:38:14 +0000	[diff] [blame]	1586	ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1587	switch (type) {
				1588	case 0:
				1589	ShOp = ARM_AM::lsl;
				1590	break;
				1591	case 1:
				1592	ShOp = ARM_AM::lsr;
				1593	break;
				1594	case 2:
				1595	ShOp = ARM_AM::asr;
				1596	break;
				1597	case 3:
				1598	ShOp = ARM_AM::ror;
				1599	break;
				1600	}
				1601
Tim Northover	0c97e76	2012-09-22 11:18:12 +0000	[diff] [blame]	1602	if (ShOp == ARM_AM::ror && imm == 0)
				1603	ShOp = ARM_AM::rrx;
				1604
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1605	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1606	return MCDisassembler::Fail;
				1607	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1608	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1609	unsigned shift;
				1610	if (U)
				1611	shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
				1612	else
				1613	shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1614	Inst.addOperand(MCOperand::createImm(shift));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1615
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1616	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1617	}
				1618
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1619	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1620	DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	1621	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1622	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1623
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1624	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				1625	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1626	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				1627	unsigned type = fieldFromInstruction(Insn, 22, 1);
				1628	unsigned imm = fieldFromInstruction(Insn, 8, 4);
				1629	unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
				1630	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1631	unsigned W = fieldFromInstruction(Insn, 21, 1);
				1632	unsigned P = fieldFromInstruction(Insn, 24, 1);
Silviu Baranga	4afd7d2	2012-03-22 14:14:49 +0000	[diff] [blame]	1633	unsigned Rt2 = Rt + 1;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1634
				1635	bool writeback = (W == 1) \| (P == 0);
Owen Anderson	1d5d2ca	2011-08-15 20:51:32 +0000	[diff] [blame]	1636
				1637	// For {LD,ST}RD, Rt must be even, else undefined.
				1638	switch (Inst.getOpcode()) {
				1639	case ARM::STRD:
				1640	case ARM::STRD_PRE:
				1641	case ARM::STRD_POST:
				1642	case ARM::LDRD:
				1643	case ARM::LDRD_PRE:
				1644	case ARM::LDRD_POST:
Silviu Baranga	4afd7d2	2012-03-22 14:14:49 +0000	[diff] [blame]	1645	if (Rt & 0x1) S = MCDisassembler::SoftFail;
				1646	break;
				1647	default:
				1648	break;
				1649	}
				1650	switch (Inst.getOpcode()) {
				1651	case ARM::STRD:
				1652	case ARM::STRD_PRE:
				1653	case ARM::STRD_POST:
				1654	if (P == 0 && W == 1)
				1655	S = MCDisassembler::SoftFail;
Vinicius Tinti	67cf33d	2015-11-20 23:20:12 +0000	[diff] [blame]	1656
Silviu Baranga	4afd7d2	2012-03-22 14:14:49 +0000	[diff] [blame]	1657	if (writeback && (Rn == 15 \|\| Rn == Rt \|\| Rn == Rt2))
				1658	S = MCDisassembler::SoftFail;
				1659	if (type && Rm == 15)
				1660	S = MCDisassembler::SoftFail;
				1661	if (Rt2 == 15)
				1662	S = MCDisassembler::SoftFail;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1663	if (!type && fieldFromInstruction(Insn, 8, 4))
Silviu Baranga	4afd7d2	2012-03-22 14:14:49 +0000	[diff] [blame]	1664	S = MCDisassembler::SoftFail;
				1665	break;
				1666	case ARM::STRH:
				1667	case ARM::STRH_PRE:
				1668	case ARM::STRH_POST:
				1669	if (Rt == 15)
				1670	S = MCDisassembler::SoftFail;
				1671	if (writeback && (Rn == 15 \|\| Rn == Rt))
				1672	S = MCDisassembler::SoftFail;
				1673	if (!type && Rm == 15)
				1674	S = MCDisassembler::SoftFail;
				1675	break;
				1676	case ARM::LDRD:
				1677	case ARM::LDRD_PRE:
				1678	case ARM::LDRD_POST:
				1679	if (type && Rn == 15){
				1680	if (Rt2 == 15)
				1681	S = MCDisassembler::SoftFail;
				1682	break;
				1683	}
				1684	if (P == 0 && W == 1)
				1685	S = MCDisassembler::SoftFail;
				1686	if (!type && (Rt2 == 15 \|\| Rm == 15 \|\| Rm == Rt \|\| Rm == Rt2))
				1687	S = MCDisassembler::SoftFail;
				1688	if (!type && writeback && Rn == 15)
				1689	S = MCDisassembler::SoftFail;
				1690	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				1691	S = MCDisassembler::SoftFail;
				1692	break;
				1693	case ARM::LDRH:
				1694	case ARM::LDRH_PRE:
				1695	case ARM::LDRH_POST:
				1696	if (type && Rn == 15){
				1697	if (Rt == 15)
				1698	S = MCDisassembler::SoftFail;
				1699	break;
				1700	}
				1701	if (Rt == 15)
				1702	S = MCDisassembler::SoftFail;
				1703	if (!type && Rm == 15)
				1704	S = MCDisassembler::SoftFail;
				1705	if (!type && writeback && (Rn == 15 \|\| Rn == Rt))
				1706	S = MCDisassembler::SoftFail;
				1707	break;
				1708	case ARM::LDRSH:
				1709	case ARM::LDRSH_PRE:
				1710	case ARM::LDRSH_POST:
				1711	case ARM::LDRSB:
				1712	case ARM::LDRSB_PRE:
				1713	case ARM::LDRSB_POST:
				1714	if (type && Rn == 15){
				1715	if (Rt == 15)
				1716	S = MCDisassembler::SoftFail;
				1717	break;
				1718	}
				1719	if (type && (Rt == 15 \|\| (writeback && Rn == Rt)))
				1720	S = MCDisassembler::SoftFail;
				1721	if (!type && (Rt == 15 \|\| Rm == 15))
				1722	S = MCDisassembler::SoftFail;
				1723	if (!type && writeback && (Rn == 15 \|\| Rn == Rt))
				1724	S = MCDisassembler::SoftFail;
Owen Anderson	1d5d2ca	2011-08-15 20:51:32 +0000	[diff] [blame]	1725	break;
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1726	default:
				1727	break;
Owen Anderson	1d5d2ca	2011-08-15 20:51:32 +0000	[diff] [blame]	1728	}
				1729
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1730	if (writeback) { // Writeback
				1731	if (P)
				1732	U \|= ARMII::IndexModePre << 9;
				1733	else
				1734	U \|= ARMII::IndexModePost << 9;
				1735
				1736	// On stores, the writeback operand precedes Rt.
				1737	switch (Inst.getOpcode()) {
				1738	case ARM::STRD:
				1739	case ARM::STRD_PRE:
				1740	case ARM::STRD_POST:
Owen Anderson	60138ea	2011-08-12 20:02:50 +0000	[diff] [blame]	1741	case ARM::STRH:
				1742	case ARM::STRH_PRE:
				1743	case ARM::STRH_POST:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1744	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1745	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1746	break;
				1747	default:
				1748	break;
				1749	}
				1750	}
				1751
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1752	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				1753	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1754	switch (Inst.getOpcode()) {
				1755	case ARM::STRD:
				1756	case ARM::STRD_PRE:
				1757	case ARM::STRD_POST:
				1758	case ARM::LDRD:
				1759	case ARM::LDRD_PRE:
				1760	case ARM::LDRD_POST:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1761	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
				1762	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1763	break;
				1764	default:
				1765	break;
				1766	}
				1767
				1768	if (writeback) {
				1769	// On loads, the writeback operand comes after Rt.
				1770	switch (Inst.getOpcode()) {
				1771	case ARM::LDRD:
				1772	case ARM::LDRD_PRE:
				1773	case ARM::LDRD_POST:
Owen Anderson	2d1d7a1	2011-08-12 20:36:11 +0000	[diff] [blame]	1774	case ARM::LDRH:
				1775	case ARM::LDRH_PRE:
				1776	case ARM::LDRH_POST:
				1777	case ARM::LDRSH:
				1778	case ARM::LDRSH_PRE:
				1779	case ARM::LDRSH_POST:
				1780	case ARM::LDRSB:
				1781	case ARM::LDRSB_PRE:
				1782	case ARM::LDRSB_POST:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1783	case ARM::LDRHTr:
				1784	case ARM::LDRSBTr:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1785	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1786	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1787	break;
				1788	default:
				1789	break;
				1790	}
				1791	}
				1792
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1793	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1794	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1795
				1796	if (type) {
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1797	Inst.addOperand(MCOperand::createReg(0));
				1798	Inst.addOperand(MCOperand::createImm(U \| (imm << 4) \| Rm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1799	} else {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1800	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1801	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1802	Inst.addOperand(MCOperand::createImm(U));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1803	}
				1804
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1805	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1806	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1807
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1808	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1809	}
				1810
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1811	static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1812	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1813	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1814
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1815	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1816	unsigned mode = fieldFromInstruction(Insn, 23, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1817
				1818	switch (mode) {
				1819	case 0:
				1820	mode = ARM_AM::da;
				1821	break;
				1822	case 1:
				1823	mode = ARM_AM::ia;
				1824	break;
				1825	case 2:
				1826	mode = ARM_AM::db;
				1827	break;
				1828	case 3:
				1829	mode = ARM_AM::ib;
				1830	break;
				1831	}
				1832
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1833	Inst.addOperand(MCOperand::createImm(mode));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1834	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1835	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1836
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1837	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1838	}
				1839
Amaury de la Vieuville	631df63	2013-06-08 13:38:52 +0000	[diff] [blame]	1840	static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
				1841	uint64_t Address, const void *Decoder) {
				1842	DecodeStatus S = MCDisassembler::Success;
				1843
				1844	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				1845	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				1846	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1847	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1848
				1849	if (pred == 0xF)
				1850	return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
				1851
				1852	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
				1853	return MCDisassembler::Fail;
				1854	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1855	return MCDisassembler::Fail;
				1856	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				1857	return MCDisassembler::Fail;
				1858	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1859	return MCDisassembler::Fail;
				1860	return S;
				1861	}
				1862
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1863	static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1864	unsigned Insn,
				1865	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1866	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1867
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1868	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1869	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1870	unsigned reglist = fieldFromInstruction(Insn, 0, 16);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1871
				1872	if (pred == 0xF) {
Amaury de la Vieuville	68bcd02	2013-06-08 13:43:59 +0000	[diff] [blame]	1873	// Ambiguous with RFE and SRS
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1874	switch (Inst.getOpcode()) {
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1875	case ARM::LDMDA:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1876	Inst.setOpcode(ARM::RFEDA);
				1877	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1878	case ARM::LDMDA_UPD:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1879	Inst.setOpcode(ARM::RFEDA_UPD);
				1880	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1881	case ARM::LDMDB:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1882	Inst.setOpcode(ARM::RFEDB);
				1883	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1884	case ARM::LDMDB_UPD:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1885	Inst.setOpcode(ARM::RFEDB_UPD);
				1886	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1887	case ARM::LDMIA:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1888	Inst.setOpcode(ARM::RFEIA);
				1889	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1890	case ARM::LDMIA_UPD:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1891	Inst.setOpcode(ARM::RFEIA_UPD);
				1892	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1893	case ARM::LDMIB:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1894	Inst.setOpcode(ARM::RFEIB);
				1895	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1896	case ARM::LDMIB_UPD:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1897	Inst.setOpcode(ARM::RFEIB_UPD);
				1898	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1899	case ARM::STMDA:
				1900	Inst.setOpcode(ARM::SRSDA);
				1901	break;
				1902	case ARM::STMDA_UPD:
				1903	Inst.setOpcode(ARM::SRSDA_UPD);
				1904	break;
				1905	case ARM::STMDB:
				1906	Inst.setOpcode(ARM::SRSDB);
				1907	break;
				1908	case ARM::STMDB_UPD:
				1909	Inst.setOpcode(ARM::SRSDB_UPD);
				1910	break;
				1911	case ARM::STMIA:
				1912	Inst.setOpcode(ARM::SRSIA);
				1913	break;
				1914	case ARM::STMIA_UPD:
				1915	Inst.setOpcode(ARM::SRSIA_UPD);
				1916	break;
				1917	case ARM::STMIB:
				1918	Inst.setOpcode(ARM::SRSIB);
				1919	break;
				1920	case ARM::STMIB_UPD:
				1921	Inst.setOpcode(ARM::SRSIB_UPD);
				1922	break;
				1923	default:
Amaury de la Vieuville	68bcd02	2013-06-08 13:43:59 +0000	[diff] [blame]	1924	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1925	}
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1926
				1927	// For stores (which become SRS's, the only operand is the mode.
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1928	if (fieldFromInstruction(Insn, 20, 1) == 0) {
Amaury de la Vieuville	68bcd02	2013-06-08 13:43:59 +0000	[diff] [blame]	1929	// Check SRS encoding constraints
				1930	if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
				1931	fieldFromInstruction(Insn, 20, 1) == 0))
				1932	return MCDisassembler::Fail;
				1933
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1934	Inst.addOperand(
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	1935	MCOperand::createImm(fieldFromInstruction(Insn, 0, 4)));
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1936	return S;
				1937	}
				1938
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1939	return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
				1940	}
				1941
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1942	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1943	return MCDisassembler::Fail;
				1944	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1945	return MCDisassembler::Fail; // Tied
				1946	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1947	return MCDisassembler::Fail;
				1948	if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
				1949	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1950
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1951	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1952	}
				1953
Sjoerd Meijer	d906bf1	2016-06-03 14:03:27 +0000	[diff] [blame]	1954	// Check for UNPREDICTABLE predicated ESB instruction
				1955	static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
				1956	uint64_t Address, const void *Decoder) {
				1957	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1958	unsigned imm8 = fieldFromInstruction(Insn, 0, 8);
				1959	const MCDisassembler Dis = static_cast<const MCDisassembler>(Decoder);
				1960	const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
				1961
				1962	DecodeStatus S = MCDisassembler::Success;
				1963
				1964	Inst.addOperand(MCOperand::createImm(imm8));
				1965
				1966	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1967	return MCDisassembler::Fail;
				1968
				1969	// ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP,
				1970	// so all predicates should be allowed.
				1971	if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0))
				1972	S = MCDisassembler::SoftFail;
				1973
				1974	return S;
				1975	}
				1976
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1977	static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1978	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1979	unsigned imod = fieldFromInstruction(Insn, 18, 2);
				1980	unsigned M = fieldFromInstruction(Insn, 17, 1);
				1981	unsigned iflags = fieldFromInstruction(Insn, 6, 3);
				1982	unsigned mode = fieldFromInstruction(Insn, 0, 5);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1983
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1984	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	3d2e0e9d	2011-08-09 23:05:39 +0000	[diff] [blame]	1985
Amaury de la Vieuville	631df63	2013-06-08 13:38:52 +0000	[diff] [blame]	1986	// This decoder is called from multiple location that do not check
				1987	// the full encoding is valid before they do.
				1988	if (fieldFromInstruction(Insn, 5, 1) != 0 \|\|
				1989	fieldFromInstruction(Insn, 16, 1) != 0 \|\|
				1990	fieldFromInstruction(Insn, 20, 8) != 0x10)
				1991	return MCDisassembler::Fail;
				1992
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1993	// imod == '01' --> UNPREDICTABLE
				1994	// NOTE: Even though this is technically UNPREDICTABLE, we choose to
				1995	// return failure here. The '01' imod value is unprintable, so there's
				1996	// nothing useful we could do even if we returned UNPREDICTABLE.
				1997
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1998	if (imod == 1) return MCDisassembler::Fail;
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1999
				2000	if (imod && M) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2001	Inst.setOpcode(ARM::CPS3p);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2002	Inst.addOperand(MCOperand::createImm(imod));
				2003	Inst.addOperand(MCOperand::createImm(iflags));
				2004	Inst.addOperand(MCOperand::createImm(mode));
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	2005	} else if (imod && !M) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2006	Inst.setOpcode(ARM::CPS2p);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2007	Inst.addOperand(MCOperand::createImm(imod));
				2008	Inst.addOperand(MCOperand::createImm(iflags));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	2009	if (mode) S = MCDisassembler::SoftFail;
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	2010	} else if (!imod && M) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2011	Inst.setOpcode(ARM::CPS1p);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2012	Inst.addOperand(MCOperand::createImm(mode));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	2013	if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson	5d2db89	2011-08-18 22:15:25 +0000	[diff] [blame]	2014	} else {
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	2015	// imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson	5d2db89	2011-08-18 22:15:25 +0000	[diff] [blame]	2016	Inst.setOpcode(ARM::CPS1p);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2017	Inst.addOperand(MCOperand::createImm(mode));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	2018	S = MCDisassembler::SoftFail;
Owen Anderson	5d2db89	2011-08-18 22:15:25 +0000	[diff] [blame]	2019	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2020
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	2021	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2022	}
				2023
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2024	static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2025	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2026	unsigned imod = fieldFromInstruction(Insn, 9, 2);
				2027	unsigned M = fieldFromInstruction(Insn, 8, 1);
				2028	unsigned iflags = fieldFromInstruction(Insn, 5, 3);
				2029	unsigned mode = fieldFromInstruction(Insn, 0, 5);
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2030
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2031	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2032
				2033	// imod == '01' --> UNPREDICTABLE
				2034	// NOTE: Even though this is technically UNPREDICTABLE, we choose to
				2035	// return failure here. The '01' imod value is unprintable, so there's
				2036	// nothing useful we could do even if we returned UNPREDICTABLE.
				2037
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	2038	if (imod == 1) return MCDisassembler::Fail;
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2039
				2040	if (imod && M) {
				2041	Inst.setOpcode(ARM::t2CPS3p);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2042	Inst.addOperand(MCOperand::createImm(imod));
				2043	Inst.addOperand(MCOperand::createImm(iflags));
				2044	Inst.addOperand(MCOperand::createImm(mode));
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2045	} else if (imod && !M) {
				2046	Inst.setOpcode(ARM::t2CPS2p);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2047	Inst.addOperand(MCOperand::createImm(imod));
				2048	Inst.addOperand(MCOperand::createImm(iflags));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	2049	if (mode) S = MCDisassembler::SoftFail;
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2050	} else if (!imod && M) {
				2051	Inst.setOpcode(ARM::t2CPS1p);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2052	Inst.addOperand(MCOperand::createImm(mode));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	2053	if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2054	} else {
Quentin Colombet	a83d5e9	2013-04-26 17:54:54 +0000	[diff] [blame]	2055	// imod == '00' && M == '0' --> this is a HINT instruction
				2056	int imm = fieldFromInstruction(Insn, 0, 8);
				2057	// HINT are defined only for immediate in [0..4]
				2058	if(imm > 4) return MCDisassembler::Fail;
				2059	Inst.setOpcode(ARM::t2HINT);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2060	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2061	}
				2062
				2063	return S;
				2064	}
				2065
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2066	static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2067	uint64_t Address, const void *Decoder) {
				2068	DecodeStatus S = MCDisassembler::Success;
				2069
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2070	unsigned Rd = fieldFromInstruction(Insn, 8, 4);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2071	unsigned imm = 0;
				2072
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2073	imm \|= (fieldFromInstruction(Insn, 0, 8) << 0);
				2074	imm \|= (fieldFromInstruction(Insn, 12, 3) << 8);
				2075	imm \|= (fieldFromInstruction(Insn, 16, 4) << 12);
				2076	imm \|= (fieldFromInstruction(Insn, 26, 1) << 11);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2077
				2078	if (Inst.getOpcode() == ARM::t2MOVTi16)
				2079	if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
				2080	return MCDisassembler::Fail;
				2081	if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
				2082	return MCDisassembler::Fail;
				2083
				2084	if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2085	Inst.addOperand(MCOperand::createImm(imm));
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2086
				2087	return S;
				2088	}
				2089
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2090	static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2091	uint64_t Address, const void *Decoder) {
				2092	DecodeStatus S = MCDisassembler::Success;
				2093
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2094	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2095	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2096	unsigned imm = 0;
				2097
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2098	imm \|= (fieldFromInstruction(Insn, 0, 12) << 0);
				2099	imm \|= (fieldFromInstruction(Insn, 16, 4) << 12);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2100
				2101	if (Inst.getOpcode() == ARM::MOVTi16)
Tim Northover	a155ab2	2013-04-19 09:58:09 +0000	[diff] [blame]	2102	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2103	return MCDisassembler::Fail;
Tim Northover	a155ab2	2013-04-19 09:58:09 +0000	[diff] [blame]	2104
				2105	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2106	return MCDisassembler::Fail;
				2107
				2108	if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2109	Inst.addOperand(MCOperand::createImm(imm));
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2110
				2111	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2112	return MCDisassembler::Fail;
				2113
				2114	return S;
				2115	}
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2116
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2117	static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2118	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2119	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2120
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2121	unsigned Rd = fieldFromInstruction(Insn, 16, 4);
				2122	unsigned Rn = fieldFromInstruction(Insn, 0, 4);
				2123	unsigned Rm = fieldFromInstruction(Insn, 8, 4);
				2124	unsigned Ra = fieldFromInstruction(Insn, 12, 4);
				2125	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2126
				2127	if (pred == 0xF)
				2128	return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
				2129
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2130	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
				2131	return MCDisassembler::Fail;
				2132	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				2133	return MCDisassembler::Fail;
				2134	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				2135	return MCDisassembler::Fail;
				2136	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
				2137	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2138
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2139	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2140	return MCDisassembler::Fail;
Owen Anderson	2f7aa73	2011-08-11 22:05:38 +0000	[diff] [blame]	2141
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2142	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2143	}
				2144
Vladimir Sukharev	0e0f8d2	2015-04-16 11:34:25 +0000	[diff] [blame]	2145	static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
				2146	uint64_t Address, const void *Decoder) {
				2147	DecodeStatus S = MCDisassembler::Success;
				2148
				2149	unsigned Pred = fieldFromInstruction(Insn, 28, 4);
				2150	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2151	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2152
				2153	if (Pred == 0xF)
				2154	return DecodeSETPANInstruction(Inst, Insn, Address, Decoder);
				2155
				2156	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2157	return MCDisassembler::Fail;
				2158	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2159	return MCDisassembler::Fail;
				2160	if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder)))
				2161	return MCDisassembler::Fail;
				2162
				2163	return S;
				2164	}
				2165
				2166	static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
				2167	uint64_t Address, const void *Decoder) {
				2168	DecodeStatus S = MCDisassembler::Success;
				2169
				2170	unsigned Imm = fieldFromInstruction(Insn, 9, 1);
				2171
				2172	const MCDisassembler Dis = static_cast<const MCDisassembler>(Decoder);
Michael Kuperstein	db0712f	2015-05-26 10:47:10 +0000	[diff] [blame]	2173	const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
				2174
				2175	if (!FeatureBits[ARM::HasV8_1aOps] \|\|
				2176	!FeatureBits[ARM::HasV8Ops])
Vladimir Sukharev	0e0f8d2	2015-04-16 11:34:25 +0000	[diff] [blame]	2177	return MCDisassembler::Fail;
				2178
				2179	// Decoder can be called from DecodeTST, which does not check the full
				2180	// encoding is valid.
				2181	if (fieldFromInstruction(Insn, 20,12) != 0xf11 \|\|
				2182	fieldFromInstruction(Insn, 4,4) != 0)
				2183	return MCDisassembler::Fail;
				2184	if (fieldFromInstruction(Insn, 10,10) != 0 \|\|
				2185	fieldFromInstruction(Insn, 0,4) != 0)
				2186	S = MCDisassembler::SoftFail;
				2187
				2188	Inst.setOpcode(ARM::SETPAN);
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2189	Inst.addOperand(MCOperand::createImm(Imm));
Vladimir Sukharev	0e0f8d2	2015-04-16 11:34:25 +0000	[diff] [blame]	2190
				2191	return S;
				2192	}
				2193
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2194	static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2195	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2196	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2197
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2198	unsigned add = fieldFromInstruction(Val, 12, 1);
				2199	unsigned imm = fieldFromInstruction(Val, 0, 12);
				2200	unsigned Rn = fieldFromInstruction(Val, 13, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2201
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2202	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2203	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2204
				2205	if (!add) imm *= -1;
				2206	if (imm == 0 && !add) imm = INT32_MIN;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2207	Inst.addOperand(MCOperand::createImm(imm));
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2208	if (Rn == 15)
				2209	tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2210
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2211	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2212	}
				2213
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2214	static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2215	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2216	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2217
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2218	unsigned Rn = fieldFromInstruction(Val, 9, 4);
Oliver Stannard	65b8538	2016-01-25 10:26:26 +0000	[diff] [blame]	2219	// U == 1 to add imm, 0 to subtract it.
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2220	unsigned U = fieldFromInstruction(Val, 8, 1);
				2221	unsigned imm = fieldFromInstruction(Val, 0, 8);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2222
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2223	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2224	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2225
				2226	if (U)
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2227	Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2228	else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2229	Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2230
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2231	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2232	}
				2233
Oliver Stannard	65b8538	2016-01-25 10:26:26 +0000	[diff] [blame]	2234	static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
				2235	uint64_t Address, const void *Decoder) {
				2236	DecodeStatus S = MCDisassembler::Success;
				2237
				2238	unsigned Rn = fieldFromInstruction(Val, 9, 4);
				2239	// U == 1 to add imm, 0 to subtract it.
				2240	unsigned U = fieldFromInstruction(Val, 8, 1);
				2241	unsigned imm = fieldFromInstruction(Val, 0, 8);
				2242
				2243	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2244	return MCDisassembler::Fail;
				2245
				2246	if (U)
				2247	Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm)));
				2248	else
				2249	Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm)));
				2250
				2251	return S;
				2252	}
				2253
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2254	static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2255	uint64_t Address, const void *Decoder) {
				2256	return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
				2257	}
				2258
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2259	static DecodeStatus
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	2260	DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
				2261	uint64_t Address, const void *Decoder) {
Kevin Enderby	6fd9624	2012-10-29 23:27:20 +0000	[diff] [blame]	2262	DecodeStatus Status = MCDisassembler::Success;
				2263
				2264	// Note the J1 and J2 values are from the encoded instruction. So here
				2265	// change them to I1 and I2 values via as documented:
				2266	// I1 = NOT(J1 EOR S);
				2267	// I2 = NOT(J2 EOR S);
				2268	// and build the imm32 with one trailing zero as documented:
				2269	// imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
				2270	unsigned S = fieldFromInstruction(Insn, 26, 1);
				2271	unsigned J1 = fieldFromInstruction(Insn, 13, 1);
				2272	unsigned J2 = fieldFromInstruction(Insn, 11, 1);
				2273	unsigned I1 = !(J1 ^ S);
				2274	unsigned I2 = !(J2 ^ S);
				2275	unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
				2276	unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
				2277	unsigned tmp = (S << 23) \| (I1 << 22) \| (I2 << 21) \| (imm10 << 11) \| imm11;
Amaury de la Vieuville	bd2b610	2013-06-13 16:41:55 +0000	[diff] [blame]	2278	int imm32 = SignExtend32<25>(tmp << 1);
Kevin Enderby	6fd9624	2012-10-29 23:27:20 +0000	[diff] [blame]	2279	if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	2280	true, 4, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2281	Inst.addOperand(MCOperand::createImm(imm32));
Kevin Enderby	6fd9624	2012-10-29 23:27:20 +0000	[diff] [blame]	2282
				2283	return Status;
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	2284	}
				2285
				2286	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2287	DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	2288	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2289	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2290
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2291	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				2292	unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2293
				2294	if (pred == 0xF) {
				2295	Inst.setOpcode(ARM::BLXi);
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2296	imm \|= fieldFromInstruction(Insn, 24, 1) << 1;
Kevin Enderby	6fbcd8d	2012-02-23 18:18:17 +0000	[diff] [blame]	2297	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
				2298	true, 4, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2299	Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2300	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2301	}
				2302
Kevin Enderby	6fbcd8d	2012-02-23 18:18:17 +0000	[diff] [blame]	2303	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
				2304	true, 4, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2305	Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2306	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2307	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2308
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2309	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2310	}
				2311
				2312
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2313	static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2314	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2315	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2316
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2317	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				2318	unsigned align = fieldFromInstruction(Val, 4, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2319
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2320	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2321	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2322	if (!align)
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2323	Inst.addOperand(MCOperand::createImm(0));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2324	else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2325	Inst.addOperand(MCOperand::createImm(4 << align));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2326
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2327	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2328	}
				2329
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2330	static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2331	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2332	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2333
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2334	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2335	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2336	unsigned wb = fieldFromInstruction(Insn, 16, 4);
				2337	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2338	Rn \|= fieldFromInstruction(Insn, 4, 2) << 4;
				2339	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2340
				2341	// First output register
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2342	switch (Inst.getOpcode()) {
Jim Grosbach	13a292c	2012-03-06 22:01:44 +0000	[diff] [blame]	2343	case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
				2344	case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
				2345	case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
				2346	case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
				2347	case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
				2348	case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
				2349	case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
				2350	case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
				2351	case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2352	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2353	return MCDisassembler::Fail;
				2354	break;
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	2355	case ARM::VLD2b16:
				2356	case ARM::VLD2b32:
				2357	case ARM::VLD2b8:
				2358	case ARM::VLD2b16wb_fixed:
				2359	case ARM::VLD2b16wb_register:
				2360	case ARM::VLD2b32wb_fixed:
				2361	case ARM::VLD2b32wb_register:
				2362	case ARM::VLD2b8wb_fixed:
				2363	case ARM::VLD2b8wb_register:
				2364	if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
				2365	return MCDisassembler::Fail;
				2366	break;
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2367	default:
				2368	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2369	return MCDisassembler::Fail;
				2370	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2371
				2372	// Second output register
				2373	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2374	case ARM::VLD3d8:
				2375	case ARM::VLD3d16:
				2376	case ARM::VLD3d32:
				2377	case ARM::VLD3d8_UPD:
				2378	case ARM::VLD3d16_UPD:
				2379	case ARM::VLD3d32_UPD:
				2380	case ARM::VLD4d8:
				2381	case ARM::VLD4d16:
				2382	case ARM::VLD4d32:
				2383	case ARM::VLD4d8_UPD:
				2384	case ARM::VLD4d16_UPD:
				2385	case ARM::VLD4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2386	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
				2387	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2388	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2389	case ARM::VLD3q8:
				2390	case ARM::VLD3q16:
				2391	case ARM::VLD3q32:
				2392	case ARM::VLD3q8_UPD:
				2393	case ARM::VLD3q16_UPD:
				2394	case ARM::VLD3q32_UPD:
				2395	case ARM::VLD4q8:
				2396	case ARM::VLD4q16:
				2397	case ARM::VLD4q32:
				2398	case ARM::VLD4q8_UPD:
				2399	case ARM::VLD4q16_UPD:
				2400	case ARM::VLD4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2401	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2402	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2403	default:
				2404	break;
				2405	}
				2406
				2407	// Third output register
				2408	switch(Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2409	case ARM::VLD3d8:
				2410	case ARM::VLD3d16:
				2411	case ARM::VLD3d32:
				2412	case ARM::VLD3d8_UPD:
				2413	case ARM::VLD3d16_UPD:
				2414	case ARM::VLD3d32_UPD:
				2415	case ARM::VLD4d8:
				2416	case ARM::VLD4d16:
				2417	case ARM::VLD4d32:
				2418	case ARM::VLD4d8_UPD:
				2419	case ARM::VLD4d16_UPD:
				2420	case ARM::VLD4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2421	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2422	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2423	break;
				2424	case ARM::VLD3q8:
				2425	case ARM::VLD3q16:
				2426	case ARM::VLD3q32:
				2427	case ARM::VLD3q8_UPD:
				2428	case ARM::VLD3q16_UPD:
				2429	case ARM::VLD3q32_UPD:
				2430	case ARM::VLD4q8:
				2431	case ARM::VLD4q16:
				2432	case ARM::VLD4q32:
				2433	case ARM::VLD4q8_UPD:
				2434	case ARM::VLD4q16_UPD:
				2435	case ARM::VLD4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2436	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
				2437	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2438	break;
				2439	default:
				2440	break;
				2441	}
				2442
				2443	// Fourth output register
				2444	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2445	case ARM::VLD4d8:
				2446	case ARM::VLD4d16:
				2447	case ARM::VLD4d32:
				2448	case ARM::VLD4d8_UPD:
				2449	case ARM::VLD4d16_UPD:
				2450	case ARM::VLD4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2451	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
				2452	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2453	break;
				2454	case ARM::VLD4q8:
				2455	case ARM::VLD4q16:
				2456	case ARM::VLD4q32:
				2457	case ARM::VLD4q8_UPD:
				2458	case ARM::VLD4q16_UPD:
				2459	case ARM::VLD4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2460	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
				2461	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2462	break;
				2463	default:
				2464	break;
				2465	}
				2466
				2467	// Writeback operand
				2468	switch (Inst.getOpcode()) {
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2469	case ARM::VLD1d8wb_fixed:
				2470	case ARM::VLD1d16wb_fixed:
				2471	case ARM::VLD1d32wb_fixed:
				2472	case ARM::VLD1d64wb_fixed:
				2473	case ARM::VLD1d8wb_register:
				2474	case ARM::VLD1d16wb_register:
				2475	case ARM::VLD1d32wb_register:
				2476	case ARM::VLD1d64wb_register:
				2477	case ARM::VLD1q8wb_fixed:
				2478	case ARM::VLD1q16wb_fixed:
				2479	case ARM::VLD1q32wb_fixed:
				2480	case ARM::VLD1q64wb_fixed:
				2481	case ARM::VLD1q8wb_register:
				2482	case ARM::VLD1q16wb_register:
				2483	case ARM::VLD1q32wb_register:
				2484	case ARM::VLD1q64wb_register:
Jim Grosbach	92fd05e	2011-10-24 23:26:05 +0000	[diff] [blame]	2485	case ARM::VLD1d8Twb_fixed:
				2486	case ARM::VLD1d8Twb_register:
				2487	case ARM::VLD1d16Twb_fixed:
				2488	case ARM::VLD1d16Twb_register:
				2489	case ARM::VLD1d32Twb_fixed:
				2490	case ARM::VLD1d32Twb_register:
				2491	case ARM::VLD1d64Twb_fixed:
				2492	case ARM::VLD1d64Twb_register:
Jim Grosbach	17ec1a1	2011-10-25 00:14:01 +0000	[diff] [blame]	2493	case ARM::VLD1d8Qwb_fixed:
				2494	case ARM::VLD1d8Qwb_register:
				2495	case ARM::VLD1d16Qwb_fixed:
				2496	case ARM::VLD1d16Qwb_register:
				2497	case ARM::VLD1d32Qwb_fixed:
				2498	case ARM::VLD1d32Qwb_register:
				2499	case ARM::VLD1d64Qwb_fixed:
				2500	case ARM::VLD1d64Qwb_register:
Jim Grosbach	d146a02	2011-12-09 21:28:25 +0000	[diff] [blame]	2501	case ARM::VLD2d8wb_fixed:
				2502	case ARM::VLD2d16wb_fixed:
				2503	case ARM::VLD2d32wb_fixed:
				2504	case ARM::VLD2q8wb_fixed:
				2505	case ARM::VLD2q16wb_fixed:
				2506	case ARM::VLD2q32wb_fixed:
				2507	case ARM::VLD2d8wb_register:
				2508	case ARM::VLD2d16wb_register:
				2509	case ARM::VLD2d32wb_register:
				2510	case ARM::VLD2q8wb_register:
				2511	case ARM::VLD2q16wb_register:
				2512	case ARM::VLD2q32wb_register:
				2513	case ARM::VLD2b8wb_fixed:
				2514	case ARM::VLD2b16wb_fixed:
				2515	case ARM::VLD2b32wb_fixed:
				2516	case ARM::VLD2b8wb_register:
				2517	case ARM::VLD2b16wb_register:
				2518	case ARM::VLD2b32wb_register:
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2519	Inst.addOperand(MCOperand::createImm(0));
Kevin Enderby	d2980cd	2012-04-11 00:25:40 +0000	[diff] [blame]	2520	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2521	case ARM::VLD3d8_UPD:
				2522	case ARM::VLD3d16_UPD:
				2523	case ARM::VLD3d32_UPD:
				2524	case ARM::VLD3q8_UPD:
				2525	case ARM::VLD3q16_UPD:
				2526	case ARM::VLD3q32_UPD:
				2527	case ARM::VLD4d8_UPD:
				2528	case ARM::VLD4d16_UPD:
				2529	case ARM::VLD4d32_UPD:
				2530	case ARM::VLD4q8_UPD:
				2531	case ARM::VLD4q16_UPD:
				2532	case ARM::VLD4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2533	if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
				2534	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2535	break;
				2536	default:
				2537	break;
				2538	}
				2539
				2540	// AddrMode6 Base (register+alignment)
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2541	if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
				2542	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2543
				2544	// AddrMode6 Offset (register)
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2545	switch (Inst.getOpcode()) {
				2546	default:
				2547	// The below have been updated to have explicit am6offset split
				2548	// between fixed and register offset. For those instructions not
				2549	// yet updated, we need to add an additional reg0 operand for the
				2550	// fixed variant.
				2551	//
				2552	// The fixed offset encodes as Rm == 0xd, so we check for that.
				2553	if (Rm == 0xd) {
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2554	Inst.addOperand(MCOperand::createReg(0));
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2555	break;
				2556	}
				2557	// Fall through to handle the register offset variant.
Justin Bogner	cd1d5aa	2016-08-17 20:30:52 +0000	[diff] [blame]	2558	LLVM_FALLTHROUGH;
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2559	case ARM::VLD1d8wb_fixed:
				2560	case ARM::VLD1d16wb_fixed:
				2561	case ARM::VLD1d32wb_fixed:
				2562	case ARM::VLD1d64wb_fixed:
Owen Anderson	8a6ebd0	2011-10-27 22:53:10 +0000	[diff] [blame]	2563	case ARM::VLD1d8Twb_fixed:
				2564	case ARM::VLD1d16Twb_fixed:
				2565	case ARM::VLD1d32Twb_fixed:
				2566	case ARM::VLD1d64Twb_fixed:
Owen Anderson	40703f4	2011-10-31 17:17:32 +0000	[diff] [blame]	2567	case ARM::VLD1d8Qwb_fixed:
				2568	case ARM::VLD1d16Qwb_fixed:
				2569	case ARM::VLD1d32Qwb_fixed:
				2570	case ARM::VLD1d64Qwb_fixed:
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2571	case ARM::VLD1d8wb_register:
				2572	case ARM::VLD1d16wb_register:
				2573	case ARM::VLD1d32wb_register:
				2574	case ARM::VLD1d64wb_register:
				2575	case ARM::VLD1q8wb_fixed:
				2576	case ARM::VLD1q16wb_fixed:
				2577	case ARM::VLD1q32wb_fixed:
				2578	case ARM::VLD1q64wb_fixed:
				2579	case ARM::VLD1q8wb_register:
				2580	case ARM::VLD1q16wb_register:
				2581	case ARM::VLD1q32wb_register:
				2582	case ARM::VLD1q64wb_register:
				2583	// The fixed offset post-increment encodes Rm == 0xd. The no-writeback
				2584	// variant encodes Rm == 0xf. Anything else is a register offset post-
				2585	// increment and we need to add the register operand to the instruction.
				2586	if (Rm != 0xD && Rm != 0xF &&
				2587	!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2588	return MCDisassembler::Fail;
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2589	break;
Kevin Enderby	d2980cd	2012-04-11 00:25:40 +0000	[diff] [blame]	2590	case ARM::VLD2d8wb_fixed:
				2591	case ARM::VLD2d16wb_fixed:
				2592	case ARM::VLD2d32wb_fixed:
				2593	case ARM::VLD2b8wb_fixed:
				2594	case ARM::VLD2b16wb_fixed:
				2595	case ARM::VLD2b32wb_fixed:
				2596	case ARM::VLD2q8wb_fixed:
				2597	case ARM::VLD2q16wb_fixed:
				2598	case ARM::VLD2q32wb_fixed:
				2599	break;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2600	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2601
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2602	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2603	}
				2604
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2605	static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
				2606	uint64_t Address, const void *Decoder) {
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2607	unsigned type = fieldFromInstruction(Insn, 8, 4);
				2608	unsigned align = fieldFromInstruction(Insn, 4, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2609	if (type == 6 && (align & 2)) return MCDisassembler::Fail;
				2610	if (type == 7 && (align & 2)) return MCDisassembler::Fail;
				2611	if (type == 10 && align == 3) return MCDisassembler::Fail;
				2612
				2613	unsigned load = fieldFromInstruction(Insn, 21, 1);
				2614	return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
				2615	: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2616	}
				2617
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2618	static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
				2619	uint64_t Address, const void *Decoder) {
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2620	unsigned size = fieldFromInstruction(Insn, 6, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2621	if (size == 3) return MCDisassembler::Fail;
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2622
				2623	unsigned type = fieldFromInstruction(Insn, 8, 4);
				2624	unsigned align = fieldFromInstruction(Insn, 4, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2625	if (type == 8 && align == 3) return MCDisassembler::Fail;
				2626	if (type == 9 && align == 3) return MCDisassembler::Fail;
				2627
				2628	unsigned load = fieldFromInstruction(Insn, 21, 1);
				2629	return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
				2630	: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2631	}
				2632
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2633	static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
				2634	uint64_t Address, const void *Decoder) {
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2635	unsigned size = fieldFromInstruction(Insn, 6, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2636	if (size == 3) return MCDisassembler::Fail;
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2637
				2638	unsigned align = fieldFromInstruction(Insn, 4, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2639	if (align & 2) return MCDisassembler::Fail;
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2640
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2641	unsigned load = fieldFromInstruction(Insn, 21, 1);
				2642	return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
				2643	: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2644	}
				2645
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2646	static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
				2647	uint64_t Address, const void *Decoder) {
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2648	unsigned size = fieldFromInstruction(Insn, 6, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2649	if (size == 3) return MCDisassembler::Fail;
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2650
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2651	unsigned load = fieldFromInstruction(Insn, 21, 1);
				2652	return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
				2653	: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2654	}
				2655
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2656	static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2657	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2658	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2659
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2660	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2661	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2662	unsigned wb = fieldFromInstruction(Insn, 16, 4);
				2663	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2664	Rn \|= fieldFromInstruction(Insn, 4, 2) << 4;
				2665	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2666
				2667	// Writeback Operand
				2668	switch (Inst.getOpcode()) {
Jim Grosbach	05df460	2011-10-31 21:50:31 +0000	[diff] [blame]	2669	case ARM::VST1d8wb_fixed:
				2670	case ARM::VST1d16wb_fixed:
				2671	case ARM::VST1d32wb_fixed:
				2672	case ARM::VST1d64wb_fixed:
				2673	case ARM::VST1d8wb_register:
				2674	case ARM::VST1d16wb_register:
				2675	case ARM::VST1d32wb_register:
				2676	case ARM::VST1d64wb_register:
				2677	case ARM::VST1q8wb_fixed:
				2678	case ARM::VST1q16wb_fixed:
				2679	case ARM::VST1q32wb_fixed:
				2680	case ARM::VST1q64wb_fixed:
				2681	case ARM::VST1q8wb_register:
				2682	case ARM::VST1q16wb_register:
				2683	case ARM::VST1q32wb_register:
				2684	case ARM::VST1q64wb_register:
Jim Grosbach	98d032f	2011-11-29 22:38:04 +0000	[diff] [blame]	2685	case ARM::VST1d8Twb_fixed:
				2686	case ARM::VST1d16Twb_fixed:
				2687	case ARM::VST1d32Twb_fixed:
				2688	case ARM::VST1d64Twb_fixed:
				2689	case ARM::VST1d8Twb_register:
				2690	case ARM::VST1d16Twb_register:
				2691	case ARM::VST1d32Twb_register:
				2692	case ARM::VST1d64Twb_register:
Jim Grosbach	5ee209c	2011-11-29 22:58:48 +0000	[diff] [blame]	2693	case ARM::VST1d8Qwb_fixed:
				2694	case ARM::VST1d16Qwb_fixed:
				2695	case ARM::VST1d32Qwb_fixed:
				2696	case ARM::VST1d64Qwb_fixed:
				2697	case ARM::VST1d8Qwb_register:
				2698	case ARM::VST1d16Qwb_register:
				2699	case ARM::VST1d32Qwb_register:
				2700	case ARM::VST1d64Qwb_register:
Jim Grosbach	88ac761	2011-12-14 21:32:11 +0000	[diff] [blame]	2701	case ARM::VST2d8wb_fixed:
				2702	case ARM::VST2d16wb_fixed:
				2703	case ARM::VST2d32wb_fixed:
				2704	case ARM::VST2d8wb_register:
				2705	case ARM::VST2d16wb_register:
				2706	case ARM::VST2d32wb_register:
				2707	case ARM::VST2q8wb_fixed:
				2708	case ARM::VST2q16wb_fixed:
				2709	case ARM::VST2q32wb_fixed:
				2710	case ARM::VST2q8wb_register:
				2711	case ARM::VST2q16wb_register:
				2712	case ARM::VST2q32wb_register:
				2713	case ARM::VST2b8wb_fixed:
				2714	case ARM::VST2b16wb_fixed:
				2715	case ARM::VST2b32wb_fixed:
				2716	case ARM::VST2b8wb_register:
				2717	case ARM::VST2b16wb_register:
				2718	case ARM::VST2b32wb_register:
Kevin Enderby	72f18bb	2012-04-11 22:40:17 +0000	[diff] [blame]	2719	if (Rm == 0xF)
				2720	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2721	Inst.addOperand(MCOperand::createImm(0));
Kevin Enderby	7e7d5ee	2012-03-21 20:54:32 +0000	[diff] [blame]	2722	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2723	case ARM::VST3d8_UPD:
				2724	case ARM::VST3d16_UPD:
				2725	case ARM::VST3d32_UPD:
				2726	case ARM::VST3q8_UPD:
				2727	case ARM::VST3q16_UPD:
				2728	case ARM::VST3q32_UPD:
				2729	case ARM::VST4d8_UPD:
				2730	case ARM::VST4d16_UPD:
				2731	case ARM::VST4d32_UPD:
				2732	case ARM::VST4q8_UPD:
				2733	case ARM::VST4q16_UPD:
				2734	case ARM::VST4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2735	if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
				2736	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2737	break;
				2738	default:
				2739	break;
				2740	}
				2741
				2742	// AddrMode6 Base (register+alignment)
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2743	if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
				2744	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2745
				2746	// AddrMode6 Offset (register)
Owen Anderson	69e54a7	2011-11-01 22:18:13 +0000	[diff] [blame]	2747	switch (Inst.getOpcode()) {
				2748	default:
				2749	if (Rm == 0xD)
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2750	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	69e54a7	2011-11-01 22:18:13 +0000	[diff] [blame]	2751	else if (Rm != 0xF) {
				2752	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2753	return MCDisassembler::Fail;
				2754	}
				2755	break;
				2756	case ARM::VST1d8wb_fixed:
				2757	case ARM::VST1d16wb_fixed:
				2758	case ARM::VST1d32wb_fixed:
				2759	case ARM::VST1d64wb_fixed:
				2760	case ARM::VST1q8wb_fixed:
				2761	case ARM::VST1q16wb_fixed:
				2762	case ARM::VST1q32wb_fixed:
				2763	case ARM::VST1q64wb_fixed:
Kevin Enderby	7e7d5ee	2012-03-21 20:54:32 +0000	[diff] [blame]	2764	case ARM::VST1d8Twb_fixed:
				2765	case ARM::VST1d16Twb_fixed:
				2766	case ARM::VST1d32Twb_fixed:
				2767	case ARM::VST1d64Twb_fixed:
				2768	case ARM::VST1d8Qwb_fixed:
				2769	case ARM::VST1d16Qwb_fixed:
				2770	case ARM::VST1d32Qwb_fixed:
				2771	case ARM::VST1d64Qwb_fixed:
				2772	case ARM::VST2d8wb_fixed:
				2773	case ARM::VST2d16wb_fixed:
				2774	case ARM::VST2d32wb_fixed:
				2775	case ARM::VST2q8wb_fixed:
				2776	case ARM::VST2q16wb_fixed:
				2777	case ARM::VST2q32wb_fixed:
				2778	case ARM::VST2b8wb_fixed:
				2779	case ARM::VST2b16wb_fixed:
				2780	case ARM::VST2b32wb_fixed:
Owen Anderson	69e54a7	2011-11-01 22:18:13 +0000	[diff] [blame]	2781	break;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2782	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2783
Owen Anderson	69e54a7	2011-11-01 22:18:13 +0000	[diff] [blame]	2784
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2785	// First input register
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2786	switch (Inst.getOpcode()) {
				2787	case ARM::VST1q16:
				2788	case ARM::VST1q32:
				2789	case ARM::VST1q64:
				2790	case ARM::VST1q8:
				2791	case ARM::VST1q16wb_fixed:
				2792	case ARM::VST1q16wb_register:
				2793	case ARM::VST1q32wb_fixed:
				2794	case ARM::VST1q32wb_register:
				2795	case ARM::VST1q64wb_fixed:
				2796	case ARM::VST1q64wb_register:
				2797	case ARM::VST1q8wb_fixed:
				2798	case ARM::VST1q8wb_register:
				2799	case ARM::VST2d16:
				2800	case ARM::VST2d32:
				2801	case ARM::VST2d8:
				2802	case ARM::VST2d16wb_fixed:
				2803	case ARM::VST2d16wb_register:
				2804	case ARM::VST2d32wb_fixed:
				2805	case ARM::VST2d32wb_register:
				2806	case ARM::VST2d8wb_fixed:
				2807	case ARM::VST2d8wb_register:
				2808	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2809	return MCDisassembler::Fail;
				2810	break;
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	2811	case ARM::VST2b16:
				2812	case ARM::VST2b32:
				2813	case ARM::VST2b8:
				2814	case ARM::VST2b16wb_fixed:
				2815	case ARM::VST2b16wb_register:
				2816	case ARM::VST2b32wb_fixed:
				2817	case ARM::VST2b32wb_register:
				2818	case ARM::VST2b8wb_fixed:
				2819	case ARM::VST2b8wb_register:
				2820	if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
				2821	return MCDisassembler::Fail;
				2822	break;
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2823	default:
				2824	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2825	return MCDisassembler::Fail;
				2826	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2827
				2828	// Second input register
				2829	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2830	case ARM::VST3d8:
				2831	case ARM::VST3d16:
				2832	case ARM::VST3d32:
				2833	case ARM::VST3d8_UPD:
				2834	case ARM::VST3d16_UPD:
				2835	case ARM::VST3d32_UPD:
				2836	case ARM::VST4d8:
				2837	case ARM::VST4d16:
				2838	case ARM::VST4d32:
				2839	case ARM::VST4d8_UPD:
				2840	case ARM::VST4d16_UPD:
				2841	case ARM::VST4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2842	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
				2843	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2844	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2845	case ARM::VST3q8:
				2846	case ARM::VST3q16:
				2847	case ARM::VST3q32:
				2848	case ARM::VST3q8_UPD:
				2849	case ARM::VST3q16_UPD:
				2850	case ARM::VST3q32_UPD:
				2851	case ARM::VST4q8:
				2852	case ARM::VST4q16:
				2853	case ARM::VST4q32:
				2854	case ARM::VST4q8_UPD:
				2855	case ARM::VST4q16_UPD:
				2856	case ARM::VST4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2857	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2858	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2859	break;
				2860	default:
				2861	break;
				2862	}
				2863
				2864	// Third input register
				2865	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2866	case ARM::VST3d8:
				2867	case ARM::VST3d16:
				2868	case ARM::VST3d32:
				2869	case ARM::VST3d8_UPD:
				2870	case ARM::VST3d16_UPD:
				2871	case ARM::VST3d32_UPD:
				2872	case ARM::VST4d8:
				2873	case ARM::VST4d16:
				2874	case ARM::VST4d32:
				2875	case ARM::VST4d8_UPD:
				2876	case ARM::VST4d16_UPD:
				2877	case ARM::VST4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2878	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2879	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2880	break;
				2881	case ARM::VST3q8:
				2882	case ARM::VST3q16:
				2883	case ARM::VST3q32:
				2884	case ARM::VST3q8_UPD:
				2885	case ARM::VST3q16_UPD:
				2886	case ARM::VST3q32_UPD:
				2887	case ARM::VST4q8:
				2888	case ARM::VST4q16:
				2889	case ARM::VST4q32:
				2890	case ARM::VST4q8_UPD:
				2891	case ARM::VST4q16_UPD:
				2892	case ARM::VST4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2893	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
				2894	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2895	break;
				2896	default:
				2897	break;
				2898	}
				2899
				2900	// Fourth input register
				2901	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2902	case ARM::VST4d8:
				2903	case ARM::VST4d16:
				2904	case ARM::VST4d32:
				2905	case ARM::VST4d8_UPD:
				2906	case ARM::VST4d16_UPD:
				2907	case ARM::VST4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2908	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
				2909	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2910	break;
				2911	case ARM::VST4q8:
				2912	case ARM::VST4q16:
				2913	case ARM::VST4q32:
				2914	case ARM::VST4q8_UPD:
				2915	case ARM::VST4q16_UPD:
				2916	case ARM::VST4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2917	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
				2918	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2919	break;
				2920	default:
				2921	break;
				2922	}
				2923
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2924	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2925	}
				2926
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2927	static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2928	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2929	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2930
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2931	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2932	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2933	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2934	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2935	unsigned align = fieldFromInstruction(Insn, 4, 1);
				2936	unsigned size = fieldFromInstruction(Insn, 6, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2937
Tim Northover	00e071a	2012-09-06 15:27:12 +0000	[diff] [blame]	2938	if (size == 0 && align == 1)
				2939	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2940	align *= (1 << size);
				2941
Jim Grosbach	13a292c	2012-03-06 22:01:44 +0000	[diff] [blame]	2942	switch (Inst.getOpcode()) {
				2943	case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
				2944	case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
				2945	case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
				2946	case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
				2947	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2948	return MCDisassembler::Fail;
				2949	break;
				2950	default:
				2951	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2952	return MCDisassembler::Fail;
				2953	break;
				2954	}
Owen Anderson	ac92e77	2011-08-22 18:22:06 +0000	[diff] [blame]	2955	if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2956	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2957	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2958	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2959
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2960	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2961	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	2962	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2963
Jim Grosbach	a68c9a8	2011-11-30 19:35:44 +0000	[diff] [blame]	2964	// The fixed offset post-increment encodes Rm == 0xd. The no-writeback
				2965	// variant encodes Rm == 0xf. Anything else is a register offset post-
				2966	// increment and we need to add the register operand to the instruction.
				2967	if (Rm != 0xD && Rm != 0xF &&
				2968	!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2969	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2970
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2971	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2972	}
				2973
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2974	static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2975	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2976	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2977
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2978	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2979	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2980	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2981	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2982	unsigned align = fieldFromInstruction(Insn, 4, 1);
				2983	unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2984	align = 2size;
				2985
Jim Grosbach	13a292c	2012-03-06 22:01:44 +0000	[diff] [blame]	2986	switch (Inst.getOpcode()) {
				2987	case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
				2988	case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
				2989	case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
				2990	case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
				2991	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2992	return MCDisassembler::Fail;
				2993	break;
Jim Grosbach	ed428bc	2012-03-06 23:10:38 +0000	[diff] [blame]	2994	case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
				2995	case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
				2996	case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
				2997	case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
				2998	if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
				2999	return MCDisassembler::Fail;
				3000	break;
Jim Grosbach	13a292c	2012-03-06 22:01:44 +0000	[diff] [blame]	3001	default:
				3002	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3003	return MCDisassembler::Fail;
				3004	break;
				3005	}
Kevin Enderby	520eb3b	2012-03-06 18:33:12 +0000	[diff] [blame]	3006
				3007	if (Rm != 0xF)
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3008	Inst.addOperand(MCOperand::createImm(0));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3009
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3010	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3011	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3012	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3013
Kevin Enderby	29ae538	2012-04-17 00:49:27 +0000	[diff] [blame]	3014	if (Rm != 0xD && Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3015	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3016	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3017	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3018
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3019	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3020	}
				3021
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3022	static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3023	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3024	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3025
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3026	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3027	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3028	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3029	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3030	unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3031
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3032	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3033	return MCDisassembler::Fail;
				3034	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
				3035	return MCDisassembler::Fail;
				3036	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
				3037	return MCDisassembler::Fail;
Owen Anderson	ac92e77	2011-08-22 18:22:06 +0000	[diff] [blame]	3038	if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3039	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3040	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3041	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3042
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3043	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3044	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3045	Inst.addOperand(MCOperand::createImm(0));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3046
				3047	if (Rm == 0xD)
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3048	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3049	else if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3050	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3051	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3052	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3053
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3054	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3055	}
				3056
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3057	static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3058	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3059	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3060
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3061	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3062	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3063	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3064	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3065	unsigned size = fieldFromInstruction(Insn, 6, 2);
				3066	unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
				3067	unsigned align = fieldFromInstruction(Insn, 4, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3068
				3069	if (size == 0x3) {
Tim Northover	00e071a	2012-09-06 15:27:12 +0000	[diff] [blame]	3070	if (align == 0)
				3071	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3072	align = 16;
				3073	} else {
				3074	if (size == 2) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3075	align *= 8;
				3076	} else {
				3077	size = 1 << size;
				3078	align = 4size;
				3079	}
				3080	}
				3081
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3082	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3083	return MCDisassembler::Fail;
				3084	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
				3085	return MCDisassembler::Fail;
				3086	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
				3087	return MCDisassembler::Fail;
				3088	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
				3089	return MCDisassembler::Fail;
Owen Anderson	ac92e77	2011-08-22 18:22:06 +0000	[diff] [blame]	3090	if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3091	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3092	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3093	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3094
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3095	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3096	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3097	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3098
				3099	if (Rm == 0xD)
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3100	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3101	else if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3102	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3103	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3104	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3105
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3106	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3107	}
				3108
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3109	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3110	DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	3111	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3112	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3113
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3114	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3115	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3116	unsigned imm = fieldFromInstruction(Insn, 0, 4);
				3117	imm \|= fieldFromInstruction(Insn, 16, 3) << 4;
				3118	imm \|= fieldFromInstruction(Insn, 24, 1) << 7;
				3119	imm \|= fieldFromInstruction(Insn, 8, 4) << 8;
				3120	imm \|= fieldFromInstruction(Insn, 5, 1) << 12;
				3121	unsigned Q = fieldFromInstruction(Insn, 6, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3122
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3123	if (Q) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3124	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				3125	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3126	} else {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3127	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3128	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3129	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3130
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3131	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3132
				3133	switch (Inst.getOpcode()) {
				3134	case ARM::VORRiv4i16:
				3135	case ARM::VORRiv2i32:
				3136	case ARM::VBICiv4i16:
				3137	case ARM::VBICiv2i32:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3138	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3139	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3140	break;
				3141	case ARM::VORRiv8i16:
				3142	case ARM::VORRiv4i32:
				3143	case ARM::VBICiv8i16:
				3144	case ARM::VBICiv4i32:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3145	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				3146	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3147	break;
				3148	default:
				3149	break;
				3150	}
				3151
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3152	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3153	}
				3154
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3155	static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3156	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3157	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3158
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3159	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3160	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3161	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3162	Rm \|= fieldFromInstruction(Insn, 5, 1) << 4;
				3163	unsigned size = fieldFromInstruction(Insn, 18, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3164
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3165	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				3166	return MCDisassembler::Fail;
				3167	if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
				3168	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3169	Inst.addOperand(MCOperand::createImm(8 << size));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3170
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3171	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3172	}
				3173
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3174	static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3175	uint64_t Address, const void *Decoder) {
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3176	Inst.addOperand(MCOperand::createImm(8 - Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3177	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3178	}
				3179
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3180	static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3181	uint64_t Address, const void *Decoder) {
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3182	Inst.addOperand(MCOperand::createImm(16 - Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3183	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3184	}
				3185
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3186	static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3187	uint64_t Address, const void *Decoder) {
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3188	Inst.addOperand(MCOperand::createImm(32 - Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3189	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3190	}
				3191
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3192	static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3193	uint64_t Address, const void *Decoder) {
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3194	Inst.addOperand(MCOperand::createImm(64 - Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3195	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3196	}
				3197
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3198	static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3199	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3200	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3201
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3202	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3203	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3204	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3205	Rn \|= fieldFromInstruction(Insn, 7, 1) << 4;
				3206	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3207	Rm \|= fieldFromInstruction(Insn, 5, 1) << 4;
				3208	unsigned op = fieldFromInstruction(Insn, 6, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3209
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3210	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3211	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3212	if (op) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3213	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3214	return MCDisassembler::Fail; // Writeback
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3215	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3216
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	3217	switch (Inst.getOpcode()) {
				3218	case ARM::VTBL2:
				3219	case ARM::VTBX2:
				3220	if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
				3221	return MCDisassembler::Fail;
				3222	break;
				3223	default:
				3224	if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
				3225	return MCDisassembler::Fail;
				3226	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3227
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3228	if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
				3229	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3230
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3231	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3232	}
				3233
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3234	static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3235	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3236	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3237
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3238	unsigned dst = fieldFromInstruction(Insn, 8, 3);
				3239	unsigned imm = fieldFromInstruction(Insn, 0, 8);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3240
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3241	if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
				3242	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3243
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3244	switch(Inst.getOpcode()) {
Owen Anderson	5658b49	2011-08-26 19:39:26 +0000	[diff] [blame]	3245	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3246	return MCDisassembler::Fail;
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3247	case ARM::tADR:
Owen Anderson	240d20a	2011-08-26 21:47:57 +0000	[diff] [blame]	3248	break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3249	case ARM::tADDrSPi:
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3250	Inst.addOperand(MCOperand::createReg(ARM::SP));
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3251	break;
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3252	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3253
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3254	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3255	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3256	}
				3257
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3258	static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3259	uint64_t Address, const void *Decoder) {
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	3260	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
				3261	true, 2, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3262	Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1)));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3263	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3264	}
				3265
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3266	static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3267	uint64_t Address, const void *Decoder) {
Kevin Enderby	cabbae6	2012-05-04 22:09:52 +0000	[diff] [blame]	3268	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	3269	true, 4, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3270	Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val)));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3271	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3272	}
				3273
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3274	static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3275	uint64_t Address, const void *Decoder) {
Gordon Keiser	772cf46	2013-03-28 19:22:28 +0000	[diff] [blame]	3276	if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	3277	true, 2, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3278	Inst.addOperand(MCOperand::createImm(Val << 1));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3279	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3280	}
				3281
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3282	static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3283	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3284	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3285
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3286	unsigned Rn = fieldFromInstruction(Val, 0, 3);
				3287	unsigned Rm = fieldFromInstruction(Val, 3, 3);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3288
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3289	if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3290	return MCDisassembler::Fail;
				3291	if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3292	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3293
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3294	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3295	}
				3296
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3297	static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3298	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3299	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3300
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3301	unsigned Rn = fieldFromInstruction(Val, 0, 3);
				3302	unsigned imm = fieldFromInstruction(Val, 3, 5);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3303
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3304	if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3305	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3306	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3307
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3308	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3309	}
				3310
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3311	static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3312	uint64_t Address, const void *Decoder) {
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	3313	unsigned imm = Val << 2;
				3314
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3315	Inst.addOperand(MCOperand::createImm(imm));
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	3316	tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3317
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3318	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3319	}
				3320
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3321	static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3322	uint64_t Address, const void *Decoder) {
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3323	Inst.addOperand(MCOperand::createReg(ARM::SP));
				3324	Inst.addOperand(MCOperand::createImm(Val));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3325
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3326	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3327	}
				3328
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3329	static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3330	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3331	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3332
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3333	unsigned Rn = fieldFromInstruction(Val, 6, 4);
				3334	unsigned Rm = fieldFromInstruction(Val, 2, 4);
				3335	unsigned imm = fieldFromInstruction(Val, 0, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3336
Amaury de la Vieuville	e2bb1d1	2013-06-18 08:02:56 +0000	[diff] [blame]	3337	// Thumb stores cannot use PC as dest register.
				3338	switch (Inst.getOpcode()) {
				3339	case ARM::t2STRHs:
				3340	case ARM::t2STRBs:
				3341	case ARM::t2STRs:
				3342	if (Rn == 15)
				3343	return MCDisassembler::Fail;
				3344	default:
				3345	break;
				3346	}
				3347
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3348	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3349	return MCDisassembler::Fail;
				3350	if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3351	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3352	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3353
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3354	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3355	}
				3356
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3357	static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3358	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3359	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3360
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3361	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3362	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3363
Michael Kuperstein	db0712f	2015-05-26 10:47:10 +0000	[diff] [blame]	3364	const FeatureBitset &featureBits =
				3365	((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
				3366
				3367	bool hasMP = featureBits[ARM::FeatureMP];
				3368	bool hasV7Ops = featureBits[ARM::HasV7Ops];
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3369
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3370	if (Rn == 15) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3371	switch (Inst.getOpcode()) {
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3372	case ARM::t2LDRBs:
				3373	Inst.setOpcode(ARM::t2LDRBpci);
				3374	break;
				3375	case ARM::t2LDRHs:
				3376	Inst.setOpcode(ARM::t2LDRHpci);
				3377	break;
				3378	case ARM::t2LDRSHs:
				3379	Inst.setOpcode(ARM::t2LDRSHpci);
				3380	break;
				3381	case ARM::t2LDRSBs:
				3382	Inst.setOpcode(ARM::t2LDRSBpci);
				3383	break;
				3384	case ARM::t2LDRs:
				3385	Inst.setOpcode(ARM::t2LDRpci);
				3386	break;
				3387	case ARM::t2PLDs:
				3388	Inst.setOpcode(ARM::t2PLDpci);
				3389	break;
				3390	case ARM::t2PLIs:
				3391	Inst.setOpcode(ARM::t2PLIpci);
				3392	break;
				3393	default:
				3394	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3395	}
				3396
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3397	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3398	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3399
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3400	if (Rt == 15) {
				3401	switch (Inst.getOpcode()) {
				3402	case ARM::t2LDRSHs:
				3403	return MCDisassembler::Fail;
				3404	case ARM::t2LDRHs:
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3405	Inst.setOpcode(ARM::t2PLDWs);
				3406	break;
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3407	case ARM::t2LDRSBs:
				3408	Inst.setOpcode(ARM::t2PLIs);
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3409	default:
				3410	break;
				3411	}
				3412	}
				3413
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3414	switch (Inst.getOpcode()) {
				3415	case ARM::t2PLDs:
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3416	break;
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3417	case ARM::t2PLIs:
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3418	if (!hasV7Ops)
				3419	return MCDisassembler::Fail;
				3420	break;
				3421	case ARM::t2PLDWs:
				3422	if (!hasV7Ops \|\| !hasMP)
				3423	return MCDisassembler::Fail;
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3424	break;
				3425	default:
				3426	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3427	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3428	}
				3429
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3430	unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
				3431	addrmode \|= fieldFromInstruction(Insn, 0, 4) << 2;
				3432	addrmode \|= fieldFromInstruction(Insn, 16, 4) << 6;
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3433	if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
				3434	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3435
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3436	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3437	}
				3438
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3439	static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
				3440	uint64_t Address, const void* Decoder) {
				3441	DecodeStatus S = MCDisassembler::Success;
				3442
				3443	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3444	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3445	unsigned U = fieldFromInstruction(Insn, 9, 1);
				3446	unsigned imm = fieldFromInstruction(Insn, 0, 8);
				3447	imm \|= (U << 8);
				3448	imm \|= (Rn << 9);
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3449	unsigned add = fieldFromInstruction(Insn, 9, 1);
				3450
Michael Kuperstein	db0712f	2015-05-26 10:47:10 +0000	[diff] [blame]	3451	const FeatureBitset &featureBits =
				3452	((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
				3453
				3454	bool hasMP = featureBits[ARM::FeatureMP];
				3455	bool hasV7Ops = featureBits[ARM::HasV7Ops];
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3456
				3457	if (Rn == 15) {
				3458	switch (Inst.getOpcode()) {
				3459	case ARM::t2LDRi8:
				3460	Inst.setOpcode(ARM::t2LDRpci);
				3461	break;
				3462	case ARM::t2LDRBi8:
				3463	Inst.setOpcode(ARM::t2LDRBpci);
				3464	break;
				3465	case ARM::t2LDRSBi8:
				3466	Inst.setOpcode(ARM::t2LDRSBpci);
				3467	break;
				3468	case ARM::t2LDRHi8:
				3469	Inst.setOpcode(ARM::t2LDRHpci);
				3470	break;
				3471	case ARM::t2LDRSHi8:
				3472	Inst.setOpcode(ARM::t2LDRSHpci);
				3473	break;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3474	case ARM::t2PLDi8:
				3475	Inst.setOpcode(ARM::t2PLDpci);
				3476	break;
				3477	case ARM::t2PLIi8:
				3478	Inst.setOpcode(ARM::t2PLIpci);
				3479	break;
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3480	default:
				3481	return MCDisassembler::Fail;
				3482	}
				3483	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3484	}
				3485
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3486	if (Rt == 15) {
				3487	switch (Inst.getOpcode()) {
				3488	case ARM::t2LDRSHi8:
				3489	return MCDisassembler::Fail;
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3490	case ARM::t2LDRHi8:
				3491	if (!add)
				3492	Inst.setOpcode(ARM::t2PLDWi8);
				3493	break;
				3494	case ARM::t2LDRSBi8:
				3495	Inst.setOpcode(ARM::t2PLIi8);
				3496	break;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3497	default:
				3498	break;
				3499	}
				3500	}
				3501
				3502	switch (Inst.getOpcode()) {
				3503	case ARM::t2PLDi8:
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3504	break;
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3505	case ARM::t2PLIi8:
				3506	if (!hasV7Ops)
				3507	return MCDisassembler::Fail;
				3508	break;
				3509	case ARM::t2PLDWi8:
				3510	if (!hasV7Ops \|\| !hasMP)
				3511	return MCDisassembler::Fail;
				3512	break;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3513	default:
				3514	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3515	return MCDisassembler::Fail;
				3516	}
				3517
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3518	if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
				3519	return MCDisassembler::Fail;
				3520	return S;
				3521	}
				3522
				3523	static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
				3524	uint64_t Address, const void* Decoder) {
				3525	DecodeStatus S = MCDisassembler::Success;
				3526
				3527	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3528	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3529	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				3530	imm \|= (Rn << 13);
				3531
Michael Kuperstein	db0712f	2015-05-26 10:47:10 +0000	[diff] [blame]	3532	const FeatureBitset &featureBits =
				3533	((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
				3534
				3535	bool hasMP = featureBits[ARM::FeatureMP];
				3536	bool hasV7Ops = featureBits[ARM::HasV7Ops];
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3537
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3538	if (Rn == 15) {
				3539	switch (Inst.getOpcode()) {
				3540	case ARM::t2LDRi12:
				3541	Inst.setOpcode(ARM::t2LDRpci);
				3542	break;
				3543	case ARM::t2LDRHi12:
				3544	Inst.setOpcode(ARM::t2LDRHpci);
				3545	break;
				3546	case ARM::t2LDRSHi12:
				3547	Inst.setOpcode(ARM::t2LDRSHpci);
				3548	break;
				3549	case ARM::t2LDRBi12:
				3550	Inst.setOpcode(ARM::t2LDRBpci);
				3551	break;
				3552	case ARM::t2LDRSBi12:
				3553	Inst.setOpcode(ARM::t2LDRSBpci);
				3554	break;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3555	case ARM::t2PLDi12:
				3556	Inst.setOpcode(ARM::t2PLDpci);
				3557	break;
				3558	case ARM::t2PLIi12:
				3559	Inst.setOpcode(ARM::t2PLIpci);
				3560	break;
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3561	default:
				3562	return MCDisassembler::Fail;
				3563	}
				3564	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3565	}
				3566
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3567	if (Rt == 15) {
				3568	switch (Inst.getOpcode()) {
				3569	case ARM::t2LDRSHi12:
				3570	return MCDisassembler::Fail;
				3571	case ARM::t2LDRHi12:
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3572	Inst.setOpcode(ARM::t2PLDWi12);
				3573	break;
				3574	case ARM::t2LDRSBi12:
				3575	Inst.setOpcode(ARM::t2PLIi12);
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3576	break;
				3577	default:
				3578	break;
				3579	}
				3580	}
				3581
				3582	switch (Inst.getOpcode()) {
				3583	case ARM::t2PLDi12:
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3584	break;
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3585	case ARM::t2PLIi12:
				3586	if (!hasV7Ops)
				3587	return MCDisassembler::Fail;
				3588	break;
				3589	case ARM::t2PLDWi12:
				3590	if (!hasV7Ops \|\| !hasMP)
				3591	return MCDisassembler::Fail;
				3592	break;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3593	default:
				3594	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3595	return MCDisassembler::Fail;
				3596	}
				3597
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3598	if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
				3599	return MCDisassembler::Fail;
				3600	return S;
				3601	}
				3602
				3603	static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
				3604	uint64_t Address, const void* Decoder) {
				3605	DecodeStatus S = MCDisassembler::Success;
				3606
				3607	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3608	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3609	unsigned imm = fieldFromInstruction(Insn, 0, 8);
				3610	imm \|= (Rn << 9);
				3611
				3612	if (Rn == 15) {
				3613	switch (Inst.getOpcode()) {
				3614	case ARM::t2LDRT:
				3615	Inst.setOpcode(ARM::t2LDRpci);
				3616	break;
				3617	case ARM::t2LDRBT:
				3618	Inst.setOpcode(ARM::t2LDRBpci);
				3619	break;
				3620	case ARM::t2LDRHT:
				3621	Inst.setOpcode(ARM::t2LDRHpci);
				3622	break;
				3623	case ARM::t2LDRSBT:
				3624	Inst.setOpcode(ARM::t2LDRSBpci);
				3625	break;
				3626	case ARM::t2LDRSHT:
				3627	Inst.setOpcode(ARM::t2LDRSHpci);
				3628	break;
				3629	default:
				3630	return MCDisassembler::Fail;
				3631	}
				3632	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3633	}
				3634
				3635	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3636	return MCDisassembler::Fail;
				3637	if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
				3638	return MCDisassembler::Fail;
				3639	return S;
				3640	}
				3641
				3642	static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
				3643	uint64_t Address, const void* Decoder) {
				3644	DecodeStatus S = MCDisassembler::Success;
				3645
				3646	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3647	unsigned U = fieldFromInstruction(Insn, 23, 1);
				3648	int imm = fieldFromInstruction(Insn, 0, 12);
				3649
Michael Kuperstein	db0712f	2015-05-26 10:47:10 +0000	[diff] [blame]	3650	const FeatureBitset &featureBits =
				3651	((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
				3652
				3653	bool hasV7Ops = featureBits[ARM::HasV7Ops];
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3654
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3655	if (Rt == 15) {
				3656	switch (Inst.getOpcode()) {
				3657	case ARM::t2LDRBpci:
				3658	case ARM::t2LDRHpci:
				3659	Inst.setOpcode(ARM::t2PLDpci);
				3660	break;
				3661	case ARM::t2LDRSBpci:
				3662	Inst.setOpcode(ARM::t2PLIpci);
				3663	break;
				3664	case ARM::t2LDRSHpci:
				3665	return MCDisassembler::Fail;
				3666	default:
				3667	break;
				3668	}
				3669	}
				3670
				3671	switch(Inst.getOpcode()) {
				3672	case ARM::t2PLDpci:
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3673	break;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3674	case ARM::t2PLIpci:
Oliver Stannard	39a85ab	2014-10-23 08:52:58 +0000	[diff] [blame]	3675	if (!hasV7Ops)
				3676	return MCDisassembler::Fail;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3677	break;
				3678	default:
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3679	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3680	return MCDisassembler::Fail;
				3681	}
				3682
				3683	if (!U) {
				3684	// Special case for #-0.
				3685	if (imm == 0)
				3686	imm = INT32_MIN;
				3687	else
				3688	imm = -imm;
				3689	}
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3690	Inst.addOperand(MCOperand::createImm(imm));
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3691
				3692	return S;
				3693	}
				3694
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3695	static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3696	uint64_t Address, const void *Decoder) {
Jiangning Liu	6a43bf7	2012-08-02 08:29:50 +0000	[diff] [blame]	3697	if (Val == 0)
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3698	Inst.addOperand(MCOperand::createImm(INT32_MIN));
Jiangning Liu	6a43bf7	2012-08-02 08:29:50 +0000	[diff] [blame]	3699	else {
				3700	int imm = Val & 0xFF;
				3701
				3702	if (!(Val & 0x100)) imm *= -1;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3703	Inst.addOperand(MCOperand::createImm(imm * 4));
Jiangning Liu	6a43bf7	2012-08-02 08:29:50 +0000	[diff] [blame]	3704	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3705
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3706	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3707	}
				3708
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3709	static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3710	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3711	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3712
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3713	unsigned Rn = fieldFromInstruction(Val, 9, 4);
				3714	unsigned imm = fieldFromInstruction(Val, 0, 9);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3715
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3716	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3717	return MCDisassembler::Fail;
				3718	if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
				3719	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3720
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3721	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3722	}
				3723
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3724	static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbach	a05627e	2011-09-09 18:37:27 +0000	[diff] [blame]	3725	uint64_t Address, const void *Decoder) {
				3726	DecodeStatus S = MCDisassembler::Success;
				3727
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3728	unsigned Rn = fieldFromInstruction(Val, 8, 4);
				3729	unsigned imm = fieldFromInstruction(Val, 0, 8);
Jim Grosbach	a05627e	2011-09-09 18:37:27 +0000	[diff] [blame]	3730
				3731	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				3732	return MCDisassembler::Fail;
				3733
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3734	Inst.addOperand(MCOperand::createImm(imm));
Jim Grosbach	a05627e	2011-09-09 18:37:27 +0000	[diff] [blame]	3735
				3736	return S;
				3737	}
				3738
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3739	static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3740	uint64_t Address, const void *Decoder) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3741	int imm = Val & 0xFF;
Owen Anderson	fe82365	2011-09-16 21:08:33 +0000	[diff] [blame]	3742	if (Val == 0)
				3743	imm = INT32_MIN;
				3744	else if (!(Val & 0x100))
				3745	imm *= -1;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3746	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3747
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3748	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3749	}
				3750
				3751
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3752	static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3753	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3754	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3755
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3756	unsigned Rn = fieldFromInstruction(Val, 9, 4);
				3757	unsigned imm = fieldFromInstruction(Val, 0, 9);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3758
Amaury de la Vieuville	e2bb1d1	2013-06-18 08:02:56 +0000	[diff] [blame]	3759	// Thumb stores cannot use PC as dest register.
				3760	switch (Inst.getOpcode()) {
				3761	case ARM::t2STRT:
				3762	case ARM::t2STRBT:
				3763	case ARM::t2STRHT:
				3764	case ARM::t2STRi8:
				3765	case ARM::t2STRHi8:
				3766	case ARM::t2STRBi8:
				3767	if (Rn == 15)
				3768	return MCDisassembler::Fail;
				3769	break;
				3770	default:
				3771	break;
				3772	}
				3773
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3774	// Some instructions always use an additive offset.
				3775	switch (Inst.getOpcode()) {
				3776	case ARM::t2LDRT:
				3777	case ARM::t2LDRBT:
				3778	case ARM::t2LDRHT:
				3779	case ARM::t2LDRSBT:
				3780	case ARM::t2LDRSHT:
Owen Anderson	ddfcec9	2011-09-19 18:07:10 +0000	[diff] [blame]	3781	case ARM::t2STRT:
				3782	case ARM::t2STRBT:
				3783	case ARM::t2STRHT:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3784	imm \|= 0x100;
				3785	break;
				3786	default:
				3787	break;
				3788	}
				3789
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3790	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3791	return MCDisassembler::Fail;
				3792	if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
				3793	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3794
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3795	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3796	}
				3797
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3798	static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3799	uint64_t Address, const void *Decoder) {
				3800	DecodeStatus S = MCDisassembler::Success;
				3801
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3802	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3803	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3804	unsigned addr = fieldFromInstruction(Insn, 0, 8);
				3805	addr \|= fieldFromInstruction(Insn, 9, 1) << 8;
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3806	addr \|= Rn << 9;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3807	unsigned load = fieldFromInstruction(Insn, 20, 1);
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3808
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3809	if (Rn == 15) {
				3810	switch (Inst.getOpcode()) {
				3811	case ARM::t2LDR_PRE:
				3812	case ARM::t2LDR_POST:
				3813	Inst.setOpcode(ARM::t2LDRpci);
				3814	break;
				3815	case ARM::t2LDRB_PRE:
				3816	case ARM::t2LDRB_POST:
				3817	Inst.setOpcode(ARM::t2LDRBpci);
				3818	break;
				3819	case ARM::t2LDRH_PRE:
				3820	case ARM::t2LDRH_POST:
				3821	Inst.setOpcode(ARM::t2LDRHpci);
				3822	break;
				3823	case ARM::t2LDRSB_PRE:
				3824	case ARM::t2LDRSB_POST:
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3825	if (Rt == 15)
				3826	Inst.setOpcode(ARM::t2PLIpci);
				3827	else
				3828	Inst.setOpcode(ARM::t2LDRSBpci);
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3829	break;
				3830	case ARM::t2LDRSH_PRE:
				3831	case ARM::t2LDRSH_POST:
				3832	Inst.setOpcode(ARM::t2LDRSHpci);
				3833	break;
				3834	default:
				3835	return MCDisassembler::Fail;
				3836	}
				3837	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3838	}
				3839
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3840	if (!load) {
				3841	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3842	return MCDisassembler::Fail;
				3843	}
				3844
Joe Abbey	f686be4	2013-03-26 13:58:53 +0000	[diff] [blame]	3845	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3846	return MCDisassembler::Fail;
				3847
				3848	if (load) {
				3849	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3850	return MCDisassembler::Fail;
				3851	}
				3852
				3853	if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
				3854	return MCDisassembler::Fail;
				3855
				3856	return S;
				3857	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3858
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3859	static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3860	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3861	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3862
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3863	unsigned Rn = fieldFromInstruction(Val, 13, 4);
				3864	unsigned imm = fieldFromInstruction(Val, 0, 12);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3865
Amaury de la Vieuville	e2bb1d1	2013-06-18 08:02:56 +0000	[diff] [blame]	3866	// Thumb stores cannot use PC as dest register.
				3867	switch (Inst.getOpcode()) {
				3868	case ARM::t2STRi12:
				3869	case ARM::t2STRBi12:
				3870	case ARM::t2STRHi12:
				3871	if (Rn == 15)
				3872	return MCDisassembler::Fail;
				3873	default:
				3874	break;
				3875	}
				3876
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3877	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3878	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3879	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3880
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3881	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3882	}
				3883
				3884
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3885	static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3886	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3887	unsigned imm = fieldFromInstruction(Insn, 0, 7);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3888
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3889	Inst.addOperand(MCOperand::createReg(ARM::SP));
				3890	Inst.addOperand(MCOperand::createReg(ARM::SP));
				3891	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3892
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3893	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3894	}
				3895
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3896	static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3897	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3898	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3899
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3900	if (Inst.getOpcode() == ARM::tADDrSP) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3901	unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
				3902	Rdm \|= fieldFromInstruction(Insn, 7, 1) << 3;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3903
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3904	if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
				3905	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3906	Inst.addOperand(MCOperand::createReg(ARM::SP));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3907	if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
				3908	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3909	} else if (Inst.getOpcode() == ARM::tADDspr) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3910	unsigned Rm = fieldFromInstruction(Insn, 3, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3911
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3912	Inst.addOperand(MCOperand::createReg(ARM::SP));
				3913	Inst.addOperand(MCOperand::createReg(ARM::SP));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3914	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3915	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3916	}
				3917
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3918	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3919	}
				3920
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3921	static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3922	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3923	unsigned imod = fieldFromInstruction(Insn, 4, 1) \| 0x2;
				3924	unsigned flags = fieldFromInstruction(Insn, 0, 3);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3925
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3926	Inst.addOperand(MCOperand::createImm(imod));
				3927	Inst.addOperand(MCOperand::createImm(flags));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3928
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3929	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3930	}
				3931
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3932	static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3933	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3934	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3935	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3936	unsigned add = fieldFromInstruction(Insn, 4, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3937
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	3938	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3939	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3940	Inst.addOperand(MCOperand::createImm(add));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3941
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3942	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3943	}
				3944
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3945	static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3946	uint64_t Address, const void *Decoder) {
NAKAMURA Takumi	70c1aa0	2012-05-22 21:47:02 +0000	[diff] [blame]	3947	// Val is passed in as S:J1:J2:imm10H:imm10L:'0'
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3948	// Note only one trailing zero not two. Also the J1 and J2 values are from
				3949	// the encoded instruction. So here change to I1 and I2 values via:
				3950	// I1 = NOT(J1 EOR S);
				3951	// I2 = NOT(J2 EOR S);
				3952	// and build the imm32 with two trailing zeros as documented:
NAKAMURA Takumi	70c1aa0	2012-05-22 21:47:02 +0000	[diff] [blame]	3953	// imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3954	unsigned S = (Val >> 23) & 1;
				3955	unsigned J1 = (Val >> 22) & 1;
				3956	unsigned J2 = (Val >> 21) & 1;
				3957	unsigned I1 = !(J1 ^ S);
				3958	unsigned I2 = !(J2 ^ S);
				3959	unsigned tmp = (Val & ~0x600000) \| (I1 << 22) \| (I2 << 21);
				3960	int imm32 = SignExtend32<25>(tmp << 1);
				3961
Jim Grosbach	79ebc51	2011-10-20 17:28:20 +0000	[diff] [blame]	3962	if (!tryAddingSymbolicOperand(Address,
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3963	(Address & ~2u) + imm32 + 4,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	3964	true, 4, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3965	Inst.addOperand(MCOperand::createImm(imm32));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3966	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3967	}
				3968
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3969	static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3970	uint64_t Address, const void *Decoder) {
				3971	if (Val == 0xA \|\| Val == 0xB)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3972	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3973
Michael Kuperstein	db0712f	2015-05-26 10:47:10 +0000	[diff] [blame]	3974	const FeatureBitset &featureBits =
				3975	((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
				3976
				3977	if (featureBits[ARM::HasV8Ops] && !(Val == 14 \|\| Val == 15))
Artyom Skrobov	e686cec	2013-11-08 16:16:30 +0000	[diff] [blame]	3978	return MCDisassembler::Fail;
				3979
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	3980	Inst.addOperand(MCOperand::createImm(Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3981	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3982	}
				3983
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3984	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3985	DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
Jim Grosbach	05541f4	2011-09-19 22:21:13 +0000	[diff] [blame]	3986	uint64_t Address, const void *Decoder) {
				3987	DecodeStatus S = MCDisassembler::Success;
				3988
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3989	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3990	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Jim Grosbach	05541f4	2011-09-19 22:21:13 +0000	[diff] [blame]	3991
				3992	if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
				3993	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3994	return MCDisassembler::Fail;
				3995	if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3996	return MCDisassembler::Fail;
				3997	return S;
				3998	}
				3999
				4000	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4001	DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	4002	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4003	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4004
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4005	unsigned pred = fieldFromInstruction(Insn, 22, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4006	if (pred == 0xE \|\| pred == 0xF) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4007	unsigned opc = fieldFromInstruction(Insn, 4, 28);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4008	switch (opc) {
				4009	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4010	return MCDisassembler::Fail;
Owen Anderson	4af0aa9	2011-08-31 22:00:41 +0000	[diff] [blame]	4011	case 0xf3bf8f4:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4012	Inst.setOpcode(ARM::t2DSB);
				4013	break;
Owen Anderson	4af0aa9	2011-08-31 22:00:41 +0000	[diff] [blame]	4014	case 0xf3bf8f5:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4015	Inst.setOpcode(ARM::t2DMB);
				4016	break;
Owen Anderson	4af0aa9	2011-08-31 22:00:41 +0000	[diff] [blame]	4017	case 0xf3bf8f6:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4018	Inst.setOpcode(ARM::t2ISB);
Owen Anderson	cd5612d	2011-09-07 17:55:19 +0000	[diff] [blame]	4019	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4020	}
				4021
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4022	unsigned imm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	4023	return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4024	}
				4025
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4026	unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
				4027	brtarget \|= fieldFromInstruction(Insn, 11, 1) << 19;
				4028	brtarget \|= fieldFromInstruction(Insn, 13, 1) << 18;
				4029	brtarget \|= fieldFromInstruction(Insn, 16, 6) << 12;
				4030	brtarget \|= fieldFromInstruction(Insn, 26, 1) << 20;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4031
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4032	if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
				4033	return MCDisassembler::Fail;
				4034	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4035	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4036
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4037	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4038	}
				4039
				4040	// Decode a shifted immediate operand. These basically consist
				4041	// of an 8-bit value, and a 4-bit directive that specifies either
				4042	// a splat operation or a rotation.
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4043	static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4044	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4045	unsigned ctrl = fieldFromInstruction(Val, 10, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4046	if (ctrl == 0) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4047	unsigned byte = fieldFromInstruction(Val, 8, 2);
				4048	unsigned imm = fieldFromInstruction(Val, 0, 8);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4049	switch (byte) {
				4050	case 0:
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4051	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4052	break;
				4053	case 1:
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4054	Inst.addOperand(MCOperand::createImm((imm << 16) \| imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4055	break;
				4056	case 2:
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4057	Inst.addOperand(MCOperand::createImm((imm << 24) \| (imm << 8)));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4058	break;
				4059	case 3:
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4060	Inst.addOperand(MCOperand::createImm((imm << 24) \| (imm << 16) \|
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4061	(imm << 8) \| imm));
				4062	break;
				4063	}
				4064	} else {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4065	unsigned unrot = fieldFromInstruction(Val, 0, 7) \| 0x80;
				4066	unsigned rot = fieldFromInstruction(Val, 7, 5);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4067	unsigned imm = (unrot >> rot) \| (unrot << ((32-rot)&31));
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4068	Inst.addOperand(MCOperand::createImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4069	}
				4070
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4071	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4072	}
				4073
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4074	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4075	DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	4076	uint64_t Address, const void *Decoder){
Richard Barton	f1ef87d	2012-06-06 09:12:53 +0000	[diff] [blame]	4077	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	4078	true, 2, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4079	Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1)));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4080	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4081	}
				4082
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4083	static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	4084	uint64_t Address, const void *Decoder){
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	4085	// Val is passed in as S:J1:J2:imm10:imm11
				4086	// Note no trailing zero after imm11. Also the J1 and J2 values are from
				4087	// the encoded instruction. So here change to I1 and I2 values via:
				4088	// I1 = NOT(J1 EOR S);
				4089	// I2 = NOT(J2 EOR S);
				4090	// and build the imm32 with one trailing zero as documented:
NAKAMURA Takumi	70c1aa0	2012-05-22 21:47:02 +0000	[diff] [blame]	4091	// imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	4092	unsigned S = (Val >> 23) & 1;
				4093	unsigned J1 = (Val >> 22) & 1;
				4094	unsigned J2 = (Val >> 21) & 1;
				4095	unsigned I1 = !(J1 ^ S);
				4096	unsigned I2 = !(J2 ^ S);
				4097	unsigned tmp = (Val & ~0x600000) \| (I1 << 22) \| (I2 << 21);
				4098	int imm32 = SignExtend32<25>(tmp << 1);
				4099
				4100	if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
Kevin Enderby	6fbcd8d	2012-02-23 18:18:17 +0000	[diff] [blame]	4101	true, 4, Inst, Decoder))
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4102	Inst.addOperand(MCOperand::createImm(imm32));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4103	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	4104	}
				4105
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4106	static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	4107	uint64_t Address, const void *Decoder) {
Jiangning Liu	288e1af	2012-08-02 08:21:27 +0000	[diff] [blame]	4108	if (Val & ~0xf)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4109	return MCDisassembler::Fail;
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	4110
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4111	Inst.addOperand(MCOperand::createImm(Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4112	return MCDisassembler::Success;
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	4113	}
				4114
Amaury de la Vieuville	43cb13a	2013-06-10 14:17:08 +0000	[diff] [blame]	4115	static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
				4116	uint64_t Address, const void *Decoder) {
				4117	if (Val & ~0xf)
				4118	return MCDisassembler::Fail;
				4119
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4120	Inst.addOperand(MCOperand::createImm(Val));
Amaury de la Vieuville	43cb13a	2013-06-10 14:17:08 +0000	[diff] [blame]	4121	return MCDisassembler::Success;
				4122	}
				4123
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4124	static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	4125	uint64_t Address, const void *Decoder) {
Renato Golin	92c816c	2014-09-01 11:25:07 +0000	[diff] [blame]	4126	DecodeStatus S = MCDisassembler::Success;
Michael Kuperstein	db0712f	2015-05-26 10:47:10 +0000	[diff] [blame]	4127	const FeatureBitset &FeatureBits =
				4128	((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
				4129
				4130	if (FeatureBits[ARM::FeatureMClass]) {
James Molloy	137ce60	2014-08-01 12:42:11 +0000	[diff] [blame]	4131	unsigned ValLow = Val & 0xff;
				4132
				4133	// Validate the SYSm value first.
				4134	switch (ValLow) {
				4135	case 0: // apsr
				4136	case 1: // iapsr
				4137	case 2: // eapsr
				4138	case 3: // xpsr
				4139	case 5: // ipsr
				4140	case 6: // epsr
				4141	case 7: // iepsr
				4142	case 8: // msp
				4143	case 9: // psp
				4144	case 16: // primask
				4145	case 20: // control
				4146	break;
				4147	case 17: // basepri
				4148	case 18: // basepri_max
				4149	case 19: // faultmask
Michael Kuperstein	db0712f	2015-05-26 10:47:10 +0000	[diff] [blame]	4150	if (!(FeatureBits[ARM::HasV7Ops]))
James Molloy	137ce60	2014-08-01 12:42:11 +0000	[diff] [blame]	4151	// Values basepri, basepri_max and faultmask are only valid for v7m.
				4152	return MCDisassembler::Fail;
				4153	break;
Bradley Smith	f277c8a	2016-01-25 11:25:36 +0000	[diff] [blame]	4154	case 0x8a: // msplim_ns
				4155	case 0x8b: // psplim_ns
				4156	case 0x91: // basepri_ns
				4157	case 0x92: // basepri_max_ns
				4158	case 0x93: // faultmask_ns
				4159	if (!(FeatureBits[ARM::HasV8MMainlineOps]))
				4160	return MCDisassembler::Fail;
Justin Bogner	cd1d5aa	2016-08-17 20:30:52 +0000	[diff] [blame]	4161	LLVM_FALLTHROUGH;
Bradley Smith	f277c8a	2016-01-25 11:25:36 +0000	[diff] [blame]	4162	case 10: // msplim
				4163	case 11: // psplim
				4164	case 0x88: // msp_ns
				4165	case 0x89: // psp_ns
				4166	case 0x90: // primask_ns
				4167	case 0x94: // control_ns
				4168	case 0x98: // sp_ns
				4169	if (!(FeatureBits[ARM::Feature8MSecExt]))
				4170	return MCDisassembler::Fail;
				4171	break;
James Molloy	137ce60	2014-08-01 12:42:11 +0000	[diff] [blame]	4172	default:
				4173	return MCDisassembler::Fail;
				4174	}
				4175
Renato Golin	92c816c	2014-09-01 11:25:07 +0000	[diff] [blame]	4176	if (Inst.getOpcode() == ARM::t2MSR_M) {
				4177	unsigned Mask = fieldFromInstruction(Val, 10, 2);
Michael Kuperstein	db0712f	2015-05-26 10:47:10 +0000	[diff] [blame]	4178	if (!(FeatureBits[ARM::HasV7Ops])) {
Renato Golin	92c816c	2014-09-01 11:25:07 +0000	[diff] [blame]	4179	// The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
				4180	// unpredictable.
				4181	if (Mask != 2)
				4182	S = MCDisassembler::SoftFail;
				4183	}
				4184	else {
				4185	// The ARMv7-M architecture stores an additional 2-bit mask value in
				4186	// MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and
				4187	// xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if
				4188	// the NZCVQ bits should be moved by the instruction. Bit mask{0}
				4189	// indicates the move for the GE{3:0} bits, the mask{0} bit can be set
				4190	// only if the processor includes the DSP extension.
				4191	if (Mask == 0 \|\| (Mask != 2 && ValLow > 3) \|\|
Artyom Skrobov	cf29644	2015-09-24 17:31:16 +0000	[diff] [blame]	4192	(!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1)))
Renato Golin	92c816c	2014-09-01 11:25:07 +0000	[diff] [blame]	4193	S = MCDisassembler::SoftFail;
				4194	}
James Molloy	137ce60	2014-08-01 12:42:11 +0000	[diff] [blame]	4195	}
				4196	} else {
				4197	// A/R class
				4198	if (Val == 0)
				4199	return MCDisassembler::Fail;
				4200	}
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4201	Inst.addOperand(MCOperand::createImm(Val));
Renato Golin	92c816c	2014-09-01 11:25:07 +0000	[diff] [blame]	4202	return S;
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	4203	}
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4204
Tim Northover	ee843ef	2014-08-15 10:47:12 +0000	[diff] [blame]	4205	static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,
				4206	uint64_t Address, const void *Decoder) {
				4207
				4208	unsigned R = fieldFromInstruction(Val, 5, 1);
				4209	unsigned SysM = fieldFromInstruction(Val, 0, 5);
				4210
				4211	// The table of encodings for these banked registers comes from B9.2.3 of the
				4212	// ARM ARM. There are patterns, but nothing regular enough to make this logic
				4213	// neater. So by fiat, these values are UNPREDICTABLE:
				4214	if (!R) {
				4215	if (SysM == 0x7 \|\| SysM == 0xf \|\| SysM == 0x18 \|\| SysM == 0x19 \|\|
				4216	SysM == 0x1a \|\| SysM == 0x1b)
				4217	return MCDisassembler::SoftFail;
				4218	} else {
				4219	if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 &&
				4220	SysM != 0x16 && SysM != 0x1c && SysM != 0x1e)
				4221	return MCDisassembler::SoftFail;
				4222	}
				4223
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4224	Inst.addOperand(MCOperand::createImm(Val));
Tim Northover	ee843ef	2014-08-15 10:47:12 +0000	[diff] [blame]	4225	return MCDisassembler::Success;
				4226	}
				4227
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4228	static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	4229	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4230	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4231
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4232	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4233	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4234	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	4235
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	4236	if (Rn == 0xF)
				4237	S = MCDisassembler::SoftFail;
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	4238
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	4239	if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4240	return MCDisassembler::Fail;
				4241	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4242	return MCDisassembler::Fail;
				4243	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4244	return MCDisassembler::Fail;
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	4245
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4246	return S;
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	4247	}
				4248
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4249	static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	4250	uint64_t Address, const void *Decoder){
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4251	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4252
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4253	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4254	unsigned Rt = fieldFromInstruction(Insn, 0, 4);
				4255	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4256	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4257
Tim Northover	27ff504	2013-04-19 15:44:32 +0000	[diff] [blame]	4258	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4259	return MCDisassembler::Fail;
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4260
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	4261	if (Rn == 0xF \|\| Rd == Rn \|\| Rd == Rt \|\| Rd == Rt+1)
				4262	S = MCDisassembler::SoftFail;
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4263
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	4264	if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4265	return MCDisassembler::Fail;
				4266	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4267	return MCDisassembler::Fail;
				4268	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4269	return MCDisassembler::Fail;
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4270
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4271	return S;
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4272	}
				4273
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4274	static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4275	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4276	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4277
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4278	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4279	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4280	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				4281	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				4282	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				4283	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4284
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4285	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4286
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4287	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4288	return MCDisassembler::Fail;
				4289	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4290	return MCDisassembler::Fail;
				4291	if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
				4292	return MCDisassembler::Fail;
				4293	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4294	return MCDisassembler::Fail;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4295
				4296	return S;
				4297	}
				4298
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4299	static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4300	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4301	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4302
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4303	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4304	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4305	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				4306	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				4307	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				4308	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				4309	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4310
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4311	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
				4312	if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4313
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4314	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4315	return MCDisassembler::Fail;
				4316	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4317	return MCDisassembler::Fail;
				4318	if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
				4319	return MCDisassembler::Fail;
				4320	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4321	return MCDisassembler::Fail;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4322
				4323	return S;
				4324	}
				4325
				4326
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4327	static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4328	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4329	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4330
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4331	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4332	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4333	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				4334	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				4335	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				4336	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4337
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4338	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4339
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4340	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4341	return MCDisassembler::Fail;
				4342	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4343	return MCDisassembler::Fail;
				4344	if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
				4345	return MCDisassembler::Fail;
				4346	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4347	return MCDisassembler::Fail;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4348
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4349	return S;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4350	}
				4351
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4352	static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4353	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4354	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4355
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4356	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4357	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4358	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				4359	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				4360	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				4361	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4362
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4363	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4364
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4365	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4366	return MCDisassembler::Fail;
				4367	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4368	return MCDisassembler::Fail;
				4369	if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
				4370	return MCDisassembler::Fail;
				4371	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4372	return MCDisassembler::Fail;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4373
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4374	return S;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4375	}
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4376
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4377	static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4378	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4379	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4380
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4381	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4382	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4383	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4384	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4385	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4386
				4387	unsigned align = 0;
				4388	unsigned index = 0;
				4389	switch (size) {
				4390	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4391	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4392	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4393	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4394	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4395	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4396	break;
				4397	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4398	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4399	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4400	index = fieldFromInstruction(Insn, 6, 2);
				4401	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4402	align = 2;
				4403	break;
				4404	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4405	if (fieldFromInstruction(Insn, 6, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4406	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4407	index = fieldFromInstruction(Insn, 7, 1);
Tim Northover	fb3cdd8	2012-09-06 15:17:49 +0000	[diff] [blame]	4408
				4409	switch (fieldFromInstruction(Insn, 4, 2)) {
				4410	case 0 :
				4411	align = 0; break;
				4412	case 3:
				4413	align = 4; break;
				4414	default:
				4415	return MCDisassembler::Fail;
				4416	}
				4417	break;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4418	}
				4419
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4420	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4421	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4422	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4423	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4424	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4425	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4426	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4427	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4428	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4429	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4430	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4431	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4432	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4433	} else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4434	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4435	}
				4436
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4437	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4438	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4439	Inst.addOperand(MCOperand::createImm(index));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4440
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4441	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4442	}
				4443
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4444	static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4445	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4446	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4447
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4448	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4449	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4450	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4451	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4452	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4453
				4454	unsigned align = 0;
				4455	unsigned index = 0;
				4456	switch (size) {
				4457	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4458	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4459	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4460	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4461	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4462	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4463	break;
				4464	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4465	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4466	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4467	index = fieldFromInstruction(Insn, 6, 2);
				4468	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4469	align = 2;
				4470	break;
				4471	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4472	if (fieldFromInstruction(Insn, 6, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4473	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4474	index = fieldFromInstruction(Insn, 7, 1);
Tim Northover	fb3cdd8	2012-09-06 15:17:49 +0000	[diff] [blame]	4475
				4476	switch (fieldFromInstruction(Insn, 4, 2)) {
				4477	case 0:
				4478	align = 0; break;
				4479	case 3:
				4480	align = 4; break;
				4481	default:
				4482	return MCDisassembler::Fail;
				4483	}
				4484	break;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4485	}
				4486
				4487	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4488	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4489	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4490	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4491	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4492	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4493	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4494	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4495	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4496	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4497	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4498	} else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4499	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4500	}
				4501
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4502	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4503	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4504	Inst.addOperand(MCOperand::createImm(index));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4505
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4506	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4507	}
				4508
				4509
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4510	static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4511	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4512	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4513
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4514	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4515	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4516	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4517	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4518	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4519
				4520	unsigned align = 0;
				4521	unsigned index = 0;
				4522	unsigned inc = 1;
				4523	switch (size) {
				4524	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4525	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4526	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4527	index = fieldFromInstruction(Insn, 5, 3);
				4528	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4529	align = 2;
				4530	break;
				4531	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4532	index = fieldFromInstruction(Insn, 6, 2);
				4533	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4534	align = 4;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4535	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4536	inc = 2;
				4537	break;
				4538	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4539	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4540	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4541	index = fieldFromInstruction(Insn, 7, 1);
				4542	if (fieldFromInstruction(Insn, 4, 1) != 0)
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4543	align = 8;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4544	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4545	inc = 2;
				4546	break;
				4547	}
				4548
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4549	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4550	return MCDisassembler::Fail;
				4551	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4552	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4553	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4554	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4555	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4556	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4557	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4558	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4559	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4560	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4561	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4562	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4563	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4564	} else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4565	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4566	}
				4567
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4568	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4569	return MCDisassembler::Fail;
				4570	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4571	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4572	Inst.addOperand(MCOperand::createImm(index));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4573
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4574	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4575	}
				4576
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4577	static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4578	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4579	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4580
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4581	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4582	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4583	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4584	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4585	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4586
				4587	unsigned align = 0;
				4588	unsigned index = 0;
				4589	unsigned inc = 1;
				4590	switch (size) {
				4591	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4592	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4593	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4594	index = fieldFromInstruction(Insn, 5, 3);
				4595	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4596	align = 2;
				4597	break;
				4598	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4599	index = fieldFromInstruction(Insn, 6, 2);
				4600	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4601	align = 4;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4602	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4603	inc = 2;
				4604	break;
				4605	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4606	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4607	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4608	index = fieldFromInstruction(Insn, 7, 1);
				4609	if (fieldFromInstruction(Insn, 4, 1) != 0)
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4610	align = 8;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4611	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4612	inc = 2;
				4613	break;
				4614	}
				4615
				4616	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4617	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4618	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4619	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4620	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4621	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4622	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4623	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4624	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4625	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4626	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4627	} else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4628	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4629	}
				4630
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4631	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4632	return MCDisassembler::Fail;
				4633	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4634	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4635	Inst.addOperand(MCOperand::createImm(index));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4636
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4637	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4638	}
				4639
				4640
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4641	static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4642	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4643	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4644
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4645	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4646	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4647	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4648	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4649	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4650
				4651	unsigned align = 0;
				4652	unsigned index = 0;
				4653	unsigned inc = 1;
				4654	switch (size) {
				4655	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4656	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4657	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4658	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4659	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4660	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4661	break;
				4662	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4663	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4664	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4665	index = fieldFromInstruction(Insn, 6, 2);
				4666	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4667	inc = 2;
				4668	break;
				4669	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4670	if (fieldFromInstruction(Insn, 4, 2))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4671	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4672	index = fieldFromInstruction(Insn, 7, 1);
				4673	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4674	inc = 2;
				4675	break;
				4676	}
				4677
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4678	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4679	return MCDisassembler::Fail;
				4680	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4681	return MCDisassembler::Fail;
				4682	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4683	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4684
				4685	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4686	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4687	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4688	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4689	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4690	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4691	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	4692	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4693	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4694	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4695	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4696	} else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4697	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4698	}
				4699
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4700	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4701	return MCDisassembler::Fail;
				4702	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4703	return MCDisassembler::Fail;
				4704	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4705	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4706	Inst.addOperand(MCOperand::createImm(index));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4707
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4708	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4709	}
				4710
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4711	static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4712	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4713	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4714
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4715	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4716	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4717	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4718	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4719	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4720
				4721	unsigned align = 0;
				4722	unsigned index = 0;
				4723	unsigned inc = 1;
				4724	switch (size) {
				4725	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4726	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4727	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4728	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4729	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4730	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4731	break;
				4732	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4733	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4734	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4735	index = fieldFromInstruction(Insn, 6, 2);
				4736	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4737	inc = 2;
				4738	break;
				4739	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4740	if (fieldFromInstruction(Insn, 4, 2))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4741	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4742	index = fieldFromInstruction(Insn, 7, 1);
				4743	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4744	inc = 2;
				4745	break;
				4746	}
				4747
				4748	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4749	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4750	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4751	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4752	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4753	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4754	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4755	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4756	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4757	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4758	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4759	} else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4760	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4761	}
				4762
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4763	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4764	return MCDisassembler::Fail;
				4765	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4766	return MCDisassembler::Fail;
				4767	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4768	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4769	Inst.addOperand(MCOperand::createImm(index));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4770
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4771	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4772	}
				4773
				4774
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4775	static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4776	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4777	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4778
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4779	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4780	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4781	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4782	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4783	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4784
				4785	unsigned align = 0;
				4786	unsigned index = 0;
				4787	unsigned inc = 1;
				4788	switch (size) {
				4789	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4790	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4791	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4792	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4793	align = 4;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4794	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4795	break;
				4796	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4797	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4798	align = 8;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4799	index = fieldFromInstruction(Insn, 6, 2);
				4800	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4801	inc = 2;
				4802	break;
				4803	case 2:
Tim Northover	fb3cdd8	2012-09-06 15:17:49 +0000	[diff] [blame]	4804	switch (fieldFromInstruction(Insn, 4, 2)) {
				4805	case 0:
				4806	align = 0; break;
				4807	case 3:
				4808	return MCDisassembler::Fail;
				4809	default:
				4810	align = 4 << fieldFromInstruction(Insn, 4, 2); break;
				4811	}
				4812
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4813	index = fieldFromInstruction(Insn, 7, 1);
				4814	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4815	inc = 2;
				4816	break;
				4817	}
				4818
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4819	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4820	return MCDisassembler::Fail;
				4821	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4822	return MCDisassembler::Fail;
				4823	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4824	return MCDisassembler::Fail;
				4825	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				4826	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4827
				4828	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4829	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4830	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4831	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4832	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4833	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4834	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4835	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4836	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4837	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4838	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4839	} else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4840	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4841	}
				4842
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4843	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4844	return MCDisassembler::Fail;
				4845	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4846	return MCDisassembler::Fail;
				4847	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4848	return MCDisassembler::Fail;
				4849	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				4850	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4851	Inst.addOperand(MCOperand::createImm(index));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4852
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4853	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4854	}
				4855
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4856	static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4857	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4858	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4859
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4860	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4861	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4862	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4863	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4864	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4865
				4866	unsigned align = 0;
				4867	unsigned index = 0;
				4868	unsigned inc = 1;
				4869	switch (size) {
				4870	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4871	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4872	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4873	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4874	align = 4;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4875	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4876	break;
				4877	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4878	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4879	align = 8;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4880	index = fieldFromInstruction(Insn, 6, 2);
				4881	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4882	inc = 2;
				4883	break;
				4884	case 2:
Tim Northover	fb3cdd8	2012-09-06 15:17:49 +0000	[diff] [blame]	4885	switch (fieldFromInstruction(Insn, 4, 2)) {
				4886	case 0:
				4887	align = 0; break;
				4888	case 3:
				4889	return MCDisassembler::Fail;
				4890	default:
				4891	align = 4 << fieldFromInstruction(Insn, 4, 2); break;
				4892	}
				4893
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4894	index = fieldFromInstruction(Insn, 7, 1);
				4895	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4896	inc = 2;
				4897	break;
				4898	}
				4899
				4900	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4901	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4902	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4903	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4904	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4905	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4906	Inst.addOperand(MCOperand::createImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4907	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4908	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4909	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4910	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4911	} else
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4912	Inst.addOperand(MCOperand::createReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4913	}
				4914
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4915	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4916	return MCDisassembler::Fail;
				4917	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4918	return MCDisassembler::Fail;
				4919	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4920	return MCDisassembler::Fail;
				4921	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				4922	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4923	Inst.addOperand(MCOperand::createImm(index));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4924
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4925	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4926	}
				4927
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4928	static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4929	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4930	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4931	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4932	unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
				4933	unsigned Rm = fieldFromInstruction(Insn, 5, 1);
				4934	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				4935	Rm \|= fieldFromInstruction(Insn, 0, 4) << 1;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4936
				4937	if (Rt == 0xF \|\| Rt2 == 0xF \|\| Rm == 0x1F)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4938	S = MCDisassembler::SoftFail;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4939
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4940	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
				4941	return MCDisassembler::Fail;
				4942	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
				4943	return MCDisassembler::Fail;
				4944	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
				4945	return MCDisassembler::Fail;
				4946	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
				4947	return MCDisassembler::Fail;
				4948	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4949	return MCDisassembler::Fail;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4950
				4951	return S;
				4952	}
				4953
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4954	static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4955	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4956	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4957	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4958	unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
				4959	unsigned Rm = fieldFromInstruction(Insn, 5, 1);
				4960	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				4961	Rm \|= fieldFromInstruction(Insn, 0, 4) << 1;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4962
				4963	if (Rt == 0xF \|\| Rt2 == 0xF \|\| Rm == 0x1F)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4964	S = MCDisassembler::SoftFail;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4965
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4966	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
				4967	return MCDisassembler::Fail;
				4968	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
				4969	return MCDisassembler::Fail;
				4970	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
				4971	return MCDisassembler::Fail;
				4972	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
				4973	return MCDisassembler::Fail;
				4974	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4975	return MCDisassembler::Fail;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4976
				4977	return S;
				4978	}
Owen Anderson	eb1367b	2011-08-22 23:44:04 +0000	[diff] [blame]	4979
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4980	static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	4981	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4982	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4983	unsigned pred = fieldFromInstruction(Insn, 4, 4);
				4984	unsigned mask = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	4985
				4986	if (pred == 0xF) {
				4987	pred = 0xE;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4988	S = MCDisassembler::SoftFail;
Owen Anderson	5230041	2011-08-24 17:21:43 +0000	[diff] [blame]	4989	}
				4990
Amaury de la Vieuville	2f0ac8d	2013-06-24 09:11:45 +0000	[diff] [blame]	4991	if (mask == 0x0)
				4992	return MCDisassembler::Fail;
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	4993
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	4994	Inst.addOperand(MCOperand::createImm(pred));
				4995	Inst.addOperand(MCOperand::createImm(mask));
Owen Anderson	37612a3	2011-08-24 22:40:22 +0000	[diff] [blame]	4996	return S;
				4997	}
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	4998
				4999	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	5000	DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	5001	uint64_t Address, const void *Decoder) {
				5002	DecodeStatus S = MCDisassembler::Success;
				5003
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5004	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				5005	unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
				5006	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				5007	unsigned addr = fieldFromInstruction(Insn, 0, 8);
				5008	unsigned W = fieldFromInstruction(Insn, 21, 1);
				5009	unsigned U = fieldFromInstruction(Insn, 23, 1);
				5010	unsigned P = fieldFromInstruction(Insn, 24, 1);
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	5011	bool writeback = (W == 1) \| (P == 0);
				5012
				5013	addr \|= (U << 8) \| (Rn << 9);
				5014
				5015	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				5016	Check(S, MCDisassembler::SoftFail);
				5017	if (Rt == Rt2)
				5018	Check(S, MCDisassembler::SoftFail);
				5019
				5020	// Rt
				5021	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
				5022	return MCDisassembler::Fail;
				5023	// Rt2
				5024	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
				5025	return MCDisassembler::Fail;
				5026	// Writeback operand
				5027	if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
				5028	return MCDisassembler::Fail;
				5029	// addr
				5030	if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
				5031	return MCDisassembler::Fail;
				5032
				5033	return S;
				5034	}
				5035
				5036	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	5037	DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	5038	uint64_t Address, const void *Decoder) {
				5039	DecodeStatus S = MCDisassembler::Success;
				5040
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5041	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				5042	unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
				5043	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				5044	unsigned addr = fieldFromInstruction(Insn, 0, 8);
				5045	unsigned W = fieldFromInstruction(Insn, 21, 1);
				5046	unsigned U = fieldFromInstruction(Insn, 23, 1);
				5047	unsigned P = fieldFromInstruction(Insn, 24, 1);
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	5048	bool writeback = (W == 1) \| (P == 0);
				5049
				5050	addr \|= (U << 8) \| (Rn << 9);
				5051
				5052	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				5053	Check(S, MCDisassembler::SoftFail);
				5054
				5055	// Writeback operand
				5056	if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
				5057	return MCDisassembler::Fail;
				5058	// Rt
				5059	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
				5060	return MCDisassembler::Fail;
				5061	// Rt2
				5062	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
				5063	return MCDisassembler::Fail;
				5064	// addr
				5065	if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
				5066	return MCDisassembler::Fail;
				5067
				5068	return S;
				5069	}
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	5070
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	5071	static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	5072	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5073	unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
				5074	unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	5075	if (sign1 != sign2) return MCDisassembler::Fail;
				5076
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5077	unsigned Val = fieldFromInstruction(Insn, 0, 8);
				5078	Val \|= fieldFromInstruction(Insn, 12, 3) << 8;
				5079	Val \|= fieldFromInstruction(Insn, 26, 1) << 11;
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	5080	Val \|= sign1 << 12;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	5081	Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val)));
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	5082
				5083	return MCDisassembler::Success;
				5084	}
				5085
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	5086	static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
Owen Anderson	f01e2de	2011-09-26 21:06:22 +0000	[diff] [blame]	5087	uint64_t Address,
				5088	const void *Decoder) {
				5089	DecodeStatus S = MCDisassembler::Success;
				5090
				5091	// Shift of "asr #32" is not allowed in Thumb2 mode.
Bradley Smith	3131e85	2015-01-19 16:37:17 +0000	[diff] [blame]	5092	if (Val == 0x20) S = MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	5093	Inst.addOperand(MCOperand::createImm(Val));
Owen Anderson	f01e2de	2011-09-26 21:06:22 +0000	[diff] [blame]	5094	return S;
				5095	}
				5096
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	5097	static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Anderson	dde461c	2011-10-28 18:02:13 +0000	[diff] [blame]	5098	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5099	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				5100	unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
				5101	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				5102	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	dde461c	2011-10-28 18:02:13 +0000	[diff] [blame]	5103
				5104	if (pred == 0xF)
				5105	return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
				5106
				5107	DecodeStatus S = MCDisassembler::Success;
Silviu Baranga	ca45af9	2012-04-18 14:18:57 +0000	[diff] [blame]	5108
				5109	if (Rt == Rn \|\| Rn == Rt2)
				5110	S = MCDisassembler::SoftFail;
				5111
Owen Anderson	dde461c	2011-10-28 18:02:13 +0000	[diff] [blame]	5112	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				5113	return MCDisassembler::Fail;
				5114	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
				5115	return MCDisassembler::Fail;
				5116	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				5117	return MCDisassembler::Fail;
				5118	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				5119	return MCDisassembler::Fail;
				5120
				5121	return S;
				5122	}
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5123
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	5124	static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5125	uint64_t Address, const void *Decoder) {
Oliver Stannard	2de8c16	2015-12-16 12:37:39 +0000	[diff] [blame]	5126	const FeatureBitset &featureBits =
				5127	((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
				5128	bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
				5129
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5130	unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
				5131	Vd \|= (fieldFromInstruction(Insn, 22, 1) << 4);
				5132	unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
				5133	Vm \|= (fieldFromInstruction(Insn, 5, 1) << 4);
				5134	unsigned imm = fieldFromInstruction(Insn, 16, 6);
				5135	unsigned cmode = fieldFromInstruction(Insn, 8, 4);
Amaury de la Vieuville	f4ec0c85	2013-06-08 13:54:05 +0000	[diff] [blame]	5136	unsigned op = fieldFromInstruction(Insn, 5, 1);
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5137
				5138	DecodeStatus S = MCDisassembler::Success;
				5139
Oliver Stannard	2de8c16	2015-12-16 12:37:39 +0000	[diff] [blame]	5140	// If the top 3 bits of imm are clear, this is a VMOV (immediate)
				5141	if (!(imm & 0x38)) {
				5142	if (cmode == 0xF) {
				5143	if (op == 1) return MCDisassembler::Fail;
				5144	Inst.setOpcode(ARM::VMOVv2f32);
				5145	}
				5146	if (hasFullFP16) {
				5147	if (cmode == 0xE) {
				5148	if (op == 1) {
				5149	Inst.setOpcode(ARM::VMOVv1i64);
				5150	} else {
				5151	Inst.setOpcode(ARM::VMOVv8i8);
				5152	}
				5153	}
				5154	if (cmode == 0xD) {
				5155	if (op == 1) {
				5156	Inst.setOpcode(ARM::VMVNv2i32);
				5157	} else {
				5158	Inst.setOpcode(ARM::VMOVv2i32);
				5159	}
				5160	}
				5161	if (cmode == 0xC) {
				5162	if (op == 1) {
				5163	Inst.setOpcode(ARM::VMVNv2i32);
				5164	} else {
				5165	Inst.setOpcode(ARM::VMOVv2i32);
				5166	}
				5167	}
				5168	}
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5169	return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
				5170	}
				5171
Amaury de la Vieuville	ea7bb57	2013-06-08 13:29:11 +0000	[diff] [blame]	5172	if (!(imm & 0x20)) return MCDisassembler::Fail;
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5173
				5174	if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
				5175	return MCDisassembler::Fail;
				5176	if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
				5177	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	5178	Inst.addOperand(MCOperand::createImm(64 - imm));
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5179
				5180	return S;
				5181	}
				5182
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	5183	static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5184	uint64_t Address, const void *Decoder) {
Oliver Stannard	2de8c16	2015-12-16 12:37:39 +0000	[diff] [blame]	5185	const FeatureBitset &featureBits =
				5186	((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
				5187	bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
				5188
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5189	unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
				5190	Vd \|= (fieldFromInstruction(Insn, 22, 1) << 4);
				5191	unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
				5192	Vm \|= (fieldFromInstruction(Insn, 5, 1) << 4);
				5193	unsigned imm = fieldFromInstruction(Insn, 16, 6);
				5194	unsigned cmode = fieldFromInstruction(Insn, 8, 4);
Amaury de la Vieuville	f4ec0c85	2013-06-08 13:54:05 +0000	[diff] [blame]	5195	unsigned op = fieldFromInstruction(Insn, 5, 1);
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5196
				5197	DecodeStatus S = MCDisassembler::Success;
				5198
Oliver Stannard	2de8c16	2015-12-16 12:37:39 +0000	[diff] [blame]	5199	// If the top 3 bits of imm are clear, this is a VMOV (immediate)
				5200	if (!(imm & 0x38)) {
				5201	if (cmode == 0xF) {
				5202	if (op == 1) return MCDisassembler::Fail;
				5203	Inst.setOpcode(ARM::VMOVv4f32);
				5204	}
				5205	if (hasFullFP16) {
				5206	if (cmode == 0xE) {
				5207	if (op == 1) {
				5208	Inst.setOpcode(ARM::VMOVv2i64);
				5209	} else {
				5210	Inst.setOpcode(ARM::VMOVv16i8);
				5211	}
				5212	}
				5213	if (cmode == 0xD) {
				5214	if (op == 1) {
				5215	Inst.setOpcode(ARM::VMVNv4i32);
				5216	} else {
				5217	Inst.setOpcode(ARM::VMOVv4i32);
				5218	}
				5219	}
				5220	if (cmode == 0xC) {
				5221	if (op == 1) {
				5222	Inst.setOpcode(ARM::VMVNv4i32);
				5223	} else {
				5224	Inst.setOpcode(ARM::VMOVv4i32);
				5225	}
				5226	}
				5227	}
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5228	return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
				5229	}
				5230
Amaury de la Vieuville	ea7bb57	2013-06-08 13:29:11 +0000	[diff] [blame]	5231	if (!(imm & 0x20)) return MCDisassembler::Fail;
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5232
				5233	if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
				5234	return MCDisassembler::Fail;
				5235	if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
				5236	return MCDisassembler::Fail;
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	5237	Inst.addOperand(MCOperand::createImm(64 - imm));
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	5238
				5239	return S;
				5240	}
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	5241
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	5242	static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	5243	uint64_t Address, const void *Decoder) {
				5244	DecodeStatus S = MCDisassembler::Success;
				5245
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5246	unsigned Rn = fieldFromInstruction(Val, 16, 4);
				5247	unsigned Rt = fieldFromInstruction(Val, 12, 4);
				5248	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				5249	Rm \|= (fieldFromInstruction(Val, 23, 1) << 4);
				5250	unsigned Cond = fieldFromInstruction(Val, 28, 4);
Vinicius Tinti	67cf33d	2015-11-20 23:20:12 +0000	[diff] [blame]	5251
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5252	if (fieldFromInstruction(Val, 8, 4) != 0 \|\| Rn == Rt)
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	5253	S = MCDisassembler::SoftFail;
				5254
				5255	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				5256	return MCDisassembler::Fail;
				5257	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				5258	return MCDisassembler::Fail;
				5259	if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
				5260	return MCDisassembler::Fail;
				5261	if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
				5262	return MCDisassembler::Fail;
				5263	if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
				5264	return MCDisassembler::Fail;
				5265
				5266	return S;
				5267	}
				5268
Ranjeet Singh	39d2d09	2016-06-17 00:52:41 +0000	[diff] [blame]	5269	static DecodeStatus DecoderForMRRC2AndMCRR2(llvm::MCInst &Inst, unsigned Val,
				5270	uint64_t Address, const void *Decoder) {
Silviu Baranga	41f1fcd	2012-04-18 13:12:50 +0000	[diff] [blame]	5271
				5272	DecodeStatus S = MCDisassembler::Success;
				5273
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	5274	unsigned CRm = fieldFromInstruction(Val, 0, 4);
				5275	unsigned opc1 = fieldFromInstruction(Val, 4, 4);
				5276	unsigned cop = fieldFromInstruction(Val, 8, 4);
				5277	unsigned Rt = fieldFromInstruction(Val, 12, 4);
				5278	unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
Silviu Baranga	41f1fcd	2012-04-18 13:12:50 +0000	[diff] [blame]	5279
				5280	if ((cop & ~0x1) == 0xa)
				5281	return MCDisassembler::Fail;
				5282
				5283	if (Rt == Rt2)
				5284	S = MCDisassembler::SoftFail;
				5285
Ranjeet Singh	39d2d09	2016-06-17 00:52:41 +0000	[diff] [blame]	5286	// We have to check if the instruction is MRRC2
				5287	// or MCRR2 when constructing the operands for
				5288	// Inst. Reason is because MRRC2 stores to two
				5289	// registers so it's tablegen desc has has two
				5290	// outputs whereas MCRR doesn't store to any
				5291	// registers so all of it's operands are listed
				5292	// as inputs, therefore the operand order for
				5293	// MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm]
				5294	// and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm]
				5295
				5296	if (Inst.getOpcode() == ARM::MRRC2) {
				5297	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				5298	return MCDisassembler::Fail;
				5299	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
				5300	return MCDisassembler::Fail;
				5301	}
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	5302	Inst.addOperand(MCOperand::createImm(cop));
				5303	Inst.addOperand(MCOperand::createImm(opc1));
Ranjeet Singh	39d2d09	2016-06-17 00:52:41 +0000	[diff] [blame]	5304	if (Inst.getOpcode() == ARM::MCRR2) {
				5305	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				5306	return MCDisassembler::Fail;
				5307	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
				5308	return MCDisassembler::Fail;
				5309	}
Jim Grosbach	e9119e4	2015-05-13 18:37:00 +0000	[diff] [blame]	5310	Inst.addOperand(MCOperand::createImm(CRm));
Silviu Baranga	41f1fcd	2012-04-18 13:12:50 +0000	[diff] [blame]	5311
				5312	return S;
				5313	}