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gerrit-public.fairphone.software / toolchain / llvm-project / f8b51c5f90c60aceedef9ed185eeac58f501075a / . / llvm / test / CodeGen / PowerPC / testCompareslllesi.ll
blob: 42062692a080d00d5dee59f6922458d7a896a23c [file] [log] [blame]
Nemanja Ivanovicd6f93f52017-09-22 11:50:25 +0000[diff] [blame]1; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
Nemanja Ivanovicdb7e7702017-11-30 13:39:10 +0000[diff] [blame]2; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
Nemanja Ivanovicd6f93f52017-09-22 11:50:25 +0000[diff] [blame]3; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
4; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
Nemanja Ivanovicdb7e7702017-11-30 13:39:10 +0000[diff] [blame]5; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
Nemanja Ivanovicd6f93f52017-09-22 11:50:25 +0000[diff] [blame]6; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
7; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
8
9@glob = common local_unnamed_addr global i32 0, align 4
10
11define i64 @test_lllesi(i32 signext %a, i32 signext %b) {
12; CHECK-LABEL: test_lllesi:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]13; CHECK: # %bb.0: # %entry
Nemanja Ivanovicd6f93f52017-09-22 11:50:25 +0000[diff] [blame]14; CHECK-NEXT: sub r3, r4, r3
15; CHECK-NEXT: rldicl r3, r3, 1, 63
16; CHECK-NEXT: xori r3, r3, 1
17; CHECK-NEXT: blr
18entry:
19 %cmp = icmp sle i32 %a, %b
20 %conv1 = zext i1 %cmp to i64
21 ret i64 %conv1
22}
23
24define i64 @test_lllesi_sext(i32 signext %a, i32 signext %b) {
25; CHECK-LABEL: test_lllesi_sext:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]26; CHECK: # %bb.0: # %entry
Nemanja Ivanovicd6f93f52017-09-22 11:50:25 +0000[diff] [blame]27; CHECK-NEXT: sub r3, r4, r3
28; CHECK-NEXT: rldicl r3, r3, 1, 63
29; CHECK-NEXT: addi r3, r3, -1
30; CHECK-NEXT: blr
31entry:
32 %cmp = icmp sle i32 %a, %b
33 %conv1 = sext i1 %cmp to i64
34 ret i64 %conv1
35}
36
37define void @test_lllesi_store(i32 signext %a, i32 signext %b) {
38; CHECK-LABEL: test_lllesi_store:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]39; CHECK: # %bb.0: # %entry
Nemanja Ivanovicd6f93f52017-09-22 11:50:25 +0000[diff] [blame]40; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
41; CHECK-NEXT: sub r3, r4, r3
42; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
43; CHECK-NEXT: rldicl r3, r3, 1, 63
44; CHECK-NEXT: xori r3, r3, 1
45; CHECK-NEXT: stw r3, 0(r12)
46; CHECK-NEXT: blr
47entry:
48 %cmp = icmp sle i32 %a, %b
49 %conv = zext i1 %cmp to i32
50 store i32 %conv, i32* @glob, align 4
51 ret void
52}
53
54define void @test_lllesi_sext_store(i32 signext %a, i32 signext %b) {
55; CHECK-LABEL: test_lllesi_sext_store:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]56; CHECK: # %bb.0: # %entry
Nemanja Ivanovicd6f93f52017-09-22 11:50:25 +0000[diff] [blame]57; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
58; CHECK-NEXT: sub r3, r4, r3
59; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
60; CHECK-NEXT: rldicl r3, r3, 1, 63
61; CHECK-NEXT: addi r3, r3, -1
62; CHECK-NEXT: stw r3, 0(r12)
63; CHECK-NEXT: blr
64entry:
65 %cmp = icmp sle i32 %a, %b
66 %sub = sext i1 %cmp to i32
67 store i32 %sub, i32* @glob, align 4
68 ret void
69}