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gerrit-public.fairphone.software / toolchain / llvm-project / f901b719214d0bd4d42d85e9b5bbbc95d1ee3479 / . / llvm / lib / Target / PowerPC / PPCScheduleE5500.td
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Hal Finkel742b5352012-08-28 16:12:39 +0000[diff] [blame]1//===-- PPCScheduleE500mc.td - e5500 Scheduling Defs -------*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the itinerary class data for the Freescale e5500 64-bit
11// Power processor.
12//
13// All information is derived from the "e5500 Core Reference Manual",
14// Freescale Document Number e5500RM, Rev. 1, 03/2012.
15//
16//===----------------------------------------------------------------------===//
17// Relevant functional units in the Freescale e5500 core
18// (These are the same as for the e500mc)
19//
20// * Decode & Dispatch
21// Can dispatch up to 2 instructions per clock cycle to either the GPR Issue
22// queues (GIQx), FP Issue Queue (FIQ), or Branch issue queue (BIQ).
23// def DIS0 : FuncUnit;
24// def DIS1 : FuncUnit;
25
26// * Execute
27// 6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX.
28// The CFX has a bypass path, allowing non-divide instructions to execute
29// while a divide instruction is being executed.
30// def SFX0 : FuncUnit; // Simple unit 0
31// def SFX1 : FuncUnit; // Simple unit 1
32// def BU : FuncUnit; // Branch unit
33// def CFX_DivBypass
34// : FuncUnit; // CFX divide bypass path
35// def CFX_0 : FuncUnit; // CFX pipeline stage 0
36
37def CFX_1 : FuncUnit; // CFX pipeline stage 1
38
39// def LSU_0 : FuncUnit; // LSU pipeline
40// def FPU_0 : FuncUnit; // FPU pipeline
41
42
43def PPCE5500Itineraries : ProcessorItineraries<
44 [DIS0, DIS1, SFX0, SFX1, BU, CFX_DivBypass, CFX_0, CFX_1,
45 LSU_0, FPU_0],
46 [CR_Bypass, GPR_Bypass, FPR_Bypass], [
47 InstrItinData<IntSimple , [InstrStage<1, [DIS0, DIS1], 0>,
48 InstrStage<1, [SFX0, SFX1]>],
49 [5, 2, 2], // Latency = 1
50 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
51 InstrItinData<IntGeneral , [InstrStage<1, [DIS0, DIS1], 0>,
52 InstrStage<1, [SFX0, SFX1]>],
53 [5, 2, 2], // Latency = 1
54 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
55 InstrItinData<IntCompare , [InstrStage<1, [DIS0, DIS1], 0>,
56 InstrStage<1, [SFX0, SFX1]>],
57 [6, 2, 2], // Latency = 1 or 2
58 [CR_Bypass, GPR_Bypass, GPR_Bypass]>,
59 InstrItinData<IntDivD , [InstrStage<1, [DIS0, DIS1], 0>,
60 InstrStage<1, [CFX_0], 0>,
61 InstrStage<26, [CFX_DivBypass]>],
62 [30, 2, 2], // Latency= 4..26, Repeat rate= 4..26
63 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
64 InstrItinData<IntDivW , [InstrStage<1, [DIS0, DIS1], 0>,
65 InstrStage<1, [CFX_0], 0>,
66 InstrStage<16, [CFX_DivBypass]>],
67 [20, 2, 2], // Latency= 4..16, Repeat rate= 4..16
68 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
69 InstrItinData<IntMFFS , [InstrStage<1, [DIS0, DIS1], 0>,
70 InstrStage<1, [FPU_0]>],
71 [11], // Latency = 7, Repeat rate = 1
72 [FPR_Bypass]>,
73 InstrItinData<IntMTFSB0 , [InstrStage<1, [DIS0, DIS1], 0>,
74 InstrStage<7, [FPU_0]>],
75 [11, 2, 2], // Latency = 7, Repeat rate = 7
76 [NoBypass, NoBypass, NoBypass]>,
77 InstrItinData<IntMulHD , [InstrStage<1, [DIS0, DIS1], 0>,
78 InstrStage<1, [CFX_0], 0>,
79 InstrStage<2, [CFX_1]>],
80 [9, 2, 2], // Latency = 4..7, Repeat rate = 2..4
81 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
82 InstrItinData<IntMulHW , [InstrStage<1, [DIS0, DIS1], 0>,
83 InstrStage<1, [CFX_0], 0>,
84 InstrStage<1, [CFX_1]>],
85 [8, 2, 2], // Latency = 4, Repeat rate = 1
86 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
87 InstrItinData<IntMulHWU , [InstrStage<1, [DIS0, DIS1], 0>,
88 InstrStage<1, [CFX_0], 0>,
89 InstrStage<1, [CFX_1]>],
90 [8, 2, 2], // Latency = 4, Repeat rate = 1
91 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
92 InstrItinData<IntMulLI , [InstrStage<1, [DIS0, DIS1], 0>,
93 InstrStage<1, [CFX_0], 0>,
94 InstrStage<2, [CFX_1]>],
95 [8, 2, 2], // Latency = 4 or 5, Repeat = 2
96 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
97 InstrItinData<IntRotate , [InstrStage<1, [DIS0, DIS1], 0>,
98 InstrStage<1, [SFX0, SFX1]>],
99 [5, 2, 2], // Latency = 1
100 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
101 InstrItinData<IntRotateD , [InstrStage<1, [DIS0, DIS1], 0>,
102 InstrStage<2, [SFX0, SFX1]>],
103 [6, 2, 2], // Latency = 2, Repeat rate = 2
104 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
105 InstrItinData<IntRotateDI , [InstrStage<1, [DIS0, DIS1], 0>,
106 InstrStage<1, [SFX0, SFX1]>],
107 [5, 2, 2], // Latency = 1, Repeat rate = 1
108 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
109 InstrItinData<IntShift , [InstrStage<1, [DIS0, DIS1], 0>,
110 InstrStage<2, [SFX0, SFX1]>],
111 [6, 2, 2], // Latency = 2, Repeat rate = 2
112 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
113 InstrItinData<IntTrapW , [InstrStage<1, [DIS0, DIS1], 0>,
114 InstrStage<2, [SFX0]>],
115 [6, 2], // Latency = 2, Repeat rate = 2
116 [GPR_Bypass, GPR_Bypass]>,
117 InstrItinData<BrB , [InstrStage<1, [DIS0, DIS1], 0>,
118 InstrStage<1, [BU]>],
119 [5, 2], // Latency = 1
120 [NoBypass, GPR_Bypass]>,
121 InstrItinData<BrCR , [InstrStage<1, [DIS0, DIS1], 0>,
122 InstrStage<1, [BU]>],
123 [5, 2, 2], // Latency = 1
124 [CR_Bypass, CR_Bypass, CR_Bypass]>,
125 InstrItinData<BrMCR , [InstrStage<1, [DIS0, DIS1], 0>,
126 InstrStage<1, [BU]>],
127 [5, 2], // Latency = 1
128 [CR_Bypass, CR_Bypass]>,
129 InstrItinData<BrMCRX , [InstrStage<1, [DIS0, DIS1], 0>,
130 InstrStage<1, [CFX_0]>],
131 [5, 2, 2], // Latency = 1
132 [CR_Bypass, GPR_Bypass]>,
133 InstrItinData<LdStDCBA , [InstrStage<1, [DIS0, DIS1], 0>,
134 InstrStage<1, [LSU_0]>],
135 [7, 2], // Latency = 3, Repeat rate = 1
136 [GPR_Bypass, GPR_Bypass]>,
137 InstrItinData<LdStDCBF , [InstrStage<1, [DIS0, DIS1], 0>,
138 InstrStage<1, [LSU_0]>],
139 [7, 2], // Latency = 3, Repeat rate = 1
140 [GPR_Bypass, GPR_Bypass]>,
141 InstrItinData<LdStDCBI , [InstrStage<1, [DIS0, DIS1], 0>,
142 InstrStage<1, [LSU_0]>],
143 [7, 2], // Latency = 3, Repeat rate = 1
144 [GPR_Bypass, GPR_Bypass]>,
145 InstrItinData<LdStLoad , [InstrStage<1, [DIS0, DIS1], 0>,
146 InstrStage<1, [LSU_0]>],
147 [7, 2], // Latency = 3
148 [GPR_Bypass, GPR_Bypass]>,
149 InstrItinData<LdStLoadUpd , [InstrStage<1, [DIS0, DIS1], 0>,
150 InstrStage<1, [SFX0, SFX1], 0>,
151 InstrStage<1, [LSU_0]>],
152 [7, 2], // Latency = 3, Repeat rate = 1
153 [GPR_Bypass, GPR_Bypass],
154 2>, // 2 micro-ops
155 InstrItinData<LdStLD , [InstrStage<1, [DIS0, DIS1], 0>,
156 InstrStage<1, [LSU_0]>],
157 [7, 2], // Latency = 3, Repeat rate = 1
158 [GPR_Bypass, GPR_Bypass]>,
159 InstrItinData<LdStLDARX , [InstrStage<1, [DIS0, DIS1], 0>,
160 InstrStage<3, [LSU_0]>],
161 [7, 2], // Latency = 3, Repeat rate = 3
162 [GPR_Bypass, GPR_Bypass]>,
163 InstrItinData<LdStLDU , [InstrStage<1, [DIS0, DIS1], 0>,
164 InstrStage<1, [SFX0, SFX1], 0>,
165 InstrStage<1, [LSU_0]>],
166 [7, 2], // Latency = 3, Repeat rate = 1
167 [GPR_Bypass, GPR_Bypass],
168 2>, // 2 micro-ops
169 InstrItinData<LdStStore , [InstrStage<1, [DIS0, DIS1], 0>,
170 InstrStage<1, [LSU_0]>],
171 [7, 2], // Latency = 3, Repeat rate = 1
172 [NoBypass, GPR_Bypass]>,
173 InstrItinData<LdStStoreUpd, [InstrStage<1, [DIS0, DIS1], 0>,
174 InstrStage<1, [SFX0, SFX1], 0>,
175 InstrStage<1, [LSU_0]>],
176 [7, 2], // Latency = 3, Repeat rate = 1
177 [NoBypass, GPR_Bypass],
178 2>, // 2 micro-ops
179 InstrItinData<LdStICBI , [InstrStage<1, [DIS0, DIS1], 0>,
180 InstrStage<1, [LSU_0]>],
181 [7, 2], // Latency = 3, Repeat rate = 1
182 [NoBypass, GPR_Bypass]>,
183 InstrItinData<LdStSTFD , [InstrStage<1, [DIS0, DIS1], 0>,
184 InstrStage<1, [LSU_0]>],
185 [7, 2, 2], // Latency = 3, Repeat rate = 1
186 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
187 InstrItinData<LdStSTFDU , [InstrStage<1, [DIS0, DIS1], 0>,
188 InstrStage<1, [SFX0, SFX1], 0>,
189 InstrStage<1, [LSU_0]>],
190 [7, 2, 2], // Latency = 3, Repeat rate = 1
191 [GPR_Bypass, GPR_Bypass, GPR_Bypass],
192 2>, // 2 micro-ops
193 InstrItinData<LdStLFD , [InstrStage<1, [DIS0, DIS1], 0>,
194 InstrStage<1, [LSU_0]>],
195 [8, 2, 2], // Latency = 4, Repeat rate = 1
196 [FPR_Bypass, GPR_Bypass, GPR_Bypass],
197 2>, // 2 micro-ops
198 InstrItinData<LdStLFDU , [InstrStage<1, [DIS0, DIS1], 0>,
199 InstrStage<1, [SFX0, SFX1], 0>,
200 InstrStage<1, [LSU_0]>],
201 [8, 2, 2], // Latency = 4, Repeat rate = 1
202 [FPR_Bypass, GPR_Bypass, GPR_Bypass],
203 2>, // 2 micro-ops
204 InstrItinData<LdStLHA , [InstrStage<1, [DIS0, DIS1], 0>,
205 InstrStage<1, [LSU_0]>],
206 [7, 2], // Latency = 3
207 [GPR_Bypass, GPR_Bypass]>,
208 InstrItinData<LdStLHAU , [InstrStage<1, [DIS0, DIS1], 0>,
209 InstrStage<1, [SFX0, SFX1], 0>,
210 InstrStage<1, [LSU_0]>],
211 [7, 2], // Latency = 3, Repeat rate = 1
212 [GPR_Bypass, GPR_Bypass],
213 2>, // 2 micro-ops
214 InstrItinData<LdStLMW , [InstrStage<1, [DIS0, DIS1], 0>,
215 InstrStage<4, [LSU_0]>],
216 [8, 2], // Latency = r+3, Repeat rate = r+3
217 [NoBypass, GPR_Bypass]>,
218 InstrItinData<LdStLWARX , [InstrStage<1, [DIS0, DIS1], 0>,
219 InstrStage<3, [LSU_0]>],
220 [7, 2, 2], // Latency = 3, Repeat rate = 3
221 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
222 InstrItinData<LdStSTD , [InstrStage<1, [DIS0, DIS1], 0>,
223 InstrStage<1, [LSU_0]>],
224 [7, 2], // Latency = 3, Repeat rate = 1
225 [NoBypass, GPR_Bypass]>,
226 InstrItinData<LdStSTDCX , [InstrStage<1, [DIS0, DIS1], 0>,
227 InstrStage<1, [LSU_0]>],
228 [7, 2], // Latency = 3, Repeat rate = 1
229 [NoBypass, GPR_Bypass]>,
230 InstrItinData<LdStSTDU , [InstrStage<1, [DIS0, DIS1], 0>,
231 InstrStage<1, [SFX0, SFX1], 0>,
232 InstrStage<1, [LSU_0]>],
233 [7, 2], // Latency = 3, Repeat rate = 1
234 [NoBypass, GPR_Bypass],
235 2>, // 2 micro-ops
236 InstrItinData<LdStSTWCX , [InstrStage<1, [DIS0, DIS1], 0>,
237 InstrStage<1, [LSU_0]>],
238 [7, 2], // Latency = 3, Repeat rate = 1
239 [NoBypass, GPR_Bypass]>,
240 InstrItinData<LdStSync , [InstrStage<1, [DIS0, DIS1], 0>,
241 InstrStage<1, [LSU_0]>]>,
242 InstrItinData<SprMTMSR , [InstrStage<1, [DIS0, DIS1], 0>,
243 InstrStage<2, [CFX_0]>],
244 [6, 2], // Latency = 2, Repeat rate = 4
245 [GPR_Bypass, GPR_Bypass]>,
246 InstrItinData<SprTLBSYNC , [InstrStage<1, [DIS0, DIS1], 0>,
247 InstrStage<1, [LSU_0], 0>]>,
248 InstrItinData<SprMFCR , [InstrStage<1, [DIS0, DIS1], 0>,
249 InstrStage<5, [CFX_0]>],
250 [9, 2], // Latency = 5, Repeat rate = 5
251 [GPR_Bypass, CR_Bypass]>,
252 InstrItinData<SprMFMSR , [InstrStage<1, [DIS0, DIS1], 0>,
253 InstrStage<4, [SFX0]>],
254 [8, 2], // Latency = 4, Repeat rate = 4
255 [GPR_Bypass, GPR_Bypass]>,
256 InstrItinData<SprMFSPR , [InstrStage<1, [DIS0, DIS1], 0>,
257 InstrStage<1, [CFX_0]>],
258 [5], // Latency = 1, Repeat rate = 1
259 [GPR_Bypass]>,
260 InstrItinData<SprMFTB , [InstrStage<1, [DIS0, DIS1], 0>,
261 InstrStage<4, [CFX_0]>],
262 [8, 2], // Latency = 4, Repeat rate = 4
263 [NoBypass, GPR_Bypass]>,
264 InstrItinData<SprMTSPR , [InstrStage<1, [DIS0, DIS1], 0>,
265 InstrStage<1, [SFX0, SFX1]>],
266 [5], // Latency = 1, Repeat rate = 1
267 [GPR_Bypass]>,
268 InstrItinData<FPGeneral , [InstrStage<1, [DIS0, DIS1], 0>,
269 InstrStage<1, [FPU_0]>],
270 [11, 2, 2], // Latency = 7, Repeat rate = 1
271 [FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
272 InstrItinData<FPAddSub , [InstrStage<1, [DIS0, DIS1], 0>,
273 InstrStage<1, [FPU_0]>],
274 [11, 2, 2], // Latency = 7, Repeat rate = 1
275 [FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
276 InstrItinData<FPCompare , [InstrStage<1, [DIS0, DIS1], 0>,
277 InstrStage<1, [FPU_0]>],
278 [11, 2, 2], // Latency = 7, Repeat rate = 1
279 [CR_Bypass, FPR_Bypass, FPR_Bypass]>,
280 InstrItinData<FPDivD , [InstrStage<1, [DIS0, DIS1], 0>,
281 InstrStage<31, [FPU_0]>],
282 [39, 2, 2], // Latency = 35, Repeat rate = 31
283 [FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
284 InstrItinData<FPDivS , [InstrStage<1, [DIS0, DIS1], 0>,
285 InstrStage<16, [FPU_0]>],
286 [24, 2, 2], // Latency = 20, Repeat rate = 16
287 [FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
288 InstrItinData<FPFused , [InstrStage<1, [DIS0, DIS1], 0>,
289 InstrStage<1, [FPU_0]>],
290 [11, 2, 2, 2], // Latency = 7, Repeat rate = 1
291 [FPR_Bypass, FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
292 InstrItinData<FPRes , [InstrStage<1, [DIS0, DIS1], 0>,
293 InstrStage<2, [FPU_0]>],
294 [12, 2], // Latency = 8, Repeat rate = 2
295 [FPR_Bypass, FPR_Bypass]>
296]>;
297
298// ===---------------------------------------------------------------------===//
299// e5500 machine model for scheduling and other instruction cost heuristics.
300
301def PPCE5500Model : SchedMachineModel {
302 let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
303 let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
304 let LoadLatency = 6; // Optimistic load latency assuming bypass.
305 // This is overriden by OperandCycles if the
306 // Itineraries are queried instead.
307
308 let Itineraries = PPCE5500Itineraries;
309}