| Ehsan Amiri | a538b0f | 2016-08-03 18:17:35 +0000 | [diff] [blame] | 1 | ; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s |
| Hal Finkel | fbf7e2a | 2014-04-04 15:15:57 +0000 | [diff] [blame] | 2 | target datalayout = "E-m:e-i64:64-n32:64" |
| 3 | target triple = "powerpc64-unknown-linux-gnu" |
| 4 | |
| 5 | define i64 @test1(i64 %a, i64 %b) { |
| 6 | entry: |
| 7 | %c = icmp eq i64 %a, %b |
| 8 | br label %foo |
| 9 | |
| 10 | foo: |
| 11 | call { i64, i64 } asm sideeffect "sc", "={r0},={r3},{r0},~{cr0},~{cr1},~{cr2},~{cr3},~{cr4},~{cr5},~{cr6},~{cr7}" (i64 %a) |
| 12 | br i1 %c, label %bar, label %end |
| 13 | |
| 14 | bar: |
| 15 | ret i64 %b |
| 16 | |
| 17 | end: |
| 18 | ret i64 %a |
| 19 | |
| 20 | ; CHECK-LABEL: @test1 |
| 21 | ; CHECK: mfcr [[REG1:[0-9]+]] |
| 22 | ; CHECK-DAG: cmpd |
| 23 | ; CHECK-DAG: mfocrf [[REG2:[0-9]+]], |
| 24 | ; CHECK-DAG: stw [[REG1]], 8(1) |
| 25 | ; CHECK-DAG: stw [[REG2]], -4(1) |
| 26 | |
| 27 | ; CHECK: sc |
| 28 | ; CHECK: lwz [[REG3:[0-9]+]], -4(1) |
| 29 | ; CHECK: mtocrf 128, [[REG3]] |
| 30 | |
| 31 | ; CHECK: lwz [[REG4:[0-9]+]], 8(1) |
| 32 | ; CHECK-DAG: mtocrf 32, [[REG4]] |
| 33 | ; CHECK-DAG: mtocrf 16, [[REG4]] |
| 34 | ; CHECK-DAG: mtocrf 8, [[REG4]] |
| 35 | ; CHECK: blr |
| 36 | } |
| 37 | |
| 38 | define i64 @test2(i64 %a, i64 %b) { |
| 39 | entry: |
| 40 | %c = icmp eq i64 %a, %b |
| 41 | br label %foo |
| 42 | |
| 43 | foo: |
| Hal Finkel | 029042b | 2014-12-04 00:46:20 +0000 | [diff] [blame] | 44 | call { i64, i64 } asm sideeffect "sc", "={r0},={r3},{r0},~{cc},~{cr1},~{cr2},~{cr3},~{cr4},~{cr5},~{cr6},~{cr7}" (i64 %a) |
| Hal Finkel | fbf7e2a | 2014-04-04 15:15:57 +0000 | [diff] [blame] | 45 | br i1 %c, label %bar, label %end |
| 46 | |
| 47 | bar: |
| 48 | ret i64 %b |
| 49 | |
| 50 | end: |
| 51 | ret i64 %a |
| 52 | |
| 53 | ; CHECK-LABEL: @test2 |
| 54 | ; CHECK: mfcr [[REG1:[0-9]+]] |
| 55 | ; CHECK-DAG: cmpd |
| 56 | ; CHECK-DAG: mfocrf [[REG2:[0-9]+]], |
| 57 | ; CHECK-DAG: stw [[REG1]], 8(1) |
| 58 | ; CHECK-DAG: stw [[REG2]], -4(1) |
| 59 | |
| 60 | ; CHECK: sc |
| 61 | ; CHECK: lwz [[REG3:[0-9]+]], -4(1) |
| 62 | ; CHECK: mtocrf 128, [[REG3]] |
| 63 | |
| 64 | ; CHECK: lwz [[REG4:[0-9]+]], 8(1) |
| 65 | ; CHECK-DAG: mtocrf 32, [[REG4]] |
| 66 | ; CHECK-DAG: mtocrf 16, [[REG4]] |
| 67 | ; CHECK-DAG: mtocrf 8, [[REG4]] |
| 68 | ; CHECK: blr |
| 69 | } |
| 70 | |