Blame - llvm/lib/Target/Sparc/Sparc.td - toolchain/llvm-project

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Jia Liu	b22310f	2012-02-18 12:03:15 +0000	[diff] [blame]	1	//===-- Sparc.td - Describe the Sparc Target Machine -------- tablegen --===//
				2	//
Chris Lattner	158e1f5	2006-02-05 05:50:24 +0000	[diff] [blame]	3	// The LLVM Compiler Infrastructure
				4	//
Chris Lattner	f3ebc3f	2007-12-29 20:36:04 +0000	[diff] [blame]	5	// This file is distributed under the University of Illinois Open Source
				6	// License. See LICENSE.TXT for details.
Jia Liu	b22310f	2012-02-18 12:03:15 +0000	[diff] [blame]	7	//
Chris Lattner	158e1f5	2006-02-05 05:50:24 +0000	[diff] [blame]	8	//===----------------------------------------------------------------------===//
				9	//
				10	//
				11	//===----------------------------------------------------------------------===//
				12
				13	//===----------------------------------------------------------------------===//
				14	// Target-independent interfaces which we are implementing
				15	//===----------------------------------------------------------------------===//
				16
Evan Cheng	977e7be	2008-11-24 07:34:46 +0000	[diff] [blame]	17	include "llvm/Target/Target.td"
Chris Lattner	158e1f5	2006-02-05 05:50:24 +0000	[diff] [blame]	18
				19	//===----------------------------------------------------------------------===//
				20	// SPARC Subtarget features.
				21	//
Venkatraman Govindaraju	a54533ed	2013-06-04 18:33:25 +0000	[diff] [blame]	22
Chris Lattner	158e1f5	2006-02-05 05:50:24 +0000	[diff] [blame]	23	def FeatureV9
				24	: SubtargetFeature<"v9", "IsV9", "true",
				25	"Enable SPARC-V9 instructions">;
				26	def FeatureV8Deprecated
				27	: SubtargetFeature<"deprecated-v8", "V8DeprecatedInsts", "true",
				28	"Enable deprecated V8 instructions in V9 mode">;
				29	def FeatureVIS
				30	: SubtargetFeature<"vis", "IsVIS", "true",
				31	"Enable UltraSPARC Visual Instruction Set extensions">;
Venkatraman Govindaraju	f9a202a	2014-03-02 19:31:21 +0000	[diff] [blame^]	32	def FeatureVIS2
				33	: SubtargetFeature<"vis2", "IsVIS2", "true",
				34	"Enable Visual Instruction Set extensions II">;
				35	def FeatureVIS3
				36	: SubtargetFeature<"vis3", "IsVIS3", "true",
				37	"Enable Visual Instruction Set extensions III">;
Chris Lattner	158e1f5	2006-02-05 05:50:24 +0000	[diff] [blame]	38
Venkatraman Govindaraju	35e0c38	2013-08-25 18:30:06 +0000	[diff] [blame]	39	def FeatureHardQuad
				40	: SubtargetFeature<"hard-quad-float", "HasHardQuad", "true",
				41	"Enable quad-word floating point instructions">;
				42
Jakob Stoklund Olesen	ead3b3d	2014-01-26 06:09:59 +0000	[diff] [blame]	43	def UsePopc : SubtargetFeature<"popc", "UsePopc", "true",
				44	"Use the popc (population count) instruction">;
				45
Chris Lattner	158e1f5	2006-02-05 05:50:24 +0000	[diff] [blame]	46	//===----------------------------------------------------------------------===//
Chris Lattner	49b269d	2008-03-17 05:41:48 +0000	[diff] [blame]	47	// Register File, Calling Conv, Instruction Descriptions
Chris Lattner	158e1f5	2006-02-05 05:50:24 +0000	[diff] [blame]	48	//===----------------------------------------------------------------------===//
				49
				50	include "SparcRegisterInfo.td"
Chris Lattner	49b269d	2008-03-17 05:41:48 +0000	[diff] [blame]	51	include "SparcCallingConv.td"
Chris Lattner	158e1f5	2006-02-05 05:50:24 +0000	[diff] [blame]	52	include "SparcInstrInfo.td"
				53
Jakob Stoklund Olesen	b93331f	2010-04-05 03:10:20 +0000	[diff] [blame]	54	def SparcInstrInfo : InstrInfo;
Chris Lattner	158e1f5	2006-02-05 05:50:24 +0000	[diff] [blame]	55
Venkatraman Govindaraju	c2dee7d	2014-01-04 11:30:13 +0000	[diff] [blame]	56	def SparcAsmParser : AsmParser {
				57	bit ShouldEmitMatchRegisterName = 0;
				58	}
				59
Chris Lattner	158e1f5	2006-02-05 05:50:24 +0000	[diff] [blame]	60	//===----------------------------------------------------------------------===//
				61	// SPARC processors supported.
				62	//===----------------------------------------------------------------------===//
				63
				64	class Proc<string Name, list<SubtargetFeature> Features>
				65	: Processor<Name, NoItineraries, Features>;
				66
				67	def : Proc<"generic", []>;
Venkatraman Govindaraju	a66b314	2014-01-11 23:56:13 +0000	[diff] [blame]	68	def : Proc<"v7", []>;
Chris Lattner	158e1f5	2006-02-05 05:50:24 +0000	[diff] [blame]	69	def : Proc<"v8", []>;
				70	def : Proc<"supersparc", []>;
				71	def : Proc<"sparclite", []>;
				72	def : Proc<"f934", []>;
				73	def : Proc<"hypersparc", []>;
				74	def : Proc<"sparclite86x", []>;
				75	def : Proc<"sparclet", []>;
				76	def : Proc<"tsc701", []>;
				77	def : Proc<"v9", [FeatureV9]>;
Venkatraman Govindaraju	f9a202a	2014-03-02 19:31:21 +0000	[diff] [blame^]	78	def : Proc<"ultrasparc", [FeatureV9, FeatureV8Deprecated, FeatureVIS]>;
				79	def : Proc<"ultrasparc3", [FeatureV9, FeatureV8Deprecated, FeatureVIS,
				80	FeatureVIS2]>;
				81	def : Proc<"niagara", [FeatureV9, FeatureV8Deprecated, FeatureVIS,
				82	FeatureVIS2]>;
				83	def : Proc<"niagara2", [FeatureV9, FeatureV8Deprecated, UsePopc,
				84	FeatureVIS, FeatureVIS2]>;
				85	def : Proc<"niagara3", [FeatureV9, FeatureV8Deprecated, UsePopc,
				86	FeatureVIS, FeatureVIS2]>;
				87	def : Proc<"niagara4", [FeatureV9, FeatureV8Deprecated, UsePopc,
				88	FeatureVIS, FeatureVIS2, FeatureVIS3]>;
Chris Lattner	158e1f5	2006-02-05 05:50:24 +0000	[diff] [blame]	89
				90
				91	//===----------------------------------------------------------------------===//
				92	// Declare the target which we are implementing
				93	//===----------------------------------------------------------------------===//
				94
				95	def Sparc : Target {
Chris Lattner	158e1f5	2006-02-05 05:50:24 +0000	[diff] [blame]	96	// Pull in Instruction Info:
				97	let InstructionSet = SparcInstrInfo;
Venkatraman Govindaraju	c2dee7d	2014-01-04 11:30:13 +0000	[diff] [blame]	98	let AssemblyParsers = [SparcAsmParser];
Chris Lattner	158e1f5	2006-02-05 05:50:24 +0000	[diff] [blame]	99	}