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Jia Liub22310f2012-02-18 12:03:15 +00001//===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===//
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +00002//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
Anton Korobeynikov2f931282011-01-10 12:39:04 +000010// This file contains the PPC implementation of TargetFrameLowering class.
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +000011//
12//===----------------------------------------------------------------------===//
13
Anton Korobeynikov2f931282011-01-10 12:39:04 +000014#include "PPCFrameLowering.h"
Roman Divackyc9e23d92012-09-12 14:47:47 +000015#include "PPCInstrBuilder.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000016#include "PPCInstrInfo.h"
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +000017#include "PPCMachineFunctionInfo.h"
Eric Christopherd104c312014-06-12 20:54:11 +000018#include "PPCSubtarget.h"
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +000019#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineFunction.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/CodeGen/MachineModuleInfo.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +000024#include "llvm/CodeGen/RegisterScavenging.h"
Chandler Carruth9fb823b2013-01-02 11:36:10 +000025#include "llvm/IR/Function.h"
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +000026#include "llvm/Target/TargetOptions.h"
27
28using namespace llvm;
29
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +000030/// VRRegNo - Map from a numbered VR register to its enum value.
31///
Craig Topperca658c22012-03-11 07:16:55 +000032static const uint16_t VRRegNo[] = {
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +000033 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
34 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
35 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
36 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
37};
38
Eric Christopherf71609b2015-02-13 00:39:27 +000039static unsigned computeReturnSaveOffset(const PPCSubtarget &STI) {
40 if (STI.isDarwinABI())
41 return STI.isPPC64() ? 16 : 8;
42 // SVR4 ABI:
43 return STI.isPPC64() ? 16 : 4;
44}
45
Eric Christopher736d39e2015-02-13 00:39:36 +000046static unsigned computeTOCSaveOffset(const PPCSubtarget &STI) {
47 return STI.isELFv2ABI() ? 24 : 40;
48}
49
Eric Christopherdc3a8a42015-02-13 00:39:38 +000050static unsigned computeFramePointerSaveOffset(const PPCSubtarget &STI) {
51 // For the Darwin ABI:
52 // We cannot use the TOC save slot (offset +20) in the PowerPC linkage area
53 // for saving the frame pointer (if needed.) While the published ABI has
54 // not used this slot since at least MacOSX 10.2, there is older code
55 // around that does use it, and that needs to continue to work.
56 if (STI.isDarwinABI())
57 return STI.isPPC64() ? -8U : -4U;
58
59 // SVR4 ABI: First slot in the general register save area.
60 return STI.isPPC64() ? -8U : -4U;
61}
62
Eric Christophera4ae2132015-02-13 22:22:57 +000063static unsigned computeLinkageSize(const PPCSubtarget &STI) {
64 if (STI.isDarwinABI() || STI.isPPC64())
65 return (STI.isELFv2ABI() ? 4 : 6) * (STI.isPPC64() ? 8 : 4);
66
67 // SVR4 ABI:
68 return 8;
69}
70
Eric Christopherd104c312014-06-12 20:54:11 +000071PPCFrameLowering::PPCFrameLowering(const PPCSubtarget &STI)
72 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
73 (STI.hasQPX() || STI.isBGQ()) ? 32 : 16, 0),
Eric Christopher736d39e2015-02-13 00:39:36 +000074 Subtarget(STI), ReturnSaveOffset(computeReturnSaveOffset(Subtarget)),
Eric Christopherdc3a8a42015-02-13 00:39:38 +000075 TOCSaveOffset(computeTOCSaveOffset(Subtarget)),
Eric Christophera4ae2132015-02-13 22:22:57 +000076 FramePointerSaveOffset(computeFramePointerSaveOffset(Subtarget)),
77 LinkageSize(computeLinkageSize(Subtarget)) {}
Eric Christopherd104c312014-06-12 20:54:11 +000078
Eric Christopherd104c312014-06-12 20:54:11 +000079// With the SVR4 ABI, callee-saved registers have fixed offsets on the stack.
80const PPCFrameLowering::SpillSlot *PPCFrameLowering::getCalleeSavedSpillSlots(
81 unsigned &NumEntries) const {
82 if (Subtarget.isDarwinABI()) {
83 NumEntries = 1;
84 if (Subtarget.isPPC64()) {
85 static const SpillSlot darwin64Offsets = {PPC::X31, -8};
86 return &darwin64Offsets;
87 } else {
88 static const SpillSlot darwinOffsets = {PPC::R31, -4};
89 return &darwinOffsets;
90 }
91 }
92
93 // Early exit if not using the SVR4 ABI.
94 if (!Subtarget.isSVR4ABI()) {
95 NumEntries = 0;
96 return nullptr;
97 }
98
99 // Note that the offsets here overlap, but this is fixed up in
100 // processFunctionBeforeFrameFinalized.
101
102 static const SpillSlot Offsets[] = {
103 // Floating-point register save area offsets.
104 {PPC::F31, -8},
105 {PPC::F30, -16},
106 {PPC::F29, -24},
107 {PPC::F28, -32},
108 {PPC::F27, -40},
109 {PPC::F26, -48},
110 {PPC::F25, -56},
111 {PPC::F24, -64},
112 {PPC::F23, -72},
113 {PPC::F22, -80},
114 {PPC::F21, -88},
115 {PPC::F20, -96},
116 {PPC::F19, -104},
117 {PPC::F18, -112},
118 {PPC::F17, -120},
119 {PPC::F16, -128},
120 {PPC::F15, -136},
121 {PPC::F14, -144},
122
123 // General register save area offsets.
124 {PPC::R31, -4},
125 {PPC::R30, -8},
126 {PPC::R29, -12},
127 {PPC::R28, -16},
128 {PPC::R27, -20},
129 {PPC::R26, -24},
130 {PPC::R25, -28},
131 {PPC::R24, -32},
132 {PPC::R23, -36},
133 {PPC::R22, -40},
134 {PPC::R21, -44},
135 {PPC::R20, -48},
136 {PPC::R19, -52},
137 {PPC::R18, -56},
138 {PPC::R17, -60},
139 {PPC::R16, -64},
140 {PPC::R15, -68},
141 {PPC::R14, -72},
142
143 // CR save area offset. We map each of the nonvolatile CR fields
144 // to the slot for CR2, which is the first of the nonvolatile CR
145 // fields to be assigned, so that we only allocate one save slot.
146 // See PPCRegisterInfo::hasReservedSpillSlot() for more information.
147 {PPC::CR2, -4},
148
149 // VRSAVE save area offset.
150 {PPC::VRSAVE, -4},
151
152 // Vector register save area
153 {PPC::V31, -16},
154 {PPC::V30, -32},
155 {PPC::V29, -48},
156 {PPC::V28, -64},
157 {PPC::V27, -80},
158 {PPC::V26, -96},
159 {PPC::V25, -112},
160 {PPC::V24, -128},
161 {PPC::V23, -144},
162 {PPC::V22, -160},
163 {PPC::V21, -176},
164 {PPC::V20, -192}};
165
166 static const SpillSlot Offsets64[] = {
167 // Floating-point register save area offsets.
168 {PPC::F31, -8},
169 {PPC::F30, -16},
170 {PPC::F29, -24},
171 {PPC::F28, -32},
172 {PPC::F27, -40},
173 {PPC::F26, -48},
174 {PPC::F25, -56},
175 {PPC::F24, -64},
176 {PPC::F23, -72},
177 {PPC::F22, -80},
178 {PPC::F21, -88},
179 {PPC::F20, -96},
180 {PPC::F19, -104},
181 {PPC::F18, -112},
182 {PPC::F17, -120},
183 {PPC::F16, -128},
184 {PPC::F15, -136},
185 {PPC::F14, -144},
186
187 // General register save area offsets.
188 {PPC::X31, -8},
189 {PPC::X30, -16},
190 {PPC::X29, -24},
191 {PPC::X28, -32},
192 {PPC::X27, -40},
193 {PPC::X26, -48},
194 {PPC::X25, -56},
195 {PPC::X24, -64},
196 {PPC::X23, -72},
197 {PPC::X22, -80},
198 {PPC::X21, -88},
199 {PPC::X20, -96},
200 {PPC::X19, -104},
201 {PPC::X18, -112},
202 {PPC::X17, -120},
203 {PPC::X16, -128},
204 {PPC::X15, -136},
205 {PPC::X14, -144},
206
207 // VRSAVE save area offset.
208 {PPC::VRSAVE, -4},
209
210 // Vector register save area
211 {PPC::V31, -16},
212 {PPC::V30, -32},
213 {PPC::V29, -48},
214 {PPC::V28, -64},
215 {PPC::V27, -80},
216 {PPC::V26, -96},
217 {PPC::V25, -112},
218 {PPC::V24, -128},
219 {PPC::V23, -144},
220 {PPC::V22, -160},
221 {PPC::V21, -176},
222 {PPC::V20, -192}};
223
224 if (Subtarget.isPPC64()) {
225 NumEntries = array_lengthof(Offsets64);
226
227 return Offsets64;
228 } else {
229 NumEntries = array_lengthof(Offsets);
230
231 return Offsets;
232 }
233}
234
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000235/// RemoveVRSaveCode - We have found that this function does not need any code
236/// to manipulate the VRSAVE register, even though it uses vector registers.
237/// This can happen when the only registers used are known to be live in or out
238/// of the function. Remove all of the VRSAVE related code from the function.
Bill Schmidt38d94582012-10-10 20:54:15 +0000239/// FIXME: The removal of the code results in a compile failure at -O0 when the
240/// function contains a function call, as the GPR containing original VRSAVE
241/// contents is spilled and reloaded around the call. Without the prolog code,
242/// the spill instruction refers to an undefined register. This code needs
243/// to account for all uses of that GPR.
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000244static void RemoveVRSaveCode(MachineInstr *MI) {
245 MachineBasicBlock *Entry = MI->getParent();
246 MachineFunction *MF = Entry->getParent();
247
248 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
249 MachineBasicBlock::iterator MBBI = MI;
250 ++MBBI;
251 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
252 MBBI->eraseFromParent();
253
254 bool RemovedAllMTVRSAVEs = true;
255 // See if we can find and remove the MTVRSAVE instruction from all of the
256 // epilog blocks.
257 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
258 // If last instruction is a return instruction, add an epilogue
Evan Cheng7f8e5632011-12-07 07:15:52 +0000259 if (!I->empty() && I->back().isReturn()) {
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000260 bool FoundIt = false;
261 for (MBBI = I->end(); MBBI != I->begin(); ) {
262 --MBBI;
263 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
264 MBBI->eraseFromParent(); // remove it.
265 FoundIt = true;
266 break;
267 }
268 }
269 RemovedAllMTVRSAVEs &= FoundIt;
270 }
271 }
272
273 // If we found and removed all MTVRSAVE instructions, remove the read of
274 // VRSAVE as well.
275 if (RemovedAllMTVRSAVEs) {
276 MBBI = MI;
277 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
278 --MBBI;
279 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
280 MBBI->eraseFromParent();
281 }
282
283 // Finally, nuke the UPDATE_VRSAVE.
284 MI->eraseFromParent();
285}
286
287// HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
288// instruction selector. Based on the vector registers that have been used,
289// transform this into the appropriate ORI instruction.
290static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
291 MachineFunction *MF = MI->getParent()->getParent();
Eric Christopherfc6de422014-08-05 02:39:49 +0000292 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000293 DebugLoc dl = MI->getDebugLoc();
294
295 unsigned UsedRegMask = 0;
296 for (unsigned i = 0; i != 32; ++i)
297 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
298 UsedRegMask |= 1 << (31-i);
299
300 // Live in and live out values already must be in the mask, so don't bother
301 // marking them.
302 for (MachineRegisterInfo::livein_iterator
303 I = MF->getRegInfo().livein_begin(),
304 E = MF->getRegInfo().livein_end(); I != E; ++I) {
Hal Finkelfeea6532013-03-26 20:08:20 +0000305 unsigned RegNo = TRI->getEncodingValue(I->first);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000306 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
307 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
308 }
Jakob Stoklund Olesenbf034db2013-02-05 17:40:36 +0000309
310 // Live out registers appear as use operands on return instructions.
311 for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end();
312 UsedRegMask != 0 && BI != BE; ++BI) {
313 const MachineBasicBlock &MBB = *BI;
314 if (MBB.empty() || !MBB.back().isReturn())
315 continue;
316 const MachineInstr &Ret = MBB.back();
317 for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) {
318 const MachineOperand &MO = Ret.getOperand(I);
319 if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg()))
320 continue;
Hal Finkelfeea6532013-03-26 20:08:20 +0000321 unsigned RegNo = TRI->getEncodingValue(MO.getReg());
Jakob Stoklund Olesenbf034db2013-02-05 17:40:36 +0000322 UsedRegMask &= ~(1 << (31-RegNo));
323 }
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000324 }
325
326 // If no registers are used, turn this into a copy.
327 if (UsedRegMask == 0) {
328 // Remove all VRSAVE code.
329 RemoveVRSaveCode(MI);
330 return;
331 }
332
333 unsigned SrcReg = MI->getOperand(1).getReg();
334 unsigned DstReg = MI->getOperand(0).getReg();
335
336 if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
337 if (DstReg != SrcReg)
338 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
339 .addReg(SrcReg)
340 .addImm(UsedRegMask);
341 else
342 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
343 .addReg(SrcReg, RegState::Kill)
344 .addImm(UsedRegMask);
345 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
346 if (DstReg != SrcReg)
347 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
348 .addReg(SrcReg)
349 .addImm(UsedRegMask >> 16);
350 else
351 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
352 .addReg(SrcReg, RegState::Kill)
353 .addImm(UsedRegMask >> 16);
354 } else {
355 if (DstReg != SrcReg)
356 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
357 .addReg(SrcReg)
358 .addImm(UsedRegMask >> 16);
359 else
360 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
361 .addReg(SrcReg, RegState::Kill)
362 .addImm(UsedRegMask >> 16);
363
364 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
365 .addReg(DstReg, RegState::Kill)
366 .addImm(UsedRegMask & 0xFFFF);
367 }
368
369 // Remove the old UPDATE_VRSAVE instruction.
370 MI->eraseFromParent();
371}
372
Roman Divackyc9e23d92012-09-12 14:47:47 +0000373static bool spillsCR(const MachineFunction &MF) {
374 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
375 return FuncInfo->isCRSpilled();
376}
377
Hal Finkelcc1eeda2013-03-23 22:06:03 +0000378static bool spillsVRSAVE(const MachineFunction &MF) {
379 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
380 return FuncInfo->isVRSAVESpilled();
381}
382
Hal Finkelbb420f12013-03-15 05:06:04 +0000383static bool hasSpills(const MachineFunction &MF) {
384 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
385 return FuncInfo->hasSpills();
386}
387
Hal Finkelfcc51d42013-03-17 04:43:44 +0000388static bool hasNonRISpills(const MachineFunction &MF) {
389 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
390 return FuncInfo->hasNonRISpills();
391}
392
Bill Schmidt82f1c772015-02-10 19:09:05 +0000393/// MustSaveLR - Return true if this function requires that we save the LR
394/// register onto the stack in the prolog and restore it in the epilog of the
395/// function.
396static bool MustSaveLR(const MachineFunction &MF, unsigned LR) {
397 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
398
399 // We need a save/restore of LR if there is any def of LR (which is
400 // defined by calls, including the PIC setup sequence), or if there is
401 // some use of the LR stack slot (e.g. for builtin_return_address).
402 // (LR comes in 32 and 64 bit versions.)
403 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR);
404 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired();
405}
406
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000407/// determineFrameLayout - Determine the size of the frame and maximum call
408/// frame size.
Hal Finkelbb420f12013-03-15 05:06:04 +0000409unsigned PPCFrameLowering::determineFrameLayout(MachineFunction &MF,
410 bool UpdateMF,
411 bool UseEstimate) const {
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000412 MachineFrameInfo *MFI = MF.getFrameInfo();
413
414 // Get the number of bytes to allocate from the FrameInfo
Hal Finkelbb420f12013-03-15 05:06:04 +0000415 unsigned FrameSize =
416 UseEstimate ? MFI->estimateStackSize(MF) : MFI->getStackSize();
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000417
Bill Schmidt8893a3d2013-08-16 20:05:04 +0000418 // Get stack alignments. The frame must be aligned to the greatest of these:
419 unsigned TargetAlign = getStackAlignment(); // alignment required per the ABI
420 unsigned MaxAlign = MFI->getMaxAlignment(); // algmt required by data in frame
Hal Finkela7c54e82013-07-17 00:45:52 +0000421 unsigned AlignMask = std::max(MaxAlign, TargetAlign) - 1;
422
Eric Christopherfc6de422014-08-05 02:39:49 +0000423 const PPCRegisterInfo *RegInfo =
Eric Christopher38522b82015-01-30 02:11:26 +0000424 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000425
426 // If we are a leaf function, and use up to 224 bytes of stack space,
427 // don't have a frame pointer, calls, or dynamic alloca then we do not need
Hal Finkel67369882013-04-15 02:07:05 +0000428 // to adjust the stack pointer (we fit in the Red Zone).
Bill Schmidt8ea7af82013-02-26 21:28:57 +0000429 // The 32-bit SVR4 ABI has no Red Zone. However, it can still generate
430 // stackless code if all local vars are reg-allocated.
Bill Wendling698e84f2012-12-30 10:32:01 +0000431 bool DisableRedZone = MF.getFunction()->getAttributes().
432 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoRedZone);
Bill Schmidt82f1c772015-02-10 19:09:05 +0000433 unsigned LR = RegInfo->getRARegister();
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000434 if (!DisableRedZone &&
Bill Schmidt8ea7af82013-02-26 21:28:57 +0000435 (Subtarget.isPPC64() || // 32-bit SVR4, no stack-
436 !Subtarget.isSVR4ABI() || // allocated locals.
Eric Christopherd1737492014-04-29 00:16:40 +0000437 FrameSize == 0) &&
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000438 FrameSize <= 224 && // Fits in red zone.
439 !MFI->hasVarSizedObjects() && // No dynamic alloca.
440 !MFI->adjustsStack() && // No calls.
Bill Schmidt82f1c772015-02-10 19:09:05 +0000441 !MustSaveLR(MF, LR) &&
Hal Finkela7c54e82013-07-17 00:45:52 +0000442 !RegInfo->hasBasePointer(MF)) { // No special alignment.
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000443 // No need for frame
Hal Finkelbb420f12013-03-15 05:06:04 +0000444 if (UpdateMF)
445 MFI->setStackSize(0);
446 return 0;
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000447 }
448
449 // Get the maximum call frame size of all the calls.
450 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
451
Ulrich Weigandf316e1d2014-06-23 13:47:52 +0000452 // Maximum call frame needs to be at least big enough for linkage area.
Eric Christophera4ae2132015-02-13 22:22:57 +0000453 unsigned minCallFrameSize = getLinkageSize();
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000454 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
455
456 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
457 // that allocations will be aligned.
458 if (MFI->hasVarSizedObjects())
459 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
460
461 // Update maximum call frame size.
Hal Finkelbb420f12013-03-15 05:06:04 +0000462 if (UpdateMF)
463 MFI->setMaxCallFrameSize(maxCallFrameSize);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000464
465 // Include call frame size in total.
466 FrameSize += maxCallFrameSize;
467
468 // Make sure the frame is aligned.
469 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
470
471 // Update frame info.
Hal Finkelbb420f12013-03-15 05:06:04 +0000472 if (UpdateMF)
473 MFI->setStackSize(FrameSize);
474
475 return FrameSize;
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000476}
477
Anton Korobeynikov0eecf5d2010-11-18 21:19:35 +0000478// hasFP - Return true if the specified function actually has a dedicated frame
479// pointer register.
Anton Korobeynikov2f931282011-01-10 12:39:04 +0000480bool PPCFrameLowering::hasFP(const MachineFunction &MF) const {
Anton Korobeynikov0eecf5d2010-11-18 21:19:35 +0000481 const MachineFrameInfo *MFI = MF.getFrameInfo();
Anton Korobeynikov3eb4fed2010-12-18 19:53:14 +0000482 // FIXME: This is pretty much broken by design: hasFP() might be called really
483 // early, before the stack layout was calculated and thus hasFP() might return
484 // true or false here depending on the time of call.
485 return (MFI->getStackSize()) && needsFP(MF);
486}
487
488// needsFP - Return true if the specified function should have a dedicated frame
489// pointer register. This is true if the function has variable sized allocas or
490// if frame pointer elimination is disabled.
Anton Korobeynikov2f931282011-01-10 12:39:04 +0000491bool PPCFrameLowering::needsFP(const MachineFunction &MF) const {
Anton Korobeynikov3eb4fed2010-12-18 19:53:14 +0000492 const MachineFrameInfo *MFI = MF.getFrameInfo();
Anton Korobeynikov0eecf5d2010-11-18 21:19:35 +0000493
494 // Naked functions have no stack frame pushed, so we don't have a frame
495 // pointer.
Eric Christopherd1737492014-04-29 00:16:40 +0000496 if (MF.getFunction()->getAttributes().hasAttribute(
497 AttributeSet::FunctionIndex, Attribute::Naked))
Anton Korobeynikov0eecf5d2010-11-18 21:19:35 +0000498 return false;
499
Nick Lewycky50f02cb2011-12-02 22:16:29 +0000500 return MF.getTarget().Options.DisableFramePointerElim(MF) ||
501 MFI->hasVarSizedObjects() ||
Hal Finkel934361a2015-01-14 01:07:51 +0000502 MFI->hasStackMap() || MFI->hasPatchPoint() ||
Nick Lewycky50f02cb2011-12-02 22:16:29 +0000503 (MF.getTarget().Options.GuaranteedTailCallOpt &&
504 MF.getInfo<PPCFunctionInfo>()->hasFastCall());
Anton Korobeynikov0eecf5d2010-11-18 21:19:35 +0000505}
506
Hal Finkelaa03c032013-03-21 19:03:19 +0000507void PPCFrameLowering::replaceFPWithRealFP(MachineFunction &MF) const {
508 bool is31 = needsFP(MF);
509 unsigned FPReg = is31 ? PPC::R31 : PPC::R1;
510 unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1;
511
Eric Christopherfc6de422014-08-05 02:39:49 +0000512 const PPCRegisterInfo *RegInfo =
Eric Christopher38522b82015-01-30 02:11:26 +0000513 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
Hal Finkelf05d6c72013-07-17 23:50:51 +0000514 bool HasBP = RegInfo->hasBasePointer(MF);
Hal Finkel3ee2af72014-07-18 23:29:49 +0000515 unsigned BPReg = HasBP ? (unsigned) RegInfo->getBaseRegister(MF) : FPReg;
Hal Finkelf05d6c72013-07-17 23:50:51 +0000516 unsigned BP8Reg = HasBP ? (unsigned) PPC::X30 : FPReg;
517
Hal Finkelaa03c032013-03-21 19:03:19 +0000518 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
519 BI != BE; ++BI)
520 for (MachineBasicBlock::iterator MBBI = BI->end(); MBBI != BI->begin(); ) {
521 --MBBI;
522 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
523 MachineOperand &MO = MBBI->getOperand(I);
524 if (!MO.isReg())
525 continue;
526
527 switch (MO.getReg()) {
528 case PPC::FP:
529 MO.setReg(FPReg);
530 break;
531 case PPC::FP8:
532 MO.setReg(FP8Reg);
533 break;
Hal Finkelf05d6c72013-07-17 23:50:51 +0000534 case PPC::BP:
535 MO.setReg(BPReg);
536 break;
537 case PPC::BP8:
538 MO.setReg(BP8Reg);
539 break;
540
Hal Finkelaa03c032013-03-21 19:03:19 +0000541 }
542 }
543 }
544}
Anton Korobeynikov0eecf5d2010-11-18 21:19:35 +0000545
Anton Korobeynikov2f931282011-01-10 12:39:04 +0000546void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000547 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
548 MachineBasicBlock::iterator MBBI = MBB.begin();
549 MachineFrameInfo *MFI = MF.getFrameInfo();
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000550 const PPCInstrInfo &TII =
Eric Christopher38522b82015-01-30 02:11:26 +0000551 *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo());
Eric Christopherfc6de422014-08-05 02:39:49 +0000552 const PPCRegisterInfo *RegInfo =
Eric Christopher38522b82015-01-30 02:11:26 +0000553 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000554
555 MachineModuleInfo &MMI = MF.getMMI();
Bill Wendlingbc07a892013-06-18 07:20:20 +0000556 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000557 DebugLoc dl;
Jay Foad1f0a44e2014-12-01 09:42:32 +0000558 bool needsCFI = MMI.hasDebugInfo() ||
Rafael Espindolafc9bae62011-05-25 03:44:17 +0000559 MF.getFunction()->needsUnwindTableEntry();
Hal Finkel3ee2af72014-07-18 23:29:49 +0000560 bool isPIC = MF.getTarget().getRelocationModel() == Reloc::PIC_;
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000561
Bill Schmidt8893a3d2013-08-16 20:05:04 +0000562 // Get processor type.
563 bool isPPC64 = Subtarget.isPPC64();
564 // Get the ABI.
565 bool isDarwinABI = Subtarget.isDarwinABI();
566 bool isSVR4ABI = Subtarget.isSVR4ABI();
Ulrich Weigandbe928cc2014-07-21 00:03:18 +0000567 bool isELFv2ABI = Subtarget.isELFv2ABI();
Bill Schmidt8893a3d2013-08-16 20:05:04 +0000568 assert((isDarwinABI || isSVR4ABI) &&
569 "Currently only Darwin and SVR4 ABIs are supported for PowerPC.");
570
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000571 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
572 // process it.
Bill Schmidt8893a3d2013-08-16 20:05:04 +0000573 if (!isSVR4ABI)
Bill Schmidt38d94582012-10-10 20:54:15 +0000574 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
575 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
576 HandleVRSaveUpdate(MBBI, TII);
577 break;
578 }
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000579 }
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000580
581 // Move MBBI back to the beginning of the function.
582 MBBI = MBB.begin();
583
584 // Work out frame sizes.
Hal Finkelbb420f12013-03-15 05:06:04 +0000585 unsigned FrameSize = determineFrameLayout(MF);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000586 int NegFrameSize = -FrameSize;
Hal Finkela7c54e82013-07-17 00:45:52 +0000587 if (!isInt<32>(NegFrameSize))
588 llvm_unreachable("Unhandled stack size!");
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000589
Hal Finkelaa03c032013-03-21 19:03:19 +0000590 if (MFI->isFrameAddressTaken())
591 replaceFPWithRealFP(MF);
592
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000593 // Check if the link register (LR) must be saved.
594 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
595 bool MustSaveLR = FI->mustSaveLR();
Craig Topperb94011f2013-07-14 04:42:23 +0000596 const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
Bill Schmidtf381afc2013-08-20 03:12:23 +0000597 // Do we have a frame pointer and/or base pointer for this function?
Anton Korobeynikov3eb4fed2010-12-18 19:53:14 +0000598 bool HasFP = hasFP(MF);
Hal Finkela7c54e82013-07-17 00:45:52 +0000599 bool HasBP = RegInfo->hasBasePointer(MF);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000600
Bill Schmidtf381afc2013-08-20 03:12:23 +0000601 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
Hal Finkel3ee2af72014-07-18 23:29:49 +0000602 unsigned BPReg = RegInfo->getBaseRegister(MF);
Bill Schmidtf381afc2013-08-20 03:12:23 +0000603 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
604 unsigned LRReg = isPPC64 ? PPC::LR8 : PPC::LR;
605 unsigned ScratchReg = isPPC64 ? PPC::X0 : PPC::R0;
606 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
607 // ...(R12/X12 is volatile in both Darwin & SVR4, & can't be a function arg.)
608 const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8
609 : PPC::MFLR );
610 const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD
611 : PPC::STW );
612 const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU
613 : PPC::STWU );
614 const MCInstrDesc& StoreUpdtIdxInst = TII.get(isPPC64 ? PPC::STDUX
615 : PPC::STWUX);
616 const MCInstrDesc& LoadImmShiftedInst = TII.get(isPPC64 ? PPC::LIS8
617 : PPC::LIS );
618 const MCInstrDesc& OrImmInst = TII.get(isPPC64 ? PPC::ORI8
619 : PPC::ORI );
620 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
621 : PPC::OR );
622 const MCInstrDesc& SubtractCarryingInst = TII.get(isPPC64 ? PPC::SUBFC8
623 : PPC::SUBFC);
624 const MCInstrDesc& SubtractImmCarryingInst = TII.get(isPPC64 ? PPC::SUBFIC8
625 : PPC::SUBFIC);
626
Bill Schmidt8893a3d2013-08-16 20:05:04 +0000627 // Regarding this assert: Even though LR is saved in the caller's frame (i.e.,
628 // LROffset is positive), that slot is callee-owned. Because PPC32 SVR4 has no
629 // Red Zone, an asynchronous event (a form of "callee") could claim a frame &
630 // overwrite it, so PPC32 SVR4 must claim at least a minimal frame to save LR.
631 assert((isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR || HasFP))) &&
632 "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4.");
633
Eric Christopherf71609b2015-02-13 00:39:27 +0000634 int LROffset = getReturnSaveOffset();
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000635
636 int FPOffset = 0;
637 if (HasFP) {
Bill Schmidt8893a3d2013-08-16 20:05:04 +0000638 if (isSVR4ABI) {
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000639 MachineFrameInfo *FFI = MF.getFrameInfo();
640 int FPIndex = FI->getFramePointerSaveIndex();
641 assert(FPIndex && "No Frame Pointer Save Slot!");
642 FPOffset = FFI->getObjectOffset(FPIndex);
643 } else {
Eric Christopherdc3a8a42015-02-13 00:39:38 +0000644 FPOffset = getFramePointerSaveOffset();
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000645 }
646 }
647
Hal Finkela7c54e82013-07-17 00:45:52 +0000648 int BPOffset = 0;
649 if (HasBP) {
Bill Schmidt8893a3d2013-08-16 20:05:04 +0000650 if (isSVR4ABI) {
Hal Finkela7c54e82013-07-17 00:45:52 +0000651 MachineFrameInfo *FFI = MF.getFrameInfo();
652 int BPIndex = FI->getBasePointerSaveIndex();
653 assert(BPIndex && "No Base Pointer Save Slot!");
654 BPOffset = FFI->getObjectOffset(BPIndex);
655 } else {
656 BPOffset =
Hal Finkel3ee2af72014-07-18 23:29:49 +0000657 PPCFrameLowering::getBasePointerSaveOffset(isPPC64,
658 isDarwinABI,
659 isPIC);
Hal Finkela7c54e82013-07-17 00:45:52 +0000660 }
661 }
662
Justin Hibbits654346e2015-01-10 01:57:21 +0000663 int PBPOffset = 0;
664 if (FI->usesPICBase()) {
665 MachineFrameInfo *FFI = MF.getFrameInfo();
666 int PBPIndex = FI->getPICBasePointerSaveIndex();
667 assert(PBPIndex && "No PIC Base Pointer Save Slot!");
668 PBPOffset = FFI->getObjectOffset(PBPIndex);
669 }
670
Bill Schmidt8893a3d2013-08-16 20:05:04 +0000671 // Get stack alignments.
672 unsigned MaxAlign = MFI->getMaxAlignment();
673 if (HasBP && MaxAlign > 1)
674 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
675 "Invalid alignment!");
676
677 // Frames of 32KB & larger require special handling because they cannot be
678 // indexed into with a simple STDU/STWU/STD/STW immediate offset operand.
679 bool isLargeFrame = !isInt<16>(NegFrameSize);
680
Bill Schmidtf381afc2013-08-20 03:12:23 +0000681 if (MustSaveLR)
682 BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000683
Bill Schmidtf381afc2013-08-20 03:12:23 +0000684 assert((isPPC64 || MustSaveCRs.empty()) &&
685 "Prologue CR saving supported only in 64-bit mode");
Hal Finkel67369882013-04-15 02:07:05 +0000686
Bill Schmidtf381afc2013-08-20 03:12:23 +0000687 if (!MustSaveCRs.empty()) { // will only occur for PPC64
Ulrich Weigandbe928cc2014-07-21 00:03:18 +0000688 // FIXME: In the ELFv2 ABI, we are not required to save all CR fields.
689 // If only one or two CR fields are clobbered, it could be more
690 // efficient to use mfocrf to selectively save just those fields.
Bill Schmidtf381afc2013-08-20 03:12:23 +0000691 MachineInstrBuilder MIB =
692 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFCR8), TempReg);
693 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
694 MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000695 }
696
Bill Schmidtf381afc2013-08-20 03:12:23 +0000697 if (HasFP)
698 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
699 BuildMI(MBB, MBBI, dl, StoreInst)
700 .addReg(FPReg)
701 .addImm(FPOffset)
702 .addReg(SPReg);
703
Justin Hibbits654346e2015-01-10 01:57:21 +0000704 if (FI->usesPICBase())
Justin Hibbits98a532d2015-01-08 15:47:19 +0000705 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
706 BuildMI(MBB, MBBI, dl, StoreInst)
707 .addReg(PPC::R30)
Justin Hibbits654346e2015-01-10 01:57:21 +0000708 .addImm(PBPOffset)
Justin Hibbits98a532d2015-01-08 15:47:19 +0000709 .addReg(SPReg);
710
Bill Schmidtf381afc2013-08-20 03:12:23 +0000711 if (HasBP)
712 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
713 BuildMI(MBB, MBBI, dl, StoreInst)
714 .addReg(BPReg)
715 .addImm(BPOffset)
716 .addReg(SPReg);
717
718 if (MustSaveLR)
719 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
720 BuildMI(MBB, MBBI, dl, StoreInst)
721 .addReg(ScratchReg)
722 .addImm(LROffset)
723 .addReg(SPReg);
724
725 if (!MustSaveCRs.empty()) // will only occur for PPC64
726 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
727 .addReg(TempReg, getKillRegState(true))
728 .addImm(8)
729 .addReg(SPReg);
730
Bill Schmidt8893a3d2013-08-16 20:05:04 +0000731 // Skip the rest if this is a leaf function & all spills fit in the Red Zone.
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000732 if (!FrameSize) return;
733
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000734 // Adjust stack pointer: r1 += NegFrameSize.
735 // If there is a preferred stack alignment, align R1 now
Hal Finkela7c54e82013-07-17 00:45:52 +0000736
Bill Schmidtf381afc2013-08-20 03:12:23 +0000737 if (HasBP) {
738 // Save a copy of r1 as the base pointer.
739 BuildMI(MBB, MBBI, dl, OrInst, BPReg)
740 .addReg(SPReg)
741 .addReg(SPReg);
742 }
743
744 if (HasBP && MaxAlign > 1) {
745 if (isPPC64)
746 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg)
747 .addReg(SPReg)
748 .addImm(0)
749 .addImm(64 - Log2_32(MaxAlign));
750 else // PPC32...
751 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), ScratchReg)
752 .addReg(SPReg)
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000753 .addImm(0)
754 .addImm(32 - Log2_32(MaxAlign))
755 .addImm(31);
Bill Schmidtf381afc2013-08-20 03:12:23 +0000756 if (!isLargeFrame) {
757 BuildMI(MBB, MBBI, dl, SubtractImmCarryingInst, ScratchReg)
758 .addReg(ScratchReg, RegState::Kill)
759 .addImm(NegFrameSize);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000760 } else {
Bill Schmidtf381afc2013-08-20 03:12:23 +0000761 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, TempReg)
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000762 .addImm(NegFrameSize >> 16);
Bill Schmidtf381afc2013-08-20 03:12:23 +0000763 BuildMI(MBB, MBBI, dl, OrImmInst, TempReg)
764 .addReg(TempReg, RegState::Kill)
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000765 .addImm(NegFrameSize & 0xFFFF);
Bill Schmidtf381afc2013-08-20 03:12:23 +0000766 BuildMI(MBB, MBBI, dl, SubtractCarryingInst, ScratchReg)
767 .addReg(ScratchReg, RegState::Kill)
768 .addReg(TempReg, RegState::Kill);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000769 }
Bill Schmidtf381afc2013-08-20 03:12:23 +0000770 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
771 .addReg(SPReg, RegState::Kill)
772 .addReg(SPReg)
773 .addReg(ScratchReg);
Hal Finkela7c54e82013-07-17 00:45:52 +0000774
Bill Schmidtf381afc2013-08-20 03:12:23 +0000775 } else if (!isLargeFrame) {
776 BuildMI(MBB, MBBI, dl, StoreUpdtInst, SPReg)
777 .addReg(SPReg)
778 .addImm(NegFrameSize)
779 .addReg(SPReg);
Bill Schmidt8893a3d2013-08-16 20:05:04 +0000780
Bill Schmidtf381afc2013-08-20 03:12:23 +0000781 } else {
782 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
783 .addImm(NegFrameSize >> 16);
784 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
785 .addReg(ScratchReg, RegState::Kill)
786 .addImm(NegFrameSize & 0xFFFF);
787 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
788 .addReg(SPReg, RegState::Kill)
789 .addReg(SPReg)
790 .addReg(ScratchReg);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000791 }
792
Jay Foad1f0a44e2014-12-01 09:42:32 +0000793 // Add Call Frame Information for the instructions we generated above.
794 if (needsCFI) {
795 unsigned CFIIndex;
796
797 if (HasBP) {
798 // Define CFA in terms of BP. Do this in preference to using FP/SP,
799 // because if the stack needed aligning then CFA won't be at a fixed
800 // offset from FP/SP.
801 unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
802 CFIIndex = MMI.addFrameInst(
803 MCCFIInstruction::createDefCfaRegister(nullptr, Reg));
804 } else {
805 // Adjust the definition of CFA to account for the change in SP.
806 assert(NegFrameSize);
807 CFIIndex = MMI.addFrameInst(
808 MCCFIInstruction::createDefCfaOffset(nullptr, NegFrameSize));
809 }
Eric Christopher612bb692014-04-29 00:16:46 +0000810 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
811 .addCFIIndex(CFIIndex);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000812
813 if (HasFP) {
Jay Foad1f0a44e2014-12-01 09:42:32 +0000814 // Describe where FP was saved, at a fixed offset from CFA.
Bill Schmidtf381afc2013-08-20 03:12:23 +0000815 unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
Rafael Espindolab1f25f12014-03-07 06:08:31 +0000816 CFIIndex = MMI.addFrameInst(
817 MCCFIInstruction::createOffset(nullptr, Reg, FPOffset));
Eric Christopher612bb692014-04-29 00:16:46 +0000818 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
Rafael Espindolab1f25f12014-03-07 06:08:31 +0000819 .addCFIIndex(CFIIndex);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000820 }
821
Justin Hibbits654346e2015-01-10 01:57:21 +0000822 if (FI->usesPICBase()) {
823 // Describe where FP was saved, at a fixed offset from CFA.
824 unsigned Reg = MRI->getDwarfRegNum(PPC::R30, true);
825 CFIIndex = MMI.addFrameInst(
826 MCCFIInstruction::createOffset(nullptr, Reg, PBPOffset));
827 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
828 .addCFIIndex(CFIIndex);
829 }
830
Hal Finkela7c54e82013-07-17 00:45:52 +0000831 if (HasBP) {
Jay Foad1f0a44e2014-12-01 09:42:32 +0000832 // Describe where BP was saved, at a fixed offset from CFA.
Bill Schmidtf381afc2013-08-20 03:12:23 +0000833 unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
Rafael Espindolab1f25f12014-03-07 06:08:31 +0000834 CFIIndex = MMI.addFrameInst(
835 MCCFIInstruction::createOffset(nullptr, Reg, BPOffset));
Eric Christopher612bb692014-04-29 00:16:46 +0000836 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
Rafael Espindolab1f25f12014-03-07 06:08:31 +0000837 .addCFIIndex(CFIIndex);
Hal Finkela7c54e82013-07-17 00:45:52 +0000838 }
839
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000840 if (MustSaveLR) {
Jay Foad1f0a44e2014-12-01 09:42:32 +0000841 // Describe where LR was saved, at a fixed offset from CFA.
Bill Schmidtf381afc2013-08-20 03:12:23 +0000842 unsigned Reg = MRI->getDwarfRegNum(LRReg, true);
Rafael Espindolab1f25f12014-03-07 06:08:31 +0000843 CFIIndex = MMI.addFrameInst(
844 MCCFIInstruction::createOffset(nullptr, Reg, LROffset));
Eric Christopher612bb692014-04-29 00:16:46 +0000845 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
Rafael Espindolab1f25f12014-03-07 06:08:31 +0000846 .addCFIIndex(CFIIndex);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000847 }
848 }
849
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000850 // If there is a frame pointer, copy R1 into R31
851 if (HasFP) {
Bill Schmidtf381afc2013-08-20 03:12:23 +0000852 BuildMI(MBB, MBBI, dl, OrInst, FPReg)
853 .addReg(SPReg)
854 .addReg(SPReg);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000855
Jay Foad1f0a44e2014-12-01 09:42:32 +0000856 if (!HasBP && needsCFI) {
857 // Change the definition of CFA from SP+offset to FP+offset, because SP
858 // will change at every alloca.
Bill Schmidtf381afc2013-08-20 03:12:23 +0000859 unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
Rafael Espindolab1f25f12014-03-07 06:08:31 +0000860 unsigned CFIIndex = MMI.addFrameInst(
861 MCCFIInstruction::createDefCfaRegister(nullptr, Reg));
862
Eric Christopher612bb692014-04-29 00:16:46 +0000863 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
Rafael Espindolab1f25f12014-03-07 06:08:31 +0000864 .addCFIIndex(CFIIndex);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000865 }
866 }
867
Jay Foad1f0a44e2014-12-01 09:42:32 +0000868 if (needsCFI) {
869 // Describe where callee saved registers were saved, at fixed offsets from
870 // CFA.
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000871 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
872 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000873 unsigned Reg = CSI[I].getReg();
874 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
Rafael Espindola08600bc2011-05-30 20:20:15 +0000875
876 // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just
877 // subregisters of CR2. We just need to emit a move of CR2.
Craig Topperabadc662012-04-20 06:31:50 +0000878 if (PPC::CRBITRCRegClass.contains(Reg))
Rafael Espindola08600bc2011-05-30 20:20:15 +0000879 continue;
Rafael Espindola08600bc2011-05-30 20:20:15 +0000880
Roman Divackyc9e23d92012-09-12 14:47:47 +0000881 // For SVR4, don't emit a move for the CR spill slot if we haven't
882 // spilled CRs.
Bill Schmidt8893a3d2013-08-16 20:05:04 +0000883 if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4)
884 && MustSaveCRs.empty())
885 continue;
Roman Divackyc9e23d92012-09-12 14:47:47 +0000886
887 // For 64-bit SVR4 when we have spilled CRs, the spill location
888 // is SP+8, not a frame-relative slot.
Bill Schmidt8893a3d2013-08-16 20:05:04 +0000889 if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
Ulrich Weigandbe928cc2014-07-21 00:03:18 +0000890 // In the ELFv1 ABI, only CR2 is noted in CFI and stands in for
891 // the whole CR word. In the ELFv2 ABI, every CR that was
892 // actually saved gets its own CFI record.
893 unsigned CRReg = isELFv2ABI? Reg : (unsigned) PPC::CR2;
Rafael Espindolab1f25f12014-03-07 06:08:31 +0000894 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
Ulrich Weigandbe928cc2014-07-21 00:03:18 +0000895 nullptr, MRI->getDwarfRegNum(CRReg, true), 8));
Eric Christopher612bb692014-04-29 00:16:46 +0000896 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
Rafael Espindolab1f25f12014-03-07 06:08:31 +0000897 .addCFIIndex(CFIIndex);
Bill Schmidt8893a3d2013-08-16 20:05:04 +0000898 continue;
Roman Divackyc9e23d92012-09-12 14:47:47 +0000899 }
900
901 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
Rafael Espindolab1f25f12014-03-07 06:08:31 +0000902 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
903 nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
Eric Christopher612bb692014-04-29 00:16:46 +0000904 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
Rafael Espindolab1f25f12014-03-07 06:08:31 +0000905 .addCFIIndex(CFIIndex);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000906 }
907 }
908}
909
Anton Korobeynikov2f931282011-01-10 12:39:04 +0000910void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000911 MachineBasicBlock &MBB) const {
Jakob Stoklund Olesen4bc5e382011-01-13 21:28:52 +0000912 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
913 assert(MBBI != MBB.end() && "Returning block has no terminator");
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000914 const PPCInstrInfo &TII =
Eric Christopher38522b82015-01-30 02:11:26 +0000915 *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo());
Eric Christopherfc6de422014-08-05 02:39:49 +0000916 const PPCRegisterInfo *RegInfo =
Eric Christopher38522b82015-01-30 02:11:26 +0000917 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000918
919 unsigned RetOpcode = MBBI->getOpcode();
920 DebugLoc dl;
921
Anton Korobeynikov0eecf5d2010-11-18 21:19:35 +0000922 assert((RetOpcode == PPC::BLR ||
Hal Finkelf4a22c02015-01-13 17:47:54 +0000923 RetOpcode == PPC::BLR8 ||
Anton Korobeynikov0eecf5d2010-11-18 21:19:35 +0000924 RetOpcode == PPC::TCRETURNri ||
925 RetOpcode == PPC::TCRETURNdi ||
926 RetOpcode == PPC::TCRETURNai ||
927 RetOpcode == PPC::TCRETURNri8 ||
928 RetOpcode == PPC::TCRETURNdi8 ||
929 RetOpcode == PPC::TCRETURNai8) &&
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000930 "Can only insert epilog into returning blocks");
931
Bill Schmidt8893a3d2013-08-16 20:05:04 +0000932 // Get alignment info so we know how to restore the SP.
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000933 const MachineFrameInfo *MFI = MF.getFrameInfo();
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000934
935 // Get the number of bytes allocated from the FrameInfo.
936 int FrameSize = MFI->getStackSize();
937
938 // Get processor type.
939 bool isPPC64 = Subtarget.isPPC64();
Bill Schmidt8893a3d2013-08-16 20:05:04 +0000940 // Get the ABI.
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000941 bool isDarwinABI = Subtarget.isDarwinABI();
Bill Schmidt8893a3d2013-08-16 20:05:04 +0000942 bool isSVR4ABI = Subtarget.isSVR4ABI();
Hal Finkel3ee2af72014-07-18 23:29:49 +0000943 bool isPIC = MF.getTarget().getRelocationModel() == Reloc::PIC_;
Bill Schmidt8893a3d2013-08-16 20:05:04 +0000944
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000945 // Check if the link register (LR) has been saved.
946 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
947 bool MustSaveLR = FI->mustSaveLR();
Craig Topperb94011f2013-07-14 04:42:23 +0000948 const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
Bill Schmidtf381afc2013-08-20 03:12:23 +0000949 // Do we have a frame pointer and/or base pointer for this function?
Anton Korobeynikov3eb4fed2010-12-18 19:53:14 +0000950 bool HasFP = hasFP(MF);
Hal Finkela7c54e82013-07-17 00:45:52 +0000951 bool HasBP = RegInfo->hasBasePointer(MF);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000952
Bill Schmidtf381afc2013-08-20 03:12:23 +0000953 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
Hal Finkel3ee2af72014-07-18 23:29:49 +0000954 unsigned BPReg = RegInfo->getBaseRegister(MF);
Bill Schmidtf381afc2013-08-20 03:12:23 +0000955 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
956 unsigned ScratchReg = isPPC64 ? PPC::X0 : PPC::R0;
957 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
958 const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8
959 : PPC::MTLR );
960 const MCInstrDesc& LoadInst = TII.get( isPPC64 ? PPC::LD
961 : PPC::LWZ );
962 const MCInstrDesc& LoadImmShiftedInst = TII.get( isPPC64 ? PPC::LIS8
963 : PPC::LIS );
964 const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8
965 : PPC::ORI );
966 const MCInstrDesc& AddImmInst = TII.get( isPPC64 ? PPC::ADDI8
967 : PPC::ADDI );
968 const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8
969 : PPC::ADD4 );
970
Eric Christopherf71609b2015-02-13 00:39:27 +0000971 int LROffset = getReturnSaveOffset();
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000972
973 int FPOffset = 0;
974 if (HasFP) {
Bill Schmidt8893a3d2013-08-16 20:05:04 +0000975 if (isSVR4ABI) {
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000976 MachineFrameInfo *FFI = MF.getFrameInfo();
977 int FPIndex = FI->getFramePointerSaveIndex();
978 assert(FPIndex && "No Frame Pointer Save Slot!");
979 FPOffset = FFI->getObjectOffset(FPIndex);
980 } else {
Eric Christopherdc3a8a42015-02-13 00:39:38 +0000981 FPOffset = getFramePointerSaveOffset();
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000982 }
983 }
984
Hal Finkela7c54e82013-07-17 00:45:52 +0000985 int BPOffset = 0;
986 if (HasBP) {
Bill Schmidt8893a3d2013-08-16 20:05:04 +0000987 if (isSVR4ABI) {
Hal Finkela7c54e82013-07-17 00:45:52 +0000988 MachineFrameInfo *FFI = MF.getFrameInfo();
989 int BPIndex = FI->getBasePointerSaveIndex();
990 assert(BPIndex && "No Base Pointer Save Slot!");
991 BPOffset = FFI->getObjectOffset(BPIndex);
992 } else {
993 BPOffset =
Hal Finkel3ee2af72014-07-18 23:29:49 +0000994 PPCFrameLowering::getBasePointerSaveOffset(isPPC64,
995 isDarwinABI,
996 isPIC);
Hal Finkela7c54e82013-07-17 00:45:52 +0000997 }
998 }
999
Justin Hibbits654346e2015-01-10 01:57:21 +00001000 int PBPOffset = 0;
1001 if (FI->usesPICBase()) {
1002 MachineFrameInfo *FFI = MF.getFrameInfo();
1003 int PBPIndex = FI->getPICBasePointerSaveIndex();
1004 assert(PBPIndex && "No PIC Base Pointer Save Slot!");
1005 PBPOffset = FFI->getObjectOffset(PBPIndex);
1006 }
1007
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +00001008 bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
1009 RetOpcode == PPC::TCRETURNdi ||
1010 RetOpcode == PPC::TCRETURNai ||
1011 RetOpcode == PPC::TCRETURNri8 ||
1012 RetOpcode == PPC::TCRETURNdi8 ||
1013 RetOpcode == PPC::TCRETURNai8;
1014
1015 if (UsesTCRet) {
1016 int MaxTCRetDelta = FI->getTailCallSPDelta();
1017 MachineOperand &StackAdjust = MBBI->getOperand(1);
1018 assert(StackAdjust.isImm() && "Expecting immediate value.");
1019 // Adjust stack pointer.
1020 int StackAdj = StackAdjust.getImm();
1021 int Delta = StackAdj - MaxTCRetDelta;
1022 assert((Delta >= 0) && "Delta must be positive");
1023 if (MaxTCRetDelta>0)
1024 FrameSize += (StackAdj +Delta);
1025 else
1026 FrameSize += StackAdj;
1027 }
1028
Bill Schmidt8893a3d2013-08-16 20:05:04 +00001029 // Frames of 32KB & larger require special handling because they cannot be
1030 // indexed into with a simple LD/LWZ immediate offset operand.
1031 bool isLargeFrame = !isInt<16>(FrameSize);
1032
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +00001033 if (FrameSize) {
Bill Schmidt8893a3d2013-08-16 20:05:04 +00001034 // In the prologue, the loaded (or persistent) stack pointer value is offset
1035 // by the STDU/STDUX/STWU/STWUX instruction. Add this offset back now.
Bill Schmidtf381afc2013-08-20 03:12:23 +00001036
1037 // If this function contained a fastcc call and GuaranteedTailCallOpt is
1038 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail
1039 // call which invalidates the stack pointer value in SP(0). So we use the
1040 // value of R31 in this case.
1041 if (FI->hasFastCall()) {
1042 assert(HasFP && "Expecting a valid frame pointer.");
1043 if (!isLargeFrame) {
1044 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1045 .addReg(FPReg).addImm(FrameSize);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +00001046 } else {
Bill Schmidtf381afc2013-08-20 03:12:23 +00001047 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
1048 .addImm(FrameSize >> 16);
1049 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
1050 .addReg(ScratchReg, RegState::Kill)
1051 .addImm(FrameSize & 0xFFFF);
1052 BuildMI(MBB, MBBI, dl, AddInst)
1053 .addReg(SPReg)
1054 .addReg(FPReg)
1055 .addReg(ScratchReg);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +00001056 }
Bill Schmidtf381afc2013-08-20 03:12:23 +00001057 } else if (!isLargeFrame && !HasBP && !MFI->hasVarSizedObjects()) {
1058 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1059 .addReg(SPReg)
1060 .addImm(FrameSize);
1061 } else {
1062 BuildMI(MBB, MBBI, dl, LoadInst, SPReg)
1063 .addImm(0)
1064 .addReg(SPReg);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +00001065 }
Bill Schmidtf381afc2013-08-20 03:12:23 +00001066
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +00001067 }
1068
Bill Schmidtf381afc2013-08-20 03:12:23 +00001069 if (MustSaveLR)
1070 BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
1071 .addImm(LROffset)
1072 .addReg(SPReg);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +00001073
Bill Schmidtf381afc2013-08-20 03:12:23 +00001074 assert((isPPC64 || MustSaveCRs.empty()) &&
1075 "Epilogue CR restoring supported only in 64-bit mode");
Hal Finkel67369882013-04-15 02:07:05 +00001076
Bill Schmidtf381afc2013-08-20 03:12:23 +00001077 if (!MustSaveCRs.empty()) // will only occur for PPC64
1078 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
1079 .addImm(8)
1080 .addReg(SPReg);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +00001081
Bill Schmidtf381afc2013-08-20 03:12:23 +00001082 if (HasFP)
1083 BuildMI(MBB, MBBI, dl, LoadInst, FPReg)
1084 .addImm(FPOffset)
1085 .addReg(SPReg);
Hal Finkela7c54e82013-07-17 00:45:52 +00001086
Justin Hibbits654346e2015-01-10 01:57:21 +00001087 if (FI->usesPICBase())
Justin Hibbits98a532d2015-01-08 15:47:19 +00001088 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
1089 BuildMI(MBB, MBBI, dl, LoadInst)
1090 .addReg(PPC::R30)
Justin Hibbits654346e2015-01-10 01:57:21 +00001091 .addImm(PBPOffset)
Justin Hibbits98a532d2015-01-08 15:47:19 +00001092 .addReg(SPReg);
1093
Bill Schmidtf381afc2013-08-20 03:12:23 +00001094 if (HasBP)
1095 BuildMI(MBB, MBBI, dl, LoadInst, BPReg)
1096 .addImm(BPOffset)
1097 .addReg(SPReg);
Hal Finkel67369882013-04-15 02:07:05 +00001098
Bill Schmidtf381afc2013-08-20 03:12:23 +00001099 if (!MustSaveCRs.empty()) // will only occur for PPC64
1100 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
1101 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i])
1102 .addReg(TempReg, getKillRegState(i == e-1));
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +00001103
Bill Schmidtf381afc2013-08-20 03:12:23 +00001104 if (MustSaveLR)
1105 BuildMI(MBB, MBBI, dl, MTLRInst).addReg(ScratchReg);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +00001106
1107 // Callee pop calling convention. Pop parameter/linkage area. Used for tail
1108 // call optimization
Hal Finkelf4a22c02015-01-13 17:47:54 +00001109 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1110 (RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8) &&
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +00001111 MF.getFunction()->getCallingConv() == CallingConv::Fast) {
1112 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1113 unsigned CallerAllocatedAmt = FI->getMinReservedArea();
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +00001114
1115 if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) {
Bill Schmidtf381afc2013-08-20 03:12:23 +00001116 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1117 .addReg(SPReg).addImm(CallerAllocatedAmt);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +00001118 } else {
Bill Schmidtf381afc2013-08-20 03:12:23 +00001119 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +00001120 .addImm(CallerAllocatedAmt >> 16);
Bill Schmidtf381afc2013-08-20 03:12:23 +00001121 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
1122 .addReg(ScratchReg, RegState::Kill)
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +00001123 .addImm(CallerAllocatedAmt & 0xFFFF);
Bill Schmidtf381afc2013-08-20 03:12:23 +00001124 BuildMI(MBB, MBBI, dl, AddInst)
1125 .addReg(SPReg)
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +00001126 .addReg(FPReg)
Bill Schmidtf381afc2013-08-20 03:12:23 +00001127 .addReg(ScratchReg);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +00001128 }
1129 } else if (RetOpcode == PPC::TCRETURNdi) {
Jakob Stoklund Olesen4bc5e382011-01-13 21:28:52 +00001130 MBBI = MBB.getLastNonDebugInstr();
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +00001131 MachineOperand &JumpTarget = MBBI->getOperand(0);
1132 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
1133 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1134 } else if (RetOpcode == PPC::TCRETURNri) {
Jakob Stoklund Olesen4bc5e382011-01-13 21:28:52 +00001135 MBBI = MBB.getLastNonDebugInstr();
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +00001136 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1137 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
1138 } else if (RetOpcode == PPC::TCRETURNai) {
Jakob Stoklund Olesen4bc5e382011-01-13 21:28:52 +00001139 MBBI = MBB.getLastNonDebugInstr();
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +00001140 MachineOperand &JumpTarget = MBBI->getOperand(0);
1141 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
1142 } else if (RetOpcode == PPC::TCRETURNdi8) {
Jakob Stoklund Olesen4bc5e382011-01-13 21:28:52 +00001143 MBBI = MBB.getLastNonDebugInstr();
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +00001144 MachineOperand &JumpTarget = MBBI->getOperand(0);
1145 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
1146 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1147 } else if (RetOpcode == PPC::TCRETURNri8) {
Jakob Stoklund Olesen4bc5e382011-01-13 21:28:52 +00001148 MBBI = MBB.getLastNonDebugInstr();
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +00001149 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1150 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
1151 } else if (RetOpcode == PPC::TCRETURNai8) {
Jakob Stoklund Olesen4bc5e382011-01-13 21:28:52 +00001152 MBBI = MBB.getLastNonDebugInstr();
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +00001153 MachineOperand &JumpTarget = MBBI->getOperand(0);
1154 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
1155 }
1156}
Anton Korobeynikov14ee3442010-11-18 23:25:52 +00001157
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001158void
Anton Korobeynikov2f931282011-01-10 12:39:04 +00001159PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
Hal Finkelbb420f12013-03-15 05:06:04 +00001160 RegScavenger *) const {
Eric Christopherfc6de422014-08-05 02:39:49 +00001161 const PPCRegisterInfo *RegInfo =
Eric Christopher38522b82015-01-30 02:11:26 +00001162 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001163
1164 // Save and clear the LR state.
1165 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1166 unsigned LR = RegInfo->getRARegister();
1167 FI->setMustSaveLR(MustSaveLR(MF, LR));
Bill Schmidtc68c6df2013-02-24 17:34:50 +00001168 MachineRegisterInfo &MRI = MF.getRegInfo();
1169 MRI.setPhysRegUnused(LR);
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001170
1171 // Save R31 if necessary
1172 int FPSI = FI->getFramePointerSaveIndex();
1173 bool isPPC64 = Subtarget.isPPC64();
1174 bool isDarwinABI = Subtarget.isDarwinABI();
Hal Finkel3ee2af72014-07-18 23:29:49 +00001175 bool isPIC = MF.getTarget().getRelocationModel() == Reloc::PIC_;
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001176 MachineFrameInfo *MFI = MF.getFrameInfo();
1177
1178 // If the frame pointer save index hasn't been defined yet.
Anton Korobeynikov3eb4fed2010-12-18 19:53:14 +00001179 if (!FPSI && needsFP(MF)) {
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001180 // Find out what the fix offset of the frame pointer save area.
Eric Christopherdc3a8a42015-02-13 00:39:38 +00001181 int FPOffset = getFramePointerSaveOffset();
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001182 // Allocate the frame index for frame pointer save area.
Anton Korobeynikov2f931282011-01-10 12:39:04 +00001183 FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001184 // Save the result.
1185 FI->setFramePointerSaveIndex(FPSI);
1186 }
1187
Hal Finkela7c54e82013-07-17 00:45:52 +00001188 int BPSI = FI->getBasePointerSaveIndex();
1189 if (!BPSI && RegInfo->hasBasePointer(MF)) {
Hal Finkel3ee2af72014-07-18 23:29:49 +00001190 int BPOffset = getBasePointerSaveOffset(isPPC64, isDarwinABI, isPIC);
Hal Finkela7c54e82013-07-17 00:45:52 +00001191 // Allocate the frame index for the base pointer save area.
1192 BPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, BPOffset, true);
1193 // Save the result.
1194 FI->setBasePointerSaveIndex(BPSI);
1195 }
1196
Justin Hibbits654346e2015-01-10 01:57:21 +00001197 // Reserve stack space for the PIC Base register (R30).
1198 // Only used in SVR4 32-bit.
1199 if (FI->usesPICBase()) {
1200 int PBPSI = FI->getPICBasePointerSaveIndex();
1201 PBPSI = MFI->CreateFixedObject(4, -8, true);
1202 FI->setPICBasePointerSaveIndex(PBPSI);
1203 }
1204
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001205 // Reserve stack space to move the linkage area to in case of a tail call.
1206 int TCSPDelta = 0;
Nick Lewycky50f02cb2011-12-02 22:16:29 +00001207 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1208 (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
Anton Korobeynikov2f931282011-01-10 12:39:04 +00001209 MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001210 }
1211
Eric Christopherd1737492014-04-29 00:16:40 +00001212 // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the
Bill Schmidtc68c6df2013-02-24 17:34:50 +00001213 // function uses CR 2, 3, or 4.
Eric Christopherd1737492014-04-29 00:16:40 +00001214 if (!isPPC64 && !isDarwinABI &&
Bill Schmidtc68c6df2013-02-24 17:34:50 +00001215 (MRI.isPhysRegUsed(PPC::CR2) ||
1216 MRI.isPhysRegUsed(PPC::CR3) ||
1217 MRI.isPhysRegUsed(PPC::CR4))) {
1218 int FrameIdx = MFI->CreateFixedObject((uint64_t)4, (int64_t)-4, true);
1219 FI->setCRSpillFrameIndex(FrameIdx);
1220 }
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001221}
1222
Hal Finkel5a765fd2013-03-14 20:33:40 +00001223void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF,
Hal Finkelbb420f12013-03-15 05:06:04 +00001224 RegScavenger *RS) const {
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001225 // Early exit if not using the SVR4 ABI.
Hal Finkelbb420f12013-03-15 05:06:04 +00001226 if (!Subtarget.isSVR4ABI()) {
1227 addScavengingSpillSlot(MF, RS);
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001228 return;
Hal Finkelbb420f12013-03-15 05:06:04 +00001229 }
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001230
1231 // Get callee saved register information.
1232 MachineFrameInfo *FFI = MF.getFrameInfo();
1233 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo();
1234
1235 // Early exit if no callee saved registers are modified!
Anton Korobeynikov3eb4fed2010-12-18 19:53:14 +00001236 if (CSI.empty() && !needsFP(MF)) {
Hal Finkelbb420f12013-03-15 05:06:04 +00001237 addScavengingSpillSlot(MF, RS);
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001238 return;
1239 }
1240
1241 unsigned MinGPR = PPC::R31;
1242 unsigned MinG8R = PPC::X31;
1243 unsigned MinFPR = PPC::F31;
1244 unsigned MinVR = PPC::V31;
1245
1246 bool HasGPSaveArea = false;
1247 bool HasG8SaveArea = false;
1248 bool HasFPSaveArea = false;
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001249 bool HasVRSAVESaveArea = false;
1250 bool HasVRSaveArea = false;
1251
1252 SmallVector<CalleeSavedInfo, 18> GPRegs;
1253 SmallVector<CalleeSavedInfo, 18> G8Regs;
1254 SmallVector<CalleeSavedInfo, 18> FPRegs;
1255 SmallVector<CalleeSavedInfo, 18> VRegs;
1256
1257 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1258 unsigned Reg = CSI[i].getReg();
Craig Topperabadc662012-04-20 06:31:50 +00001259 if (PPC::GPRCRegClass.contains(Reg)) {
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001260 HasGPSaveArea = true;
1261
1262 GPRegs.push_back(CSI[i]);
1263
1264 if (Reg < MinGPR) {
1265 MinGPR = Reg;
1266 }
Craig Topperabadc662012-04-20 06:31:50 +00001267 } else if (PPC::G8RCRegClass.contains(Reg)) {
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001268 HasG8SaveArea = true;
1269
1270 G8Regs.push_back(CSI[i]);
1271
1272 if (Reg < MinG8R) {
1273 MinG8R = Reg;
1274 }
Craig Topperabadc662012-04-20 06:31:50 +00001275 } else if (PPC::F8RCRegClass.contains(Reg)) {
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001276 HasFPSaveArea = true;
1277
1278 FPRegs.push_back(CSI[i]);
1279
1280 if (Reg < MinFPR) {
1281 MinFPR = Reg;
1282 }
Craig Topperabadc662012-04-20 06:31:50 +00001283 } else if (PPC::CRBITRCRegClass.contains(Reg) ||
1284 PPC::CRRCRegClass.contains(Reg)) {
Roman Divackyc9e23d92012-09-12 14:47:47 +00001285 ; // do nothing, as we already know whether CRs are spilled
Craig Topperabadc662012-04-20 06:31:50 +00001286 } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001287 HasVRSAVESaveArea = true;
Craig Topperabadc662012-04-20 06:31:50 +00001288 } else if (PPC::VRRCRegClass.contains(Reg)) {
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001289 HasVRSaveArea = true;
1290
1291 VRegs.push_back(CSI[i]);
1292
1293 if (Reg < MinVR) {
1294 MinVR = Reg;
1295 }
1296 } else {
1297 llvm_unreachable("Unknown RegisterClass!");
1298 }
1299 }
1300
1301 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>();
Eric Christopher38522b82015-01-30 02:11:26 +00001302 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001303
1304 int64_t LowerBound = 0;
1305
1306 // Take into account stack space reserved for tail calls.
1307 int TCSPDelta = 0;
Nick Lewycky50f02cb2011-12-02 22:16:29 +00001308 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1309 (TCSPDelta = PFI->getTailCallSPDelta()) < 0) {
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001310 LowerBound = TCSPDelta;
1311 }
1312
1313 // The Floating-point register save area is right below the back chain word
1314 // of the previous stack frame.
1315 if (HasFPSaveArea) {
1316 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) {
1317 int FI = FPRegs[i].getFrameIdx();
1318
1319 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1320 }
1321
Hal Finkelfeea6532013-03-26 20:08:20 +00001322 LowerBound -= (31 - TRI->getEncodingValue(MinFPR) + 1) * 8;
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001323 }
1324
1325 // Check whether the frame pointer register is allocated. If so, make sure it
1326 // is spilled to the correct offset.
Anton Korobeynikov3eb4fed2010-12-18 19:53:14 +00001327 if (needsFP(MF)) {
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001328 HasGPSaveArea = true;
1329
1330 int FI = PFI->getFramePointerSaveIndex();
1331 assert(FI && "No Frame Pointer Save Slot!");
1332
1333 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1334 }
1335
Justin Hibbits654346e2015-01-10 01:57:21 +00001336 if (PFI->usesPICBase()) {
1337 HasGPSaveArea = true;
1338
1339 int FI = PFI->getPICBasePointerSaveIndex();
1340 assert(FI && "No PIC Base Pointer Save Slot!");
1341
1342 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1343 }
1344
Eric Christopherfc6de422014-08-05 02:39:49 +00001345 const PPCRegisterInfo *RegInfo =
Eric Christopher38522b82015-01-30 02:11:26 +00001346 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
Hal Finkela7c54e82013-07-17 00:45:52 +00001347 if (RegInfo->hasBasePointer(MF)) {
1348 HasGPSaveArea = true;
1349
1350 int FI = PFI->getBasePointerSaveIndex();
1351 assert(FI && "No Base Pointer Save Slot!");
1352
1353 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1354 }
1355
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001356 // General register save area starts right below the Floating-point
1357 // register save area.
1358 if (HasGPSaveArea || HasG8SaveArea) {
1359 // Move general register save area spill slots down, taking into account
1360 // the size of the Floating-point register save area.
1361 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) {
1362 int FI = GPRegs[i].getFrameIdx();
1363
1364 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1365 }
1366
1367 // Move general register save area spill slots down, taking into account
1368 // the size of the Floating-point register save area.
1369 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) {
1370 int FI = G8Regs[i].getFrameIdx();
1371
1372 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1373 }
1374
1375 unsigned MinReg =
Hal Finkelfeea6532013-03-26 20:08:20 +00001376 std::min<unsigned>(TRI->getEncodingValue(MinGPR),
1377 TRI->getEncodingValue(MinG8R));
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001378
1379 if (Subtarget.isPPC64()) {
1380 LowerBound -= (31 - MinReg + 1) * 8;
1381 } else {
1382 LowerBound -= (31 - MinReg + 1) * 4;
1383 }
1384 }
1385
Roman Divackyc9e23d92012-09-12 14:47:47 +00001386 // For 32-bit only, the CR save area is below the general register
1387 // save area. For 64-bit SVR4, the CR save area is addressed relative
1388 // to the stack pointer and hence does not need an adjustment here.
1389 // Only CR2 (the first nonvolatile spilled) has an associated frame
1390 // index so that we have a single uniform save area.
1391 if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) {
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001392 // Adjust the frame index of the CR spill slot.
1393 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1394 unsigned Reg = CSI[i].getReg();
1395
Roman Divackyc9e23d92012-09-12 14:47:47 +00001396 if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2)
Eric Christopherd1737492014-04-29 00:16:40 +00001397 // Leave Darwin logic as-is.
1398 || (!Subtarget.isSVR4ABI() &&
1399 (PPC::CRBITRCRegClass.contains(Reg) ||
1400 PPC::CRRCRegClass.contains(Reg)))) {
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001401 int FI = CSI[i].getFrameIdx();
1402
1403 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1404 }
1405 }
1406
1407 LowerBound -= 4; // The CR save area is always 4 bytes long.
1408 }
1409
1410 if (HasVRSAVESaveArea) {
1411 // FIXME SVR4: Is it actually possible to have multiple elements in CSI
1412 // which have the VRSAVE register class?
1413 // Adjust the frame index of the VRSAVE spill slot.
1414 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1415 unsigned Reg = CSI[i].getReg();
1416
Craig Topperabadc662012-04-20 06:31:50 +00001417 if (PPC::VRSAVERCRegClass.contains(Reg)) {
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001418 int FI = CSI[i].getFrameIdx();
1419
1420 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1421 }
1422 }
1423
1424 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long.
1425 }
1426
1427 if (HasVRSaveArea) {
1428 // Insert alignment padding, we need 16-byte alignment.
1429 LowerBound = (LowerBound - 15) & ~(15);
1430
1431 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) {
1432 int FI = VRegs[i].getFrameIdx();
1433
1434 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1435 }
1436 }
Hal Finkelbb420f12013-03-15 05:06:04 +00001437
1438 addScavengingSpillSlot(MF, RS);
1439}
1440
1441void
1442PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF,
1443 RegScavenger *RS) const {
1444 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
1445 // a large stack, which will require scavenging a register to materialize a
1446 // large offset.
1447
1448 // We need to have a scavenger spill slot for spills if the frame size is
1449 // large. In case there is no free register for large-offset addressing,
1450 // this slot is used for the necessary emergency spill. Also, we need the
1451 // slot for dynamic stack allocations.
1452
1453 // The scavenger might be invoked if the frame offset does not fit into
1454 // the 16-bit immediate. We don't know the complete frame size here
1455 // because we've not yet computed callee-saved register spills or the
1456 // needed alignment padding.
1457 unsigned StackSize = determineFrameLayout(MF, false, true);
1458 MachineFrameInfo *MFI = MF.getFrameInfo();
Hal Finkelcc1eeda2013-03-23 22:06:03 +00001459 if (MFI->hasVarSizedObjects() || spillsCR(MF) || spillsVRSAVE(MF) ||
1460 hasNonRISpills(MF) || (hasSpills(MF) && !isInt<16>(StackSize))) {
Hal Finkelbb420f12013-03-15 05:06:04 +00001461 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1462 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
1463 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
Hal Finkel9e331c22013-03-22 23:32:27 +00001464 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
Hal Finkelbb420f12013-03-15 05:06:04 +00001465 RC->getAlignment(),
1466 false));
Hal Finkel0dfbb052013-03-26 18:57:22 +00001467
Hal Finkel18607632013-07-18 04:28:21 +00001468 // Might we have over-aligned allocas?
1469 bool HasAlVars = MFI->hasVarSizedObjects() &&
1470 MFI->getMaxAlignment() > getStackAlignment();
1471
Hal Finkel0dfbb052013-03-26 18:57:22 +00001472 // These kinds of spills might need two registers.
Hal Finkel18607632013-07-18 04:28:21 +00001473 if (spillsCR(MF) || spillsVRSAVE(MF) || HasAlVars)
Hal Finkel0dfbb052013-03-26 18:57:22 +00001474 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1475 RC->getAlignment(),
1476 false));
1477
Hal Finkelbb420f12013-03-15 05:06:04 +00001478 }
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001479}
Roman Divackyc9e23d92012-09-12 14:47:47 +00001480
Eric Christopherd1737492014-04-29 00:16:40 +00001481bool
Roman Divackyc9e23d92012-09-12 14:47:47 +00001482PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
Eric Christopherd1737492014-04-29 00:16:40 +00001483 MachineBasicBlock::iterator MI,
1484 const std::vector<CalleeSavedInfo> &CSI,
1485 const TargetRegisterInfo *TRI) const {
Roman Divackyc9e23d92012-09-12 14:47:47 +00001486
1487 // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1488 // Return false otherwise to maintain pre-existing behavior.
1489 if (!Subtarget.isSVR4ABI())
1490 return false;
1491
1492 MachineFunction *MF = MBB.getParent();
1493 const PPCInstrInfo &TII =
Eric Christopher38522b82015-01-30 02:11:26 +00001494 *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo());
Roman Divackyc9e23d92012-09-12 14:47:47 +00001495 DebugLoc DL;
1496 bool CRSpilled = false;
Hal Finkel2f293912013-04-13 23:06:15 +00001497 MachineInstrBuilder CRMIB;
Eric Christopherd1737492014-04-29 00:16:40 +00001498
Roman Divackyc9e23d92012-09-12 14:47:47 +00001499 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1500 unsigned Reg = CSI[i].getReg();
Hal Finkelac1a24b2013-06-28 22:29:56 +00001501 // Only Darwin actually uses the VRSAVE register, but it can still appear
1502 // here if, for example, @llvm.eh.unwind.init() is used. If we're not on
1503 // Darwin, ignore it.
1504 if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
1505 continue;
1506
Roman Divackyc9e23d92012-09-12 14:47:47 +00001507 // CR2 through CR4 are the nonvolatile CR fields.
1508 bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4;
1509
Roman Divackyc9e23d92012-09-12 14:47:47 +00001510 // Add the callee-saved register as live-in; it's killed at the spill.
1511 MBB.addLiveIn(Reg);
1512
Hal Finkel2f293912013-04-13 23:06:15 +00001513 if (CRSpilled && IsCRField) {
1514 CRMIB.addReg(Reg, RegState::ImplicitKill);
1515 continue;
1516 }
1517
Roman Divackyc9e23d92012-09-12 14:47:47 +00001518 // Insert the spill to the stack frame.
1519 if (IsCRField) {
Hal Finkel67369882013-04-15 02:07:05 +00001520 PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
Roman Divackyc9e23d92012-09-12 14:47:47 +00001521 if (Subtarget.isPPC64()) {
Hal Finkel67369882013-04-15 02:07:05 +00001522 // The actual spill will happen at the start of the prologue.
1523 FuncInfo->addMustSaveCR(Reg);
Roman Divackyc9e23d92012-09-12 14:47:47 +00001524 } else {
Hal Finkel67369882013-04-15 02:07:05 +00001525 CRSpilled = true;
Bill Schmidtef3d1a22013-05-14 16:08:32 +00001526 FuncInfo->setSpillsCR();
Hal Finkel67369882013-04-15 02:07:05 +00001527
Eric Christopherd1737492014-04-29 00:16:40 +00001528 // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have
1529 // the same frame index in PPCRegisterInfo::hasReservedSpillSlot.
1530 CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12)
Hal Finkel2f293912013-04-13 23:06:15 +00001531 .addReg(Reg, RegState::ImplicitKill);
1532
Eric Christopherd1737492014-04-29 00:16:40 +00001533 MBB.insert(MI, CRMIB);
1534 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW))
1535 .addReg(PPC::R12,
1536 getKillRegState(true)),
1537 CSI[i].getFrameIdx()));
Roman Divackyc9e23d92012-09-12 14:47:47 +00001538 }
Roman Divackyc9e23d92012-09-12 14:47:47 +00001539 } else {
1540 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1541 TII.storeRegToStackSlot(MBB, MI, Reg, true,
Eric Christopherd1737492014-04-29 00:16:40 +00001542 CSI[i].getFrameIdx(), RC, TRI);
Roman Divackyc9e23d92012-09-12 14:47:47 +00001543 }
1544 }
1545 return true;
1546}
1547
1548static void
Hal Finkeld85a04b2013-04-13 08:09:20 +00001549restoreCRs(bool isPPC64, bool is31,
1550 bool CR2Spilled, bool CR3Spilled, bool CR4Spilled,
Eric Christopherd1737492014-04-29 00:16:40 +00001551 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
1552 const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) {
Roman Divackyc9e23d92012-09-12 14:47:47 +00001553
1554 MachineFunction *MF = MBB.getParent();
Eric Christophercccae792015-01-30 22:02:31 +00001555 const PPCInstrInfo &TII = *MF->getSubtarget<PPCSubtarget>().getInstrInfo();
Roman Divackyc9e23d92012-09-12 14:47:47 +00001556 DebugLoc DL;
1557 unsigned RestoreOp, MoveReg;
1558
Hal Finkel67369882013-04-15 02:07:05 +00001559 if (isPPC64)
1560 // This is handled during epilogue generation.
1561 return;
1562 else {
Roman Divackyc9e23d92012-09-12 14:47:47 +00001563 // 32-bit: FP-relative
1564 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ),
Eric Christopherd1737492014-04-29 00:16:40 +00001565 PPC::R12),
1566 CSI[CSIIndex].getFrameIdx()));
Ulrich Weigand49f487e2013-07-03 17:59:07 +00001567 RestoreOp = PPC::MTOCRF;
Roman Divackyc9e23d92012-09-12 14:47:47 +00001568 MoveReg = PPC::R12;
1569 }
Eric Christopherd1737492014-04-29 00:16:40 +00001570
Roman Divackyc9e23d92012-09-12 14:47:47 +00001571 if (CR2Spilled)
1572 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2)
Hal Finkel035b4822013-03-28 03:38:16 +00001573 .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled)));
Roman Divackyc9e23d92012-09-12 14:47:47 +00001574
1575 if (CR3Spilled)
1576 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3)
Hal Finkel035b4822013-03-28 03:38:16 +00001577 .addReg(MoveReg, getKillRegState(!CR4Spilled)));
Roman Divackyc9e23d92012-09-12 14:47:47 +00001578
1579 if (CR4Spilled)
1580 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4)
Hal Finkel035b4822013-03-28 03:38:16 +00001581 .addReg(MoveReg, getKillRegState(true)));
Roman Divackyc9e23d92012-09-12 14:47:47 +00001582}
1583
Eli Bendersky8da87162013-02-21 20:05:00 +00001584void PPCFrameLowering::
1585eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1586 MachineBasicBlock::iterator I) const {
Eric Christopher38522b82015-01-30 02:11:26 +00001587 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
Eli Bendersky8da87162013-02-21 20:05:00 +00001588 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1589 I->getOpcode() == PPC::ADJCALLSTACKUP) {
1590 // Add (actually subtract) back the amount the callee popped on return.
1591 if (int CalleeAmt = I->getOperand(1).getImm()) {
1592 bool is64Bit = Subtarget.isPPC64();
1593 CalleeAmt *= -1;
1594 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;
1595 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
1596 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;
1597 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
1598 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
1599 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
1600 MachineInstr *MI = I;
1601 DebugLoc dl = MI->getDebugLoc();
1602
1603 if (isInt<16>(CalleeAmt)) {
1604 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg)
1605 .addReg(StackReg, RegState::Kill)
1606 .addImm(CalleeAmt);
1607 } else {
1608 MachineBasicBlock::iterator MBBI = I;
1609 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
1610 .addImm(CalleeAmt >> 16);
1611 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
1612 .addReg(TmpReg, RegState::Kill)
1613 .addImm(CalleeAmt & 0xFFFF);
1614 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg)
1615 .addReg(StackReg, RegState::Kill)
1616 .addReg(TmpReg);
1617 }
1618 }
1619 }
1620 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
1621 MBB.erase(I);
1622}
1623
Eric Christopherd1737492014-04-29 00:16:40 +00001624bool
Roman Divackyc9e23d92012-09-12 14:47:47 +00001625PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
Eric Christopherd1737492014-04-29 00:16:40 +00001626 MachineBasicBlock::iterator MI,
1627 const std::vector<CalleeSavedInfo> &CSI,
1628 const TargetRegisterInfo *TRI) const {
Roman Divackyc9e23d92012-09-12 14:47:47 +00001629
1630 // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1631 // Return false otherwise to maintain pre-existing behavior.
1632 if (!Subtarget.isSVR4ABI())
1633 return false;
1634
1635 MachineFunction *MF = MBB.getParent();
1636 const PPCInstrInfo &TII =
Eric Christopher38522b82015-01-30 02:11:26 +00001637 *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo());
Roman Divackyc9e23d92012-09-12 14:47:47 +00001638 bool CR2Spilled = false;
1639 bool CR3Spilled = false;
1640 bool CR4Spilled = false;
1641 unsigned CSIIndex = 0;
1642
1643 // Initialize insertion-point logic; we will be restoring in reverse
1644 // order of spill.
1645 MachineBasicBlock::iterator I = MI, BeforeI = I;
1646 bool AtStart = I == MBB.begin();
1647
1648 if (!AtStart)
1649 --BeforeI;
1650
1651 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1652 unsigned Reg = CSI[i].getReg();
1653
Hal Finkelac1a24b2013-06-28 22:29:56 +00001654 // Only Darwin actually uses the VRSAVE register, but it can still appear
1655 // here if, for example, @llvm.eh.unwind.init() is used. If we're not on
1656 // Darwin, ignore it.
1657 if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
1658 continue;
1659
Roman Divackyc9e23d92012-09-12 14:47:47 +00001660 if (Reg == PPC::CR2) {
1661 CR2Spilled = true;
1662 // The spill slot is associated only with CR2, which is the
1663 // first nonvolatile spilled. Save it here.
1664 CSIIndex = i;
1665 continue;
1666 } else if (Reg == PPC::CR3) {
1667 CR3Spilled = true;
1668 continue;
1669 } else if (Reg == PPC::CR4) {
1670 CR4Spilled = true;
1671 continue;
1672 } else {
1673 // When we first encounter a non-CR register after seeing at
1674 // least one CR register, restore all spilled CRs together.
1675 if ((CR2Spilled || CR3Spilled || CR4Spilled)
Eric Christopherd1737492014-04-29 00:16:40 +00001676 && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
Hal Finkeld85a04b2013-04-13 08:09:20 +00001677 bool is31 = needsFP(*MF);
1678 restoreCRs(Subtarget.isPPC64(), is31,
1679 CR2Spilled, CR3Spilled, CR4Spilled,
Eric Christopherd1737492014-04-29 00:16:40 +00001680 MBB, I, CSI, CSIIndex);
1681 CR2Spilled = CR3Spilled = CR4Spilled = false;
Roman Divackyc9e23d92012-09-12 14:47:47 +00001682 }
1683
1684 // Default behavior for non-CR saves.
1685 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1686 TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(),
Eric Christopherd1737492014-04-29 00:16:40 +00001687 RC, TRI);
Roman Divackyc9e23d92012-09-12 14:47:47 +00001688 assert(I != MBB.begin() &&
Eric Christopherd1737492014-04-29 00:16:40 +00001689 "loadRegFromStackSlot didn't insert any code!");
Roman Divackyc9e23d92012-09-12 14:47:47 +00001690 }
1691
1692 // Insert in reverse order.
1693 if (AtStart)
1694 I = MBB.begin();
1695 else {
1696 I = BeforeI;
1697 ++I;
Eric Christopherd1737492014-04-29 00:16:40 +00001698 }
Roman Divackyc9e23d92012-09-12 14:47:47 +00001699 }
1700
1701 // If we haven't yet spilled the CRs, do so now.
Hal Finkeld85a04b2013-04-13 08:09:20 +00001702 if (CR2Spilled || CR3Spilled || CR4Spilled) {
Eric Christopherd1737492014-04-29 00:16:40 +00001703 bool is31 = needsFP(*MF);
Hal Finkeld85a04b2013-04-13 08:09:20 +00001704 restoreCRs(Subtarget.isPPC64(), is31, CR2Spilled, CR3Spilled, CR4Spilled,
Eric Christopherd1737492014-04-29 00:16:40 +00001705 MBB, I, CSI, CSIIndex);
Hal Finkeld85a04b2013-04-13 08:09:20 +00001706 }
Roman Divackyc9e23d92012-09-12 14:47:47 +00001707
1708 return true;
1709}