blob: da495642961761e47ac46ab1de152ac1c353664d [file] [log] [blame]
Akira Hatanaka71928e62012-04-17 18:03:21 +00001//===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file is part of the Mips Disassembler.
11//
12//===----------------------------------------------------------------------===//
13
14#include "Mips.h"
Akira Hatanaka9bf2b562012-07-09 18:46:47 +000015#include "MipsRegisterInfo.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000016#include "MipsSubtarget.h"
Akira Hatanaka71928e62012-04-17 18:03:21 +000017#include "llvm/MC/MCDisassembler.h"
Jim Grosbachecaef492012-08-14 19:06:05 +000018#include "llvm/MC/MCFixedLenDisassembler.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000019#include "llvm/MC/MCInst.h"
20#include "llvm/MC/MCSubtargetInfo.h"
21#include "llvm/Support/MathExtras.h"
Akira Hatanaka71928e62012-04-17 18:03:21 +000022#include "llvm/Support/MemoryObject.h"
23#include "llvm/Support/TargetRegistry.h"
Akira Hatanaka71928e62012-04-17 18:03:21 +000024
Akira Hatanaka71928e62012-04-17 18:03:21 +000025using namespace llvm;
26
27typedef MCDisassembler::DecodeStatus DecodeStatus;
28
Benjamin Kramercb3e98c2012-05-01 14:34:24 +000029namespace {
30
Akira Hatanaka9bf2b562012-07-09 18:46:47 +000031/// MipsDisassemblerBase - a disasembler class for Mips.
32class MipsDisassemblerBase : public MCDisassembler {
Akira Hatanaka71928e62012-04-17 18:03:21 +000033public:
34 /// Constructor - Initializes the disassembler.
35 ///
Akira Hatanaka9bf2b562012-07-09 18:46:47 +000036 MipsDisassemblerBase(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
37 bool bigEndian) :
Akira Hatanaka9bfa2e22013-08-28 00:55:15 +000038 MCDisassembler(STI), RegInfo(Info),
39 IsN64(STI.getFeatureBits() & Mips::FeatureN64), isBigEndian(bigEndian) {}
Akira Hatanaka71928e62012-04-17 18:03:21 +000040
Akira Hatanaka9bf2b562012-07-09 18:46:47 +000041 virtual ~MipsDisassemblerBase() {}
Akira Hatanaka71928e62012-04-17 18:03:21 +000042
Benjamin Kramerdcfd5b52013-08-03 22:16:16 +000043 const MCRegisterInfo *getRegInfo() const { return RegInfo.get(); }
Akira Hatanaka9bf2b562012-07-09 18:46:47 +000044
Akira Hatanaka9bfa2e22013-08-28 00:55:15 +000045 bool isN64() const { return IsN64; }
46
Akira Hatanaka71928e62012-04-17 18:03:21 +000047private:
Benjamin Kramerdcfd5b52013-08-03 22:16:16 +000048 OwningPtr<const MCRegisterInfo> RegInfo;
Akira Hatanaka9bfa2e22013-08-28 00:55:15 +000049 bool IsN64;
Akira Hatanaka9bf2b562012-07-09 18:46:47 +000050protected:
Akira Hatanaka71928e62012-04-17 18:03:21 +000051 bool isBigEndian;
52};
53
Akira Hatanaka9bf2b562012-07-09 18:46:47 +000054/// MipsDisassembler - a disasembler class for Mips32.
55class MipsDisassembler : public MipsDisassemblerBase {
Vladimir Medicdde3d582013-09-06 12:30:36 +000056 bool IsMicroMips;
Akira Hatanaka9bf2b562012-07-09 18:46:47 +000057public:
58 /// Constructor - Initializes the disassembler.
59 ///
60 MipsDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
61 bool bigEndian) :
Vladimir Medicdde3d582013-09-06 12:30:36 +000062 MipsDisassemblerBase(STI, Info, bigEndian) {
63 IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
64 }
Akira Hatanaka9bf2b562012-07-09 18:46:47 +000065
66 /// getInstruction - See MCDisassembler.
67 virtual DecodeStatus getInstruction(MCInst &instr,
68 uint64_t &size,
69 const MemoryObject &region,
70 uint64_t address,
71 raw_ostream &vStream,
72 raw_ostream &cStream) const;
73};
74
Akira Hatanaka71928e62012-04-17 18:03:21 +000075
76/// Mips64Disassembler - a disasembler class for Mips64.
Akira Hatanaka9bf2b562012-07-09 18:46:47 +000077class Mips64Disassembler : public MipsDisassemblerBase {
Akira Hatanaka71928e62012-04-17 18:03:21 +000078public:
79 /// Constructor - Initializes the disassembler.
80 ///
Akira Hatanaka9bf2b562012-07-09 18:46:47 +000081 Mips64Disassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
82 bool bigEndian) :
83 MipsDisassemblerBase(STI, Info, bigEndian) {}
Akira Hatanaka71928e62012-04-17 18:03:21 +000084
85 /// getInstruction - See MCDisassembler.
Akira Hatanaka9bf2b562012-07-09 18:46:47 +000086 virtual DecodeStatus getInstruction(MCInst &instr,
87 uint64_t &size,
88 const MemoryObject &region,
89 uint64_t address,
90 raw_ostream &vStream,
91 raw_ostream &cStream) const;
Akira Hatanaka71928e62012-04-17 18:03:21 +000092};
93
Benjamin Kramercb3e98c2012-05-01 14:34:24 +000094} // end anonymous namespace
95
Akira Hatanaka71928e62012-04-17 18:03:21 +000096// Forward declare these because the autogenerated code will reference them.
97// Definitions are further down.
Akira Hatanaka13e6ccf2013-08-06 23:08:38 +000098static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
99 unsigned RegNo,
100 uint64_t Address,
101 const void *Decoder);
Akira Hatanaka71928e62012-04-17 18:03:21 +0000102
Reed Kotlerec8a5492013-02-14 03:05:25 +0000103static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
104 unsigned RegNo,
105 uint64_t Address,
106 const void *Decoder);
107
Akira Hatanaka13e6ccf2013-08-06 23:08:38 +0000108static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
109 unsigned RegNo,
110 uint64_t Address,
111 const void *Decoder);
Akira Hatanaka71928e62012-04-17 18:03:21 +0000112
Akira Hatanaka9bfa2e22013-08-28 00:55:15 +0000113static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
114 unsigned Insn,
115 uint64_t Address,
116 const void *Decoder);
117
Akira Hatanaka654655f2013-08-14 00:53:38 +0000118static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
119 unsigned RegNo,
120 uint64_t Address,
121 const void *Decoder);
Akira Hatanakaecabd1a2012-09-27 02:01:10 +0000122
Akira Hatanaka71928e62012-04-17 18:03:21 +0000123static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
124 unsigned RegNo,
125 uint64_t Address,
126 const void *Decoder);
127
128static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
129 unsigned RegNo,
130 uint64_t Address,
131 const void *Decoder);
132
Akira Hatanaka14e31a22013-08-20 22:58:56 +0000133static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
134 unsigned RegNo,
135 uint64_t Address,
136 const void *Decoder);
137
Akira Hatanaka71928e62012-04-17 18:03:21 +0000138static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
139 unsigned RegNo,
140 uint64_t Address,
141 const void *Decoder);
142
Akira Hatanaka1fb1b8b2013-07-26 20:13:47 +0000143static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
144 unsigned RegNo,
145 uint64_t Address,
146 const void *Decoder);
147
Akira Hatanaka71928e62012-04-17 18:03:21 +0000148static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
149 unsigned Insn,
150 uint64_t Address,
151 const void *Decoder);
152
153static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
154 unsigned RegNo,
155 uint64_t Address,
156 const void *Decoder);
157
Akira Hatanaka00fcf2e2013-08-08 21:54:26 +0000158static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
159 unsigned RegNo,
160 uint64_t Address,
161 const void *Decoder);
Akira Hatanakaecabd1a2012-09-27 02:01:10 +0000162
Akira Hatanaka8002a3f2013-08-14 00:47:08 +0000163static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
164 unsigned RegNo,
165 uint64_t Address,
166 const void *Decoder);
Akira Hatanaka59bfaf72013-04-18 00:52:44 +0000167
Akira Hatanaka8002a3f2013-08-14 00:47:08 +0000168static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
169 unsigned RegNo,
170 uint64_t Address,
171 const void *Decoder);
Akira Hatanaka59bfaf72013-04-18 00:52:44 +0000172
Jack Carter3eb663b2013-09-26 00:09:46 +0000173static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
174 unsigned RegNo,
175 uint64_t Address,
176 const void *Decoder);
177
Jack Carter5dc8ac92013-09-25 23:50:44 +0000178static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
179 unsigned RegNo,
180 uint64_t Address,
181 const void *Decoder);
182
183static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
184 unsigned RegNo,
185 uint64_t Address,
186 const void *Decoder);
187
188static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
189 unsigned RegNo,
190 uint64_t Address,
191 const void *Decoder);
192
Matheus Almeidaa591fdc2013-10-21 12:26:50 +0000193static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
194 unsigned RegNo,
195 uint64_t Address,
196 const void *Decoder);
197
Akira Hatanaka71928e62012-04-17 18:03:21 +0000198static DecodeStatus DecodeBranchTarget(MCInst &Inst,
199 unsigned Offset,
200 uint64_t Address,
201 const void *Decoder);
202
Akira Hatanaka71928e62012-04-17 18:03:21 +0000203static DecodeStatus DecodeJumpTarget(MCInst &Inst,
204 unsigned Insn,
205 uint64_t Address,
206 const void *Decoder);
207
208static DecodeStatus DecodeMem(MCInst &Inst,
209 unsigned Insn,
210 uint64_t Address,
211 const void *Decoder);
212
Vladimir Medicdde3d582013-09-06 12:30:36 +0000213static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
214 unsigned Insn,
215 uint64_t Address,
216 const void *Decoder);
217
218static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
219 unsigned Insn,
220 uint64_t Address,
221 const void *Decoder);
222
Akira Hatanaka71928e62012-04-17 18:03:21 +0000223static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
224 uint64_t Address,
225 const void *Decoder);
226
227static DecodeStatus DecodeSimm16(MCInst &Inst,
228 unsigned Insn,
229 uint64_t Address,
230 const void *Decoder);
231
Akira Hatanaka71928e62012-04-17 18:03:21 +0000232static DecodeStatus DecodeInsSize(MCInst &Inst,
233 unsigned Insn,
234 uint64_t Address,
235 const void *Decoder);
236
237static DecodeStatus DecodeExtSize(MCInst &Inst,
238 unsigned Insn,
239 uint64_t Address,
240 const void *Decoder);
241
242namespace llvm {
243extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
244 TheMips64elTarget;
245}
246
247static MCDisassembler *createMipsDisassembler(
248 const Target &T,
249 const MCSubtargetInfo &STI) {
Akira Hatanaka9bf2b562012-07-09 18:46:47 +0000250 return new MipsDisassembler(STI, T.createMCRegInfo(""), true);
Akira Hatanaka71928e62012-04-17 18:03:21 +0000251}
252
253static MCDisassembler *createMipselDisassembler(
254 const Target &T,
255 const MCSubtargetInfo &STI) {
Akira Hatanaka9bf2b562012-07-09 18:46:47 +0000256 return new MipsDisassembler(STI, T.createMCRegInfo(""), false);
Akira Hatanaka71928e62012-04-17 18:03:21 +0000257}
258
259static MCDisassembler *createMips64Disassembler(
260 const Target &T,
261 const MCSubtargetInfo &STI) {
Akira Hatanaka9bf2b562012-07-09 18:46:47 +0000262 return new Mips64Disassembler(STI, T.createMCRegInfo(""), true);
Akira Hatanaka71928e62012-04-17 18:03:21 +0000263}
264
265static MCDisassembler *createMips64elDisassembler(
266 const Target &T,
267 const MCSubtargetInfo &STI) {
Akira Hatanaka9bf2b562012-07-09 18:46:47 +0000268 return new Mips64Disassembler(STI, T.createMCRegInfo(""), false);
Akira Hatanaka71928e62012-04-17 18:03:21 +0000269}
270
271extern "C" void LLVMInitializeMipsDisassembler() {
272 // Register the disassembler.
273 TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
274 createMipsDisassembler);
275 TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
276 createMipselDisassembler);
277 TargetRegistry::RegisterMCDisassembler(TheMips64Target,
278 createMips64Disassembler);
279 TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
280 createMips64elDisassembler);
281}
282
283
284#include "MipsGenDisassemblerTables.inc"
285
286 /// readInstruction - read four bytes from the MemoryObject
287 /// and return 32 bit word sorted according to the given endianess
288static DecodeStatus readInstruction32(const MemoryObject &region,
289 uint64_t address,
290 uint64_t &size,
291 uint32_t &insn,
Vladimir Medicdde3d582013-09-06 12:30:36 +0000292 bool isBigEndian,
293 bool IsMicroMips) {
Akira Hatanaka71928e62012-04-17 18:03:21 +0000294 uint8_t Bytes[4];
295
296 // We want to read exactly 4 Bytes of data.
Benjamin Kramer534d3a42013-05-24 10:54:58 +0000297 if (region.readBytes(address, 4, Bytes) == -1) {
Akira Hatanaka71928e62012-04-17 18:03:21 +0000298 size = 0;
299 return MCDisassembler::Fail;
300 }
301
302 if (isBigEndian) {
303 // Encoded as a big-endian 32-bit word in the stream.
304 insn = (Bytes[3] << 0) |
305 (Bytes[2] << 8) |
306 (Bytes[1] << 16) |
307 (Bytes[0] << 24);
308 }
309 else {
310 // Encoded as a small-endian 32-bit word in the stream.
Vladimir Medicdde3d582013-09-06 12:30:36 +0000311 // Little-endian byte ordering:
312 // mips32r2: 4 | 3 | 2 | 1
313 // microMIPS: 2 | 1 | 4 | 3
314 if (IsMicroMips) {
315 insn = (Bytes[2] << 0) |
316 (Bytes[3] << 8) |
317 (Bytes[0] << 16) |
318 (Bytes[1] << 24);
319 } else {
320 insn = (Bytes[0] << 0) |
321 (Bytes[1] << 8) |
322 (Bytes[2] << 16) |
323 (Bytes[3] << 24);
324 }
Akira Hatanaka71928e62012-04-17 18:03:21 +0000325 }
326
327 return MCDisassembler::Success;
328}
329
330DecodeStatus
331MipsDisassembler::getInstruction(MCInst &instr,
332 uint64_t &Size,
333 const MemoryObject &Region,
334 uint64_t Address,
335 raw_ostream &vStream,
336 raw_ostream &cStream) const {
337 uint32_t Insn;
338
339 DecodeStatus Result = readInstruction32(Region, Address, Size,
Vladimir Medicdde3d582013-09-06 12:30:36 +0000340 Insn, isBigEndian, IsMicroMips);
Akira Hatanaka71928e62012-04-17 18:03:21 +0000341 if (Result == MCDisassembler::Fail)
342 return MCDisassembler::Fail;
343
Vladimir Medicdde3d582013-09-06 12:30:36 +0000344 if (IsMicroMips) {
345 // Calling the auto-generated decoder function.
346 Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address,
347 this, STI);
348 if (Result != MCDisassembler::Fail) {
349 Size = 4;
350 return Result;
351 }
352 return MCDisassembler::Fail;
353 }
354
Akira Hatanaka71928e62012-04-17 18:03:21 +0000355 // Calling the auto-generated decoder function.
Jim Grosbachecaef492012-08-14 19:06:05 +0000356 Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
357 this, STI);
Akira Hatanaka71928e62012-04-17 18:03:21 +0000358 if (Result != MCDisassembler::Fail) {
359 Size = 4;
360 return Result;
361 }
362
363 return MCDisassembler::Fail;
364}
365
366DecodeStatus
367Mips64Disassembler::getInstruction(MCInst &instr,
368 uint64_t &Size,
369 const MemoryObject &Region,
370 uint64_t Address,
371 raw_ostream &vStream,
372 raw_ostream &cStream) const {
373 uint32_t Insn;
374
375 DecodeStatus Result = readInstruction32(Region, Address, Size,
Vladimir Medicdde3d582013-09-06 12:30:36 +0000376 Insn, isBigEndian, false);
Akira Hatanaka71928e62012-04-17 18:03:21 +0000377 if (Result == MCDisassembler::Fail)
378 return MCDisassembler::Fail;
379
380 // Calling the auto-generated decoder function.
Jim Grosbachecaef492012-08-14 19:06:05 +0000381 Result = decodeInstruction(DecoderTableMips6432, instr, Insn, Address,
382 this, STI);
Akira Hatanaka71928e62012-04-17 18:03:21 +0000383 if (Result != MCDisassembler::Fail) {
384 Size = 4;
385 return Result;
386 }
387 // If we fail to decode in Mips64 decoder space we can try in Mips32
Jim Grosbachecaef492012-08-14 19:06:05 +0000388 Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
389 this, STI);
Akira Hatanaka71928e62012-04-17 18:03:21 +0000390 if (Result != MCDisassembler::Fail) {
391 Size = 4;
392 return Result;
393 }
394
395 return MCDisassembler::Fail;
396}
397
Akira Hatanaka9bf2b562012-07-09 18:46:47 +0000398static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
399 const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
400 return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo);
401}
402
Reed Kotlerec8a5492013-02-14 03:05:25 +0000403static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
404 unsigned RegNo,
405 uint64_t Address,
406 const void *Decoder) {
407
408 return MCDisassembler::Fail;
409
410}
411
Akira Hatanaka13e6ccf2013-08-06 23:08:38 +0000412static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
413 unsigned RegNo,
414 uint64_t Address,
415 const void *Decoder) {
Akira Hatanaka71928e62012-04-17 18:03:21 +0000416
417 if (RegNo > 31)
418 return MCDisassembler::Fail;
419
Akira Hatanaka13e6ccf2013-08-06 23:08:38 +0000420 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
Akira Hatanaka9bf2b562012-07-09 18:46:47 +0000421 Inst.addOperand(MCOperand::CreateReg(Reg));
Akira Hatanaka71928e62012-04-17 18:03:21 +0000422 return MCDisassembler::Success;
423}
424
Akira Hatanaka13e6ccf2013-08-06 23:08:38 +0000425static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
426 unsigned RegNo,
427 uint64_t Address,
428 const void *Decoder) {
Akira Hatanaka71928e62012-04-17 18:03:21 +0000429 if (RegNo > 31)
430 return MCDisassembler::Fail;
Akira Hatanaka13e6ccf2013-08-06 23:08:38 +0000431 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
Akira Hatanaka9bf2b562012-07-09 18:46:47 +0000432 Inst.addOperand(MCOperand::CreateReg(Reg));
Akira Hatanaka71928e62012-04-17 18:03:21 +0000433 return MCDisassembler::Success;
434}
435
Akira Hatanaka9bfa2e22013-08-28 00:55:15 +0000436static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
437 unsigned RegNo,
438 uint64_t Address,
439 const void *Decoder) {
440 if (static_cast<const MipsDisassembler *>(Decoder)->isN64())
441 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
442
443 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
444}
445
Akira Hatanaka654655f2013-08-14 00:53:38 +0000446static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
447 unsigned RegNo,
448 uint64_t Address,
449 const void *Decoder) {
Akira Hatanaka13e6ccf2013-08-06 23:08:38 +0000450 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
Akira Hatanakaecabd1a2012-09-27 02:01:10 +0000451}
452
Akira Hatanaka71928e62012-04-17 18:03:21 +0000453static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
454 unsigned RegNo,
455 uint64_t Address,
456 const void *Decoder) {
457 if (RegNo > 31)
458 return MCDisassembler::Fail;
459
Akira Hatanaka9bf2b562012-07-09 18:46:47 +0000460 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
461 Inst.addOperand(MCOperand::CreateReg(Reg));
Akira Hatanaka71928e62012-04-17 18:03:21 +0000462 return MCDisassembler::Success;
463}
464
465static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
466 unsigned RegNo,
467 uint64_t Address,
468 const void *Decoder) {
469 if (RegNo > 31)
470 return MCDisassembler::Fail;
471
Akira Hatanaka9bf2b562012-07-09 18:46:47 +0000472 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
473 Inst.addOperand(MCOperand::CreateReg(Reg));
Akira Hatanaka71928e62012-04-17 18:03:21 +0000474 return MCDisassembler::Success;
475}
476
Akira Hatanaka14e31a22013-08-20 22:58:56 +0000477static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
478 unsigned RegNo,
479 uint64_t Address,
480 const void *Decoder) {
481 if (RegNo > 31)
482 return MCDisassembler::Fail;
483
484 unsigned Reg = getReg(Decoder, Mips::FGRH32RegClassID, RegNo);
485 Inst.addOperand(MCOperand::CreateReg(Reg));
486 return MCDisassembler::Success;
487}
488
Akira Hatanaka71928e62012-04-17 18:03:21 +0000489static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
490 unsigned RegNo,
491 uint64_t Address,
492 const void *Decoder) {
Chad Rosier253777f2013-06-26 22:23:32 +0000493 if (RegNo > 31)
494 return MCDisassembler::Fail;
495 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
496 Inst.addOperand(MCOperand::CreateReg(Reg));
Akira Hatanaka71928e62012-04-17 18:03:21 +0000497 return MCDisassembler::Success;
498}
499
Akira Hatanaka1fb1b8b2013-07-26 20:13:47 +0000500static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
501 unsigned RegNo,
502 uint64_t Address,
503 const void *Decoder) {
504 if (RegNo > 7)
505 return MCDisassembler::Fail;
506 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
507 Inst.addOperand(MCOperand::CreateReg(Reg));
508 return MCDisassembler::Success;
509}
510
Akira Hatanaka71928e62012-04-17 18:03:21 +0000511static DecodeStatus DecodeMem(MCInst &Inst,
512 unsigned Insn,
513 uint64_t Address,
514 const void *Decoder) {
515 int Offset = SignExtend32<16>(Insn & 0xffff);
Jim Grosbachecaef492012-08-14 19:06:05 +0000516 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
517 unsigned Base = fieldFromInstruction(Insn, 21, 5);
Akira Hatanaka9bf2b562012-07-09 18:46:47 +0000518
Akira Hatanaka13e6ccf2013-08-06 23:08:38 +0000519 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
520 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
Akira Hatanaka71928e62012-04-17 18:03:21 +0000521
522 if(Inst.getOpcode() == Mips::SC){
Akira Hatanaka9bf2b562012-07-09 18:46:47 +0000523 Inst.addOperand(MCOperand::CreateReg(Reg));
Akira Hatanaka71928e62012-04-17 18:03:21 +0000524 }
525
Akira Hatanaka9bf2b562012-07-09 18:46:47 +0000526 Inst.addOperand(MCOperand::CreateReg(Reg));
527 Inst.addOperand(MCOperand::CreateReg(Base));
Akira Hatanaka71928e62012-04-17 18:03:21 +0000528 Inst.addOperand(MCOperand::CreateImm(Offset));
529
530 return MCDisassembler::Success;
531}
532
Vladimir Medicdde3d582013-09-06 12:30:36 +0000533static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
534 unsigned Insn,
535 uint64_t Address,
536 const void *Decoder) {
537 int Offset = SignExtend32<12>(Insn & 0x0fff);
538 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
539 unsigned Base = fieldFromInstruction(Insn, 16, 5);
540
541 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
542 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
543
544 Inst.addOperand(MCOperand::CreateReg(Reg));
545 Inst.addOperand(MCOperand::CreateReg(Base));
546 Inst.addOperand(MCOperand::CreateImm(Offset));
547
548 return MCDisassembler::Success;
549}
550
551static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
552 unsigned Insn,
553 uint64_t Address,
554 const void *Decoder) {
555 int Offset = SignExtend32<16>(Insn & 0xffff);
556 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
557 unsigned Base = fieldFromInstruction(Insn, 16, 5);
558
559 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
560 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
561
562 Inst.addOperand(MCOperand::CreateReg(Reg));
563 Inst.addOperand(MCOperand::CreateReg(Base));
564 Inst.addOperand(MCOperand::CreateImm(Offset));
565
566 return MCDisassembler::Success;
567}
568
Akira Hatanaka71928e62012-04-17 18:03:21 +0000569static DecodeStatus DecodeFMem(MCInst &Inst,
570 unsigned Insn,
571 uint64_t Address,
572 const void *Decoder) {
573 int Offset = SignExtend32<16>(Insn & 0xffff);
Jim Grosbachecaef492012-08-14 19:06:05 +0000574 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
575 unsigned Base = fieldFromInstruction(Insn, 21, 5);
Akira Hatanaka71928e62012-04-17 18:03:21 +0000576
Akira Hatanaka9bf2b562012-07-09 18:46:47 +0000577 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
Akira Hatanaka13e6ccf2013-08-06 23:08:38 +0000578 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
Akira Hatanaka9bf2b562012-07-09 18:46:47 +0000579
580 Inst.addOperand(MCOperand::CreateReg(Reg));
581 Inst.addOperand(MCOperand::CreateReg(Base));
Akira Hatanaka71928e62012-04-17 18:03:21 +0000582 Inst.addOperand(MCOperand::CreateImm(Offset));
583
584 return MCDisassembler::Success;
585}
586
587
588static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
589 unsigned RegNo,
590 uint64_t Address,
591 const void *Decoder) {
592 // Currently only hardware register 29 is supported.
593 if (RegNo != 29)
594 return MCDisassembler::Fail;
595 Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
596 return MCDisassembler::Success;
597}
598
Akira Hatanaka71928e62012-04-17 18:03:21 +0000599static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
600 unsigned RegNo,
601 uint64_t Address,
602 const void *Decoder) {
Akira Hatanaka9bf2b562012-07-09 18:46:47 +0000603 if (RegNo > 30 || RegNo %2)
Akira Hatanaka71928e62012-04-17 18:03:21 +0000604 return MCDisassembler::Fail;
605
Akira Hatanaka9bf2b562012-07-09 18:46:47 +0000606 ;
607 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
608 Inst.addOperand(MCOperand::CreateReg(Reg));
Akira Hatanaka71928e62012-04-17 18:03:21 +0000609 return MCDisassembler::Success;
610}
611
Akira Hatanaka00fcf2e2013-08-08 21:54:26 +0000612static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
613 unsigned RegNo,
614 uint64_t Address,
615 const void *Decoder) {
Akira Hatanakaecabd1a2012-09-27 02:01:10 +0000616 if (RegNo >= 4)
617 return MCDisassembler::Fail;
618
Akira Hatanaka00fcf2e2013-08-08 21:54:26 +0000619 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
Akira Hatanakaecabd1a2012-09-27 02:01:10 +0000620 Inst.addOperand(MCOperand::CreateReg(Reg));
621 return MCDisassembler::Success;
622}
623
Akira Hatanaka8002a3f2013-08-14 00:47:08 +0000624static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
625 unsigned RegNo,
626 uint64_t Address,
627 const void *Decoder) {
Akira Hatanaka59bfaf72013-04-18 00:52:44 +0000628 if (RegNo >= 4)
629 return MCDisassembler::Fail;
630
Akira Hatanaka8002a3f2013-08-14 00:47:08 +0000631 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
Akira Hatanaka59bfaf72013-04-18 00:52:44 +0000632 Inst.addOperand(MCOperand::CreateReg(Reg));
633 return MCDisassembler::Success;
634}
635
Akira Hatanaka8002a3f2013-08-14 00:47:08 +0000636static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
637 unsigned RegNo,
638 uint64_t Address,
639 const void *Decoder) {
Akira Hatanaka59bfaf72013-04-18 00:52:44 +0000640 if (RegNo >= 4)
641 return MCDisassembler::Fail;
642
Akira Hatanaka8002a3f2013-08-14 00:47:08 +0000643 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
Akira Hatanaka59bfaf72013-04-18 00:52:44 +0000644 Inst.addOperand(MCOperand::CreateReg(Reg));
645 return MCDisassembler::Success;
646}
647
Jack Carter3eb663b2013-09-26 00:09:46 +0000648static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
649 unsigned RegNo,
650 uint64_t Address,
651 const void *Decoder) {
652 if (RegNo > 31)
653 return MCDisassembler::Fail;
654
655 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
656 Inst.addOperand(MCOperand::CreateReg(Reg));
657 return MCDisassembler::Success;
658}
659
Jack Carter5dc8ac92013-09-25 23:50:44 +0000660static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
661 unsigned RegNo,
662 uint64_t Address,
663 const void *Decoder) {
664 if (RegNo > 31)
665 return MCDisassembler::Fail;
666
667 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
668 Inst.addOperand(MCOperand::CreateReg(Reg));
669 return MCDisassembler::Success;
670}
671
672static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
673 unsigned RegNo,
674 uint64_t Address,
675 const void *Decoder) {
676 if (RegNo > 31)
677 return MCDisassembler::Fail;
678
679 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
680 Inst.addOperand(MCOperand::CreateReg(Reg));
681 return MCDisassembler::Success;
682}
683
684static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
685 unsigned RegNo,
686 uint64_t Address,
687 const void *Decoder) {
688 if (RegNo > 31)
689 return MCDisassembler::Fail;
690
691 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
692 Inst.addOperand(MCOperand::CreateReg(Reg));
693 return MCDisassembler::Success;
694}
695
Matheus Almeidaa591fdc2013-10-21 12:26:50 +0000696static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
697 unsigned RegNo,
698 uint64_t Address,
699 const void *Decoder) {
700 if (RegNo > 7)
701 return MCDisassembler::Fail;
702
703 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
704 Inst.addOperand(MCOperand::CreateReg(Reg));
705 return MCDisassembler::Success;
706}
707
Akira Hatanaka71928e62012-04-17 18:03:21 +0000708static DecodeStatus DecodeBranchTarget(MCInst &Inst,
709 unsigned Offset,
710 uint64_t Address,
711 const void *Decoder) {
712 unsigned BranchOffset = Offset & 0xffff;
713 BranchOffset = SignExtend32<18>(BranchOffset << 2) + 4;
714 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
715 return MCDisassembler::Success;
716}
717
Akira Hatanaka71928e62012-04-17 18:03:21 +0000718static DecodeStatus DecodeJumpTarget(MCInst &Inst,
719 unsigned Insn,
720 uint64_t Address,
721 const void *Decoder) {
722
Jim Grosbachecaef492012-08-14 19:06:05 +0000723 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
Akira Hatanaka71928e62012-04-17 18:03:21 +0000724 Inst.addOperand(MCOperand::CreateImm(JumpOffset));
725 return MCDisassembler::Success;
726}
727
728
729static DecodeStatus DecodeSimm16(MCInst &Inst,
730 unsigned Insn,
731 uint64_t Address,
732 const void *Decoder) {
733 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
734 return MCDisassembler::Success;
735}
736
737static DecodeStatus DecodeInsSize(MCInst &Inst,
738 unsigned Insn,
739 uint64_t Address,
740 const void *Decoder) {
741 // First we need to grab the pos(lsb) from MCInst.
742 int Pos = Inst.getOperand(2).getImm();
743 int Size = (int) Insn - Pos + 1;
744 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
745 return MCDisassembler::Success;
746}
747
748static DecodeStatus DecodeExtSize(MCInst &Inst,
749 unsigned Insn,
750 uint64_t Address,
751 const void *Decoder) {
752 int Size = (int) Insn + 1;
753 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
754 return MCDisassembler::Success;
755}