blob: 539373f7bdeb4e27faffcfb68135603cc5556ef5 [file] [log] [blame]
Matt Arsenaultfa5f7672016-09-14 15:19:03 +00001; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
Matt Arsenault7aad8fd2017-01-24 22:02:15 +00002; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
3; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=FUNC %s
Matt Arsenaultd0792852015-12-14 17:25:38 +00004
5declare i16 @llvm.bitreverse.i16(i16) #1
6declare i32 @llvm.bitreverse.i32(i32) #1
7declare i64 @llvm.bitreverse.i64(i64) #1
8
9declare <2 x i32> @llvm.bitreverse.v2i32(<2 x i32>) #1
10declare <4 x i32> @llvm.bitreverse.v4i32(<4 x i32>) #1
11
12declare <2 x i64> @llvm.bitreverse.v2i64(<2 x i64>) #1
13declare <4 x i64> @llvm.bitreverse.v4i64(<4 x i64>) #1
14
Matt Arsenaultd0792852015-12-14 17:25:38 +000015; FUNC-LABEL: {{^}}s_brev_i16:
Tom Stellard115a6152016-11-10 16:02:37 +000016; SI: s_brev_b32
Matt Arsenault3dbeefa2017-03-21 21:39:51 +000017define amdgpu_kernel void @s_brev_i16(i16 addrspace(1)* noalias %out, i16 %val) #0 {
Matt Arsenaultd0792852015-12-14 17:25:38 +000018 %brev = call i16 @llvm.bitreverse.i16(i16 %val) #1
19 store i16 %brev, i16 addrspace(1)* %out
20 ret void
21}
22
23; FUNC-LABEL: {{^}}v_brev_i16:
24; SI: v_bfrev_b32_e32
Matt Arsenault3dbeefa2017-03-21 21:39:51 +000025define amdgpu_kernel void @v_brev_i16(i16 addrspace(1)* noalias %out, i16 addrspace(1)* noalias %valptr) #0 {
Matt Arsenaultd0792852015-12-14 17:25:38 +000026 %val = load i16, i16 addrspace(1)* %valptr
27 %brev = call i16 @llvm.bitreverse.i16(i16 %val) #1
28 store i16 %brev, i16 addrspace(1)* %out
29 ret void
30}
31
32; FUNC-LABEL: {{^}}s_brev_i32:
33; SI: s_load_dword [[VAL:s[0-9]+]],
34; SI: s_brev_b32 [[SRESULT:s[0-9]+]], [[VAL]]
35; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]]
36; SI: buffer_store_dword [[VRESULT]],
37; SI: s_endpgm
Matt Arsenault3dbeefa2017-03-21 21:39:51 +000038define amdgpu_kernel void @s_brev_i32(i32 addrspace(1)* noalias %out, i32 %val) #0 {
Matt Arsenaultd0792852015-12-14 17:25:38 +000039 %brev = call i32 @llvm.bitreverse.i32(i32 %val) #1
40 store i32 %brev, i32 addrspace(1)* %out
41 ret void
42}
43
44; FUNC-LABEL: {{^}}v_brev_i32:
45; SI: buffer_load_dword [[VAL:v[0-9]+]],
46; SI: v_bfrev_b32_e32 [[RESULT:v[0-9]+]], [[VAL]]
47; SI: buffer_store_dword [[RESULT]],
48; SI: s_endpgm
Matt Arsenault3dbeefa2017-03-21 21:39:51 +000049define amdgpu_kernel void @v_brev_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) #0 {
Matt Arsenaultd0792852015-12-14 17:25:38 +000050 %val = load i32, i32 addrspace(1)* %valptr
51 %brev = call i32 @llvm.bitreverse.i32(i32 %val) #1
52 store i32 %brev, i32 addrspace(1)* %out
53 ret void
54}
55
56; FUNC-LABEL: {{^}}s_brev_v2i32:
57; SI: s_brev_b32
58; SI: s_brev_b32
Matt Arsenault3dbeefa2017-03-21 21:39:51 +000059define amdgpu_kernel void @s_brev_v2i32(<2 x i32> addrspace(1)* noalias %out, <2 x i32> %val) #0 {
Matt Arsenaultd0792852015-12-14 17:25:38 +000060 %brev = call <2 x i32> @llvm.bitreverse.v2i32(<2 x i32> %val) #1
61 store <2 x i32> %brev, <2 x i32> addrspace(1)* %out
62 ret void
63}
64
65; FUNC-LABEL: {{^}}v_brev_v2i32:
66; SI: v_bfrev_b32_e32
67; SI: v_bfrev_b32_e32
Matt Arsenault3dbeefa2017-03-21 21:39:51 +000068define amdgpu_kernel void @v_brev_v2i32(<2 x i32> addrspace(1)* noalias %out, <2 x i32> addrspace(1)* noalias %valptr) #0 {
Matt Arsenaultd0792852015-12-14 17:25:38 +000069 %val = load <2 x i32>, <2 x i32> addrspace(1)* %valptr
70 %brev = call <2 x i32> @llvm.bitreverse.v2i32(<2 x i32> %val) #1
71 store <2 x i32> %brev, <2 x i32> addrspace(1)* %out
72 ret void
73}
74
75; FUNC-LABEL: {{^}}s_brev_i64:
Matt Arsenault3dbeefa2017-03-21 21:39:51 +000076define amdgpu_kernel void @s_brev_i64(i64 addrspace(1)* noalias %out, i64 %val) #0 {
Matt Arsenaultd0792852015-12-14 17:25:38 +000077 %brev = call i64 @llvm.bitreverse.i64(i64 %val) #1
78 store i64 %brev, i64 addrspace(1)* %out
79 ret void
80}
81
82; FUNC-LABEL: {{^}}v_brev_i64:
Matt Arsenaultfa5f7672016-09-14 15:19:03 +000083; SI-NOT: v_or_b32_e64 v{{[0-9]+}}, 0, 0
Matt Arsenault3dbeefa2017-03-21 21:39:51 +000084define amdgpu_kernel void @v_brev_i64(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %valptr) #0 {
Matt Arsenaultd0792852015-12-14 17:25:38 +000085 %val = load i64, i64 addrspace(1)* %valptr
86 %brev = call i64 @llvm.bitreverse.i64(i64 %val) #1
87 store i64 %brev, i64 addrspace(1)* %out
88 ret void
89}
90
91; FUNC-LABEL: {{^}}s_brev_v2i64:
Matt Arsenault3dbeefa2017-03-21 21:39:51 +000092define amdgpu_kernel void @s_brev_v2i64(<2 x i64> addrspace(1)* noalias %out, <2 x i64> %val) #0 {
Matt Arsenaultd0792852015-12-14 17:25:38 +000093 %brev = call <2 x i64> @llvm.bitreverse.v2i64(<2 x i64> %val) #1
94 store <2 x i64> %brev, <2 x i64> addrspace(1)* %out
95 ret void
96}
97
98; FUNC-LABEL: {{^}}v_brev_v2i64:
Matt Arsenault3dbeefa2017-03-21 21:39:51 +000099define amdgpu_kernel void @v_brev_v2i64(<2 x i64> addrspace(1)* noalias %out, <2 x i64> addrspace(1)* noalias %valptr) #0 {
Matt Arsenaultd0792852015-12-14 17:25:38 +0000100 %val = load <2 x i64>, <2 x i64> addrspace(1)* %valptr
101 %brev = call <2 x i64> @llvm.bitreverse.v2i64(<2 x i64> %val) #1
102 store <2 x i64> %brev, <2 x i64> addrspace(1)* %out
103 ret void
104}
105
Matt Arsenaultd0792852015-12-14 17:25:38 +0000106attributes #0 = { nounwind }
107attributes #1 = { nounwind readnone }