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gerrit-public.fairphone.software / toolchain / llvm-project / 655822ab7ec7c5acb45f2bf18662b6cd603b0397 / . / llvm / lib / Target / ARM / ARM.td
blob: e02815ea3355c951b585c1cfcf11894c42eaed34 [file] [log] [blame]
Jia Liub22310f2012-02-18 12:03:15 +0000[diff] [blame]1//===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
Rafael Espindolaffdc24b2006-05-14 22:18:28 +0000[diff] [blame]2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattnerf3ebc3f2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
Rafael Espindolaffdc24b2006-05-14 22:18:28 +0000[diff] [blame]6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10//
11//===----------------------------------------------------------------------===//
12
13//===----------------------------------------------------------------------===//
14// Target-independent interfaces which we are implementing
15//===----------------------------------------------------------------------===//
16
Evan Cheng977e7be2008-11-24 07:34:46 +0000[diff] [blame]17include "llvm/Target/Target.td"
Rafael Espindolaffdc24b2006-05-14 22:18:28 +0000[diff] [blame]18
Evan Chengf2c26162011-07-07 08:26:46 +0000[diff] [blame]19//===----------------------------------------------------------------------===//
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]20// ARM Helper classes.
21//
22
23class ProcNoItin<string Name, list<SubtargetFeature> Features>
24 : Processor<Name, NoItineraries, Features>;
25
26class Architecture<string fname, string aname, list<SubtargetFeature> features >
27 : SubtargetFeature<fname, "ARMArch", aname,
28 !strconcat(aname, " architecture"), features>;
29
30//===----------------------------------------------------------------------===//
Evan Chengf2c26162011-07-07 08:26:46 +0000[diff] [blame]31// ARM Subtarget state.
32//
33
Evan Cheng1834f5d2011-07-07 19:05:12 +0000[diff] [blame]34def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
Evan Chengf2c26162011-07-07 08:26:46 +0000[diff] [blame]35 "Thumb mode">;
Jim Grosbach080fdf42010-09-30 01:57:53 +0000[diff] [blame]36
Eric Christopher824f42f2015-05-12 01:26:05 +0000[diff] [blame]37def ModeSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
38 "Use software floating point features.">;
39
Rafael Espindolaffdc24b2006-05-14 22:18:28 +0000[diff] [blame]40//===----------------------------------------------------------------------===//
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]41// ARM Subtarget features.
42//
43
Evan Cheng8b2bda02011-07-07 03:55:05 +0000[diff] [blame]44def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
Anton Korobeynikovb6f45382009-05-29 23:41:08 +0000[diff] [blame]45 "Enable VFP2 instructions">;
Evan Cheng8b2bda02011-07-07 03:55:05 +0000[diff] [blame]46def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
47 "Enable VFP3 instructions",
48 [FeatureVFP2]>;
49def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
50 "Enable NEON instructions",
51 [FeatureVFP3]>;
Evan Cheng2bd65362011-07-07 00:08:19 +0000[diff] [blame]52def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
Anton Korobeynikovb6f45382009-05-29 23:41:08 +0000[diff] [blame]53 "Enable Thumb2 instructions">;
Evan Cheng5190f092010-08-11 07:17:46 +0000[diff] [blame]54def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
Tim Northovera2292d02013-06-10 23:20:58 +0000[diff] [blame]55 "Does not support ARM mode execution",
56 [ModeThumb]>;
Anton Korobeynikov0a65a372010-03-14 18:42:38 +0000[diff] [blame]57def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
58 "Enable half-precision floating point">;
Bob Wilsone8a549c2012-09-29 21:43:49 +0000[diff] [blame]59def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true",
60 "Enable VFP4 instructions",
61 [FeatureVFP3, FeatureFP16]>;
Joey Goulyccd04892013-09-13 13:46:57 +0000[diff] [blame]62def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8",
Joey Goulyb1b0dd82013-06-27 11:49:26 +0000[diff] [blame]63 "true", "Enable ARMv8 FP",
64 [FeatureVFP4]>;
Oliver Stannard8addbf42015-12-01 10:23:06 +0000[diff] [blame]65def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
66 "Enable full half-precision floating point",
67 [FeatureFPARMv8]>;
Bob Wilsondd6eb5b2010-10-12 16:22:47 +0000[diff] [blame]68def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true",
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]69 "Restrict FP to 16 double registers">;
Jim Grosbach151cd8f2010-05-05 23:44:43 +0000[diff] [blame]70def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
71 "Enable divide instructions">;
Bob Wilsone8a549c2012-09-29 21:43:49 +0000[diff] [blame]72def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm",
73 "HasHardwareDivideInARM", "true",
74 "Enable divide instructions in ARM mode">;
Evan Cheng40921a42010-08-11 06:51:54 +0000[diff] [blame]75def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
Jim Grosbach151cd8f2010-05-05 23:44:43 +0000[diff] [blame]76 "Enable Thumb2 extract and pack instructions">;
Evan Cheng40921a42010-08-11 06:51:54 +0000[diff] [blame]77def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",
78 "Has data barrier (dmb / dsb) instructions">;
Bradley Smith4c21cba2016-01-15 10:23:46 +0000[diff] [blame]79def FeatureV7Clrex : SubtargetFeature<"v7clrex", "HasV7Clrex", "true",
80 "Has v7 clrex instruction">;
81def FeatureAcquireRelease : SubtargetFeature<"acquire-release",
82 "HasAcquireRelease", "true",
83 "Has v8 acquire/release (lda/ldaex etc) instructions">;
Evan Cheng58066e32010-07-13 19:21:50 +0000[diff] [blame]84def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
85 "FP compare + branch is slow">;
Jim Grosbach4d5dc3e2010-08-11 15:44:15 +0000[diff] [blame]86def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
87 "Floating point unit supports single precision only">;
Tim Northovercedd4812013-05-23 19:11:14 +0000[diff] [blame]88def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
89 "Enable support for Performance Monitor extensions">;
Tim Northoverc6047652013-04-10 12:08:35 +0000[diff] [blame]90def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",
91 "Enable support for TrustZone security extensions">;
Amara Emerson33089092013-09-19 11:59:01 +0000[diff] [blame]92def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
93 "Enable support for Cryptography extensions",
94 [FeatureNEON]>;
Bernard Ogdenee87e852013-10-29 09:47:35 +0000[diff] [blame]95def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
96 "Enable support for CRC instructions">;
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]97
Tim Northover13510302014-04-01 13:22:02 +0000[diff] [blame]98// Cyclone has preferred instructions for zeroing VFP registers, which can
99// execute in 0 cycles.
100def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
101 "Has zero-cycle zeroing instructions">;
102
Evan Cheng62c7b5b2010-12-05 22:04:16 +0000[diff] [blame]103// Some processors have FP multiply-accumulate instructions that don't
104// play nicely with other VFP / NEON instructions, and it's generally better
Jim Grosbacha43386b2010-03-25 23:11:16 +0000[diff] [blame]105// to just not use them.
Evan Cheng62c7b5b2010-12-05 22:04:16 +0000[diff] [blame]106def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
107 "Disable VFP / NEON MAC instructions">;
Evan Cheng38bf5ad2011-03-31 19:38:48 +0000[diff] [blame]108
109// Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
110def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
111 "HasVMLxForwarding", "true",
112 "Has multiplier accumulator forwarding">;
113
Jim Grosbach71fcb4f2010-03-25 23:47:34 +0000[diff] [blame]114// Some processors benefit from using NEON instructions for scalar
115// single-precision FP operations.
Jim Grosbach62800a92010-08-17 18:39:16 +0000[diff] [blame]116def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
117 "true",
118 "Use NEON for single precision FP">;
Jim Grosbach71fcb4f2010-03-25 23:47:34 +0000[diff] [blame]119
Evan Chengce8fb682010-08-09 18:35:19 +0000[diff] [blame]120// Disable 32-bit to 16-bit narrowing for experimentation.
121def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
122 "Prefer 32-bit Thumb instrs">;
Jim Grosbacha43386b2010-03-25 23:11:16 +0000[diff] [blame]123
Bob Wilsona2881ee2011-04-19 18:11:49 +0000[diff] [blame]124/// Some instructions update CPSR partially, which can add false dependency for
125/// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
126/// mapped to a separate physical register. Avoid partial CPSR update for these
127/// processors.
128def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
129 "AvoidCPSRPartialUpdate", "true",
130 "Avoid CPSR partial update for OOO execution">;
131
Evan Chengddc0cb62012-12-20 19:59:30 +0000[diff] [blame]132def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop",
133 "AvoidMOVsShifterOperand", "true",
134 "Avoid movs instructions with shifter operand">;
135
Evan Cheng65f9d192012-02-28 18:51:51 +0000[diff] [blame]136// Some processors perform return stack prediction. CodeGen should avoid issue
137// "normal" call instructions to callees which do not return.
138def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true",
139 "Has return address stack">;
140
Artyom Skrobov5a6e3942015-10-23 17:19:19 +0000[diff] [blame]141/// DSP extension.
142def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true",
Artyom Skrobovcf296442015-09-24 17:31:16 +0000[diff] [blame]143 "Supports DSP instructions in ARM and/or Thumb2">;
Jim Grosbachcf1464d2011-07-01 21:12:19 +0000[diff] [blame]144
Evan Cheng8740ee32010-11-03 06:34:55 +0000[diff] [blame]145// Multiprocessing extension.
146def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
147 "Supports Multiprocessing extension">;
Evan Cheng40921a42010-08-11 06:51:54 +0000[diff] [blame]148
Bradley Smith25219752013-11-01 13:27:35 +0000[diff] [blame]149// Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8).
150def FeatureVirtualization : SubtargetFeature<"virtualization",
151 "HasVirtualization", "true",
152 "Supports Virtualization extension",
153 [FeatureHWDiv, FeatureHWDivARM]>;
154
Amara Emerson330afb52013-09-23 14:26:15 +0000[diff] [blame]155// M-series ISA
156def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass",
James Molloy21efa7d2011-09-28 14:21:38 +0000[diff] [blame]157 "Is microcontroller profile ('M' series)">;
158
Amara Emerson330afb52013-09-23 14:26:15 +0000[diff] [blame]159// R-series ISA
160def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass",
161 "Is realtime profile ('R' series)">;
162
163// A-series ISA
164def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass",
165 "Is application profile ('A' series)">;
166
Eli Bendersky2e2ce492013-01-30 16:30:19 +0000[diff] [blame]167// Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
168// See ARMInstrInfo.td for details.
169def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
170 "NaCl trap">;
171
Akira Hatanaka2670f4a2015-07-28 22:44:28 +0000[diff] [blame]172def FeatureStrictAlign : SubtargetFeature<"strict-align",
173 "StrictAlign", "true",
174 "Disallow all unaligned memory "
175 "access">;
176
Akira Hatanaka1bc8af72015-07-07 06:54:42 +0000[diff] [blame]177def FeatureLongCalls : SubtargetFeature<"long-calls", "GenLongCalls", "true",
178 "Generate calls via indirect call "
179 "instructions">;
180
Akira Hatanaka28581522015-07-21 01:42:02 +0000[diff] [blame]181def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true",
182 "Reserve R9, making it unavailable as "
183 "GPR">;
184
Akira Hatanaka024d91a2015-07-16 00:58:23 +0000[diff] [blame]185def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true",
186 "Don't use movt/movw pairs for 32-bit "
187 "imms">;
188
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]189
190//===----------------------------------------------------------------------===//
191// ARM ISAa.
192//
193
Evan Cheng8b2bda02011-07-07 03:55:05 +0000[diff] [blame]194def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true",
Evan Chengf2c26162011-07-07 08:26:46 +0000[diff] [blame]195 "Support ARM v4T instructions">;
Evan Cheng8b2bda02011-07-07 03:55:05 +0000[diff] [blame]196def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true",
Evan Chengf2c26162011-07-07 08:26:46 +0000[diff] [blame]197 "Support ARM v5T instructions",
Evan Cheng8b2bda02011-07-07 03:55:05 +0000[diff] [blame]198 [HasV4TOps]>;
199def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true",
Evan Chengf2c26162011-07-07 08:26:46 +0000[diff] [blame]200 "Support ARM v5TE, v5TEj, and v5TExp instructions",
Evan Cheng8b2bda02011-07-07 03:55:05 +0000[diff] [blame]201 [HasV5TOps]>;
202def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true",
Evan Chengf2c26162011-07-07 08:26:46 +0000[diff] [blame]203 "Support ARM v6 instructions",
Evan Cheng8b2bda02011-07-07 03:55:05 +0000[diff] [blame]204 [HasV5TEOps]>;
Tim Northoverf86d1f02013-10-07 11:10:47 +0000[diff] [blame]205def HasV6MOps : SubtargetFeature<"v6m", "HasV6MOps", "true",
206 "Support ARM v6M instructions",
207 [HasV6Ops]>;
Bradley Smithe26f7992016-01-15 10:24:39 +0000[diff] [blame]208def HasV8MBaselineOps : SubtargetFeature<"v8m", "HasV8MBaselineOps", "true",
209 "Support ARM v8M Baseline instructions",
210 [HasV6MOps]>;
Renato Golin12350602015-03-17 11:55:28 +0000[diff] [blame]211def HasV6KOps : SubtargetFeature<"v6k", "HasV6KOps", "true",
212 "Support ARM v6k instructions",
213 [HasV6Ops]>;
Evan Cheng8b2bda02011-07-07 03:55:05 +0000[diff] [blame]214def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
Evan Chengf2c26162011-07-07 08:26:46 +0000[diff] [blame]215 "Support ARM v6t2 instructions",
Bradley Smithe26f7992016-01-15 10:24:39 +0000[diff] [blame]216 [HasV8MBaselineOps, HasV6KOps, FeatureThumb2]>;
Evan Cheng8b2bda02011-07-07 03:55:05 +0000[diff] [blame]217def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
Evan Chengf2c26162011-07-07 08:26:46 +0000[diff] [blame]218 "Support ARM v7 instructions",
Bradley Smith4c21cba2016-01-15 10:23:46 +0000[diff] [blame]219 [HasV6T2Ops, FeaturePerfMon,
220 FeatureV7Clrex]>;
Joey Goulyb3f550e2013-06-26 16:58:26 +0000[diff] [blame]221def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true",
222 "Support ARM v8 instructions",
Bradley Smith4c21cba2016-01-15 10:23:46 +0000[diff] [blame]223 [HasV7Ops, FeatureAcquireRelease]>;
Vladimir Sukharev2afdb322015-04-01 14:54:56 +0000[diff] [blame]224def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
Vladimir Sukharevc632cda2015-03-26 17:05:54 +0000[diff] [blame]225 "Support ARM v8.1a instructions",
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]226 [HasV8Ops]>;
Oliver Stannard8addbf42015-12-01 10:23:06 +0000[diff] [blame]227def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
228 "Support ARM v8.2a instructions",
229 [HasV8_1aOps]>;
Bradley Smithe26f7992016-01-15 10:24:39 +0000[diff] [blame]230def HasV8MMainlineOps : SubtargetFeature<"v8m.main", "HasV8MMainlineOps", "true",
231 "Support ARM v8M Mainline instructions",
232 [HasV7Ops]>;
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]233
Evan Cheng40921a42010-08-11 06:51:54 +0000[diff] [blame]234
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]235//===----------------------------------------------------------------------===//
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]236// ARM Processor subtarget features.
237//
238
239def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
240 "Cortex-A5 ARM processors", []>;
241def ProcA7 : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7",
242 "Cortex-A7 ARM processors", []>;
243def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
244 "Cortex-A8 ARM processors", []>;
245def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
246 "Cortex-A9 ARM processors", []>;
247def ProcA12 : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12",
248 "Cortex-A12 ARM processors", []>;
249def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
250 "Cortex-A15 ARM processors", []>;
251def ProcA17 : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17",
252 "Cortex-A17 ARM processors", []>;
Christof Douma8b5dc2c2015-12-02 11:53:44 +0000[diff] [blame]253def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
254 "Cortex-A35 ARM processors", []>;
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]255def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
256 "Cortex-A53 ARM processors", []>;
257def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
258 "Cortex-A57 ARM processors", []>;
259def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
260 "Cortex-A72 ARM processors", []>;
261
262def ProcKrait : SubtargetFeature<"krait", "ARMProcFamily", "Krait",
263 "Qualcomm ARM processors", []>;
264def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
265 "Swift ARM processors", []>;
266
MinSeong Kima7385eb2016-01-05 12:51:59 +0000[diff] [blame]267def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1",
268 "Samsung Exynos-M1 processors", []>;
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]269
270def ProcR4 : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4",
Bradley Smith4c21cba2016-01-15 10:23:46 +0000[diff] [blame]271 "Cortex-R4 ARM processors", []>;
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]272def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
273 "Cortex-R5 ARM processors", []>;
274def ProcR7 : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7",
275 "Cortex-R7 ARM processors", []>;
276
277
278//===----------------------------------------------------------------------===//
279// ARM schedules.
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]280//
281
Evan Cheng4e712de2009-06-19 01:51:50 +0000[diff] [blame]282include "ARMSchedule.td"
283
Richard Bartonc31078c2013-11-22 11:53:16 +0000[diff] [blame]284
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]285//===----------------------------------------------------------------------===//
286// ARM architectures
287//
Bob Wilsone8a549c2012-09-29 21:43:49 +0000[diff] [blame]288
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]289def ARMv2 : Architecture<"armv2", "ARMv2", []>;
Bernard Ogden4400cde2013-10-14 13:16:57 +0000[diff] [blame]290
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]291def ARMv2a : Architecture<"armv2a", "ARMv2a", []>;
Renato Golin16ea8ba2014-10-13 10:22:19 +0000[diff] [blame]292
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]293def ARMv3 : Architecture<"armv3", "ARMv3", []>;
Bernard Ogden4400cde2013-10-14 13:16:57 +0000[diff] [blame]294
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]295def ARMv3m : Architecture<"armv3m", "ARMv3m", []>;
Bernard Ogden53169762013-10-14 13:17:07 +0000[diff] [blame]296
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]297def ARMv4 : Architecture<"armv4", "ARMv4", []>;
Javed Absar5c5e3c52015-04-09 14:07:28 +0000[diff] [blame]298
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]299def ARMv4t : Architecture<"armv4t", "ARMv4t", [HasV4TOps]>;
Evan Chengbf407072010-09-10 01:29:16 +0000[diff] [blame]300
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]301def ARMv5t : Architecture<"armv5t", "ARMv5t", [HasV5TOps]>;
Ana Pazos93a07c22013-12-06 22:48:17 +0000[diff] [blame]302
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]303def ARMv5te : Architecture<"armv5te", "ARMv5te", [HasV5TEOps]>;
Rafael Espindolad89b16d2014-01-02 13:40:08 +0000[diff] [blame]304
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]305def ARMv5tej : Architecture<"armv5tej", "ARMv5tej", [HasV5TEOps]>;
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]306
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]307def ARMv6 : Architecture<"armv6", "ARMv6", [HasV6Ops]>;
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]308
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]309def ARMv6t2 : Architecture<"armv6t2", "ARMv6t2", [HasV6T2Ops,
Artyom Skrobovcf296442015-09-24 17:31:16 +0000[diff] [blame]310 FeatureDSP]>;
Anton Korobeynikovb6f45382009-05-29 23:41:08 +0000[diff] [blame]311
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]312def ARMv6k : Architecture<"armv6k", "ARMv6k", [HasV6KOps]>;
313
Artyom Skrobovf187a652015-11-16 14:05:32 +0000[diff] [blame]314def ARMv6kz : Architecture<"armv6kz", "ARMv6kz", [HasV6KOps,
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]315 FeatureTrustZone]>;
316
317def ARMv6m : Architecture<"armv6-m", "ARMv6m", [HasV6MOps,
318 FeatureNoARM,
319 FeatureDB,
320 FeatureMClass]>;
321
322def ARMv6sm : Architecture<"armv6s-m", "ARMv6sm", [HasV6MOps,
323 FeatureNoARM,
324 FeatureDB,
325 FeatureMClass]>;
326
327def ARMv7a : Architecture<"armv7-a", "ARMv7a", [HasV7Ops,
328 FeatureNEON,
329 FeatureDB,
330 FeatureDSP,
331 FeatureAClass]>;
332
333def ARMv7r : Architecture<"armv7-r", "ARMv7r", [HasV7Ops,
334 FeatureDB,
335 FeatureDSP,
336 FeatureHWDiv,
337 FeatureRClass]>;
338
339def ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops,
340 FeatureThumb2,
341 FeatureNoARM,
342 FeatureDB,
343 FeatureHWDiv,
344 FeatureMClass]>;
345
346def ARMv7em : Architecture<"armv7e-m", "ARMv7em", [HasV7Ops,
347 FeatureThumb2,
348 FeatureNoARM,
349 FeatureDB,
350 FeatureHWDiv,
351 FeatureMClass,
352 FeatureDSP,
353 FeatureT2XtPk]>;
354
355def ARMv8a : Architecture<"armv8-a", "ARMv8a", [HasV8Ops,
356 FeatureAClass,
357 FeatureDB,
358 FeatureFPARMv8,
359 FeatureNEON,
360 FeatureDSP,
361 FeatureTrustZone,
362 FeatureMP,
363 FeatureVirtualization,
364 FeatureCrypto,
365 FeatureCRC]>;
366
367def ARMv81a : Architecture<"armv8.1-a", "ARMv81a", [HasV8_1aOps,
368 FeatureAClass,
369 FeatureDB,
370 FeatureFPARMv8,
371 FeatureNEON,
372 FeatureDSP,
373 FeatureTrustZone,
374 FeatureMP,
375 FeatureVirtualization,
376 FeatureCrypto,
377 FeatureCRC]>;
378
Oliver Stannard46670712015-12-01 10:33:56 +0000[diff] [blame]379def ARMv82a : Architecture<"armv8.2-a", "ARMv82a", [HasV8_2aOps,
380 FeatureAClass,
381 FeatureDB,
382 FeatureFPARMv8,
383 FeatureNEON,
384 FeatureDSP,
385 FeatureTrustZone,
386 FeatureMP,
387 FeatureVirtualization,
388 FeatureCrypto,
389 FeatureCRC]>;
390
Bradley Smithe26f7992016-01-15 10:24:39 +0000[diff] [blame]391def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline",
392 [HasV8MBaselineOps,
393 FeatureNoARM,
394 FeatureDB,
395 FeatureHWDiv,
Bradley Smith433c22e2016-01-15 10:26:51 +0000[diff] [blame]396 FeatureV7Clrex,
Bradley Smithe26f7992016-01-15 10:24:39 +0000[diff] [blame]397 FeatureAcquireRelease,
398 FeatureMClass]>;
399
400def ARMv8mMainline : Architecture<"armv8-m.main", "ARMv8mMainline",
401 [HasV8MMainlineOps,
402 FeatureNoARM,
403 FeatureDB,
404 FeatureHWDiv,
405 FeatureAcquireRelease,
406 FeatureMClass]>;
407
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]408// Aliases
409def IWMMXT : Architecture<"iwmmxt", "ARMv5te", [ARMv5te]>;
410def IWMMXT2 : Architecture<"iwmmxt2", "ARMv5te", [ARMv5te]>;
411def XScale : Architecture<"xscale", "ARMv5te", [ARMv5te]>;
412def ARMv6j : Architecture<"armv6j", "ARMv7a", [ARMv6]>;
413def ARMv7k : Architecture<"armv7k", "ARMv7a", [ARMv7a]>;
414def ARMv7s : Architecture<"armv7s", "ARMv7a", [ARMv7a]>;
415
416
417//===----------------------------------------------------------------------===//
418// ARM processors
419//
420
421// Dummy CPU, used to target architectures
422def : ProcNoItin<"generic", []>;
423
424def : ProcNoItin<"arm8", [ARMv4]>;
425def : ProcNoItin<"arm810", [ARMv4]>;
426def : ProcNoItin<"strongarm", [ARMv4]>;
427def : ProcNoItin<"strongarm110", [ARMv4]>;
428def : ProcNoItin<"strongarm1100", [ARMv4]>;
429def : ProcNoItin<"strongarm1110", [ARMv4]>;
430
431def : ProcNoItin<"arm7tdmi", [ARMv4t]>;
432def : ProcNoItin<"arm7tdmi-s", [ARMv4t]>;
433def : ProcNoItin<"arm710t", [ARMv4t]>;
434def : ProcNoItin<"arm720t", [ARMv4t]>;
435def : ProcNoItin<"arm9", [ARMv4t]>;
436def : ProcNoItin<"arm9tdmi", [ARMv4t]>;
437def : ProcNoItin<"arm920", [ARMv4t]>;
438def : ProcNoItin<"arm920t", [ARMv4t]>;
439def : ProcNoItin<"arm922t", [ARMv4t]>;
440def : ProcNoItin<"arm940t", [ARMv4t]>;
441def : ProcNoItin<"ep9312", [ARMv4t]>;
442
443def : ProcNoItin<"arm10tdmi", [ARMv5t]>;
444def : ProcNoItin<"arm1020t", [ARMv5t]>;
445
446def : ProcNoItin<"arm9e", [ARMv5te]>;
447def : ProcNoItin<"arm926ej-s", [ARMv5te]>;
448def : ProcNoItin<"arm946e-s", [ARMv5te]>;
449def : ProcNoItin<"arm966e-s", [ARMv5te]>;
450def : ProcNoItin<"arm968e-s", [ARMv5te]>;
451def : ProcNoItin<"arm10e", [ARMv5te]>;
452def : ProcNoItin<"arm1020e", [ARMv5te]>;
453def : ProcNoItin<"arm1022e", [ARMv5te]>;
454def : ProcNoItin<"xscale", [ARMv5te]>;
455def : ProcNoItin<"iwmmxt", [ARMv5te]>;
456
457def : Processor<"arm1136j-s", ARMV6Itineraries, [ARMv6]>;
458def : Processor<"arm1136jf-s", ARMV6Itineraries, [ARMv6,
459 FeatureVFP2,
460 FeatureHasSlowFPVMLx]>;
461
462def : Processor<"cortex-m0", ARMV6Itineraries, [ARMv6m]>;
463def : Processor<"cortex-m0plus", ARMV6Itineraries, [ARMv6m]>;
464def : Processor<"cortex-m1", ARMV6Itineraries, [ARMv6m]>;
465def : Processor<"sc000", ARMV6Itineraries, [ARMv6m]>;
466
Artyom Skrobovf187a652015-11-16 14:05:32 +0000[diff] [blame]467def : Processor<"arm1176jz-s", ARMV6Itineraries, [ARMv6kz]>;
468def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ARMv6kz,
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]469 FeatureVFP2,
470 FeatureHasSlowFPVMLx]>;
471
472def : Processor<"mpcorenovfp", ARMV6Itineraries, [ARMv6k]>;
473def : Processor<"mpcore", ARMV6Itineraries, [ARMv6k,
474 FeatureVFP2,
475 FeatureHasSlowFPVMLx]>;
476
477def : Processor<"arm1156t2-s", ARMV6Itineraries, [ARMv6t2]>;
478def : Processor<"arm1156t2f-s", ARMV6Itineraries, [ARMv6t2,
479 FeatureVFP2,
480 FeatureHasSlowFPVMLx]>;
481
Quentin Colombet13cd5212012-11-29 19:48:01 +0000[diff] [blame]482// FIXME: A5 has currently the same Schedule model as A8
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]483def : ProcessorModel<"cortex-a5", CortexA8Model, [ARMv7a, ProcA5,
484 FeatureHasRAS,
485 FeatureTrustZone,
486 FeatureSlowFPBrcc,
487 FeatureHasSlowFPVMLx,
488 FeatureVMLxForwarding,
489 FeatureT2XtPk,
490 FeatureMP,
491 FeatureVFP4]>;
492
493def : ProcessorModel<"cortex-a7", CortexA8Model, [ARMv7a, ProcA7,
494 FeatureHasRAS,
495 FeatureTrustZone,
496 FeatureSlowFPBrcc,
497 FeatureHasSlowFPVMLx,
498 FeatureVMLxForwarding,
499 FeatureT2XtPk,
500 FeatureMP,
501 FeatureVFP4,
502 FeatureHWDiv,
503 FeatureHWDivARM,
504 FeatureVirtualization]>;
505
506def : ProcessorModel<"cortex-a8", CortexA8Model, [ARMv7a, ProcA8,
507 FeatureHasRAS,
508 FeatureTrustZone,
509 FeatureSlowFPBrcc,
510 FeatureHasSlowFPVMLx,
511 FeatureVMLxForwarding,
512 FeatureT2XtPk]>;
513
514def : ProcessorModel<"cortex-a9", CortexA9Model, [ARMv7a, ProcA9,
515 FeatureHasRAS,
516 FeatureTrustZone,
517 FeatureVMLxForwarding,
518 FeatureT2XtPk,
519 FeatureFP16,
520 FeatureAvoidPartialCPSR,
521 FeatureMP]>;
Richard Bartonc31078c2013-11-22 11:53:16 +0000[diff] [blame]522
523// FIXME: A12 has currently the same Schedule model as A9
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]524def : ProcessorModel<"cortex-a12", CortexA9Model, [ARMv7a, ProcA12,
525 FeatureHasRAS,
526 FeatureTrustZone,
527 FeatureVMLxForwarding,
528 FeatureT2XtPk,
529 FeatureVFP4,
530 FeatureHWDiv,
531 FeatureHWDivARM,
532 FeatureAvoidPartialCPSR,
533 FeatureVirtualization,
534 FeatureMP]>;
Richard Bartonc31078c2013-11-22 11:53:16 +0000[diff] [blame]535
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]536// FIXME: A15 has currently the same Schedule model as A9.
537def : ProcessorModel<"cortex-a15", CortexA9Model, [ARMv7a, ProcA15,
538 FeatureHasRAS,
539 FeatureTrustZone,
540 FeatureT2XtPk,
541 FeatureVFP4,
542 FeatureMP,
543 FeatureHWDiv,
544 FeatureHWDivARM,
545 FeatureAvoidPartialCPSR,
546 FeatureVirtualization]>;
Richard Bartonc31078c2013-11-22 11:53:16 +0000[diff] [blame]547
Renato Golin16ea8ba2014-10-13 10:22:19 +0000[diff] [blame]548// FIXME: A17 has currently the same Schedule model as A9
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]549def : ProcessorModel<"cortex-a17", CortexA9Model, [ARMv7a, ProcA17,
550 FeatureHasRAS,
551 FeatureTrustZone,
552 FeatureMP,
553 FeatureVMLxForwarding,
554 FeatureT2XtPk,
555 FeatureVFP4,
556 FeatureHWDiv,
557 FeatureHWDivARM,
558 FeatureAvoidPartialCPSR,
559 FeatureVirtualization]>;
Renato Golin16ea8ba2014-10-13 10:22:19 +0000[diff] [blame]560
Tim Northover13510302014-04-01 13:22:02 +0000[diff] [blame]561// FIXME: krait has currently the same Schedule model as A9
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]562// FIXME: krait has currently the same features as A9 plus VFP4 and hardware
563// division features.
564def : ProcessorModel<"krait", CortexA9Model, [ARMv7a, ProcKrait,
565 FeatureHasRAS,
566 FeatureVMLxForwarding,
567 FeatureT2XtPk,
568 FeatureFP16,
569 FeatureAvoidPartialCPSR,
570 FeatureVFP4,
571 FeatureHWDiv,
572 FeatureHWDivARM]>;
573
574def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift,
575 FeatureHasRAS,
576 FeatureNEONForFP,
577 FeatureT2XtPk,
578 FeatureVFP4,
579 FeatureMP,
580 FeatureHWDiv,
581 FeatureHWDivARM,
582 FeatureAvoidPartialCPSR,
583 FeatureAvoidMOVsShOp,
584 FeatureHasSlowFPVMLx]>;
Tim Northover13510302014-04-01 13:22:02 +0000[diff] [blame]585
Javed Absar5c5e3c52015-04-09 14:07:28 +0000[diff] [blame]586// FIXME: R4 has currently the same ProcessorModel as A8.
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]587def : ProcessorModel<"cortex-r4", CortexA8Model, [ARMv7r, ProcR4,
588 FeatureHasRAS,
589 FeatureAvoidPartialCPSR,
590 FeatureT2XtPk]>;
Javed Absar5c5e3c52015-04-09 14:07:28 +0000[diff] [blame]591
592// FIXME: R4F has currently the same ProcessorModel as A8.
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]593def : ProcessorModel<"cortex-r4f", CortexA8Model, [ARMv7r, ProcR4,
594 FeatureHasRAS,
595 FeatureSlowFPBrcc,
596 FeatureHasSlowFPVMLx,
597 FeatureVFP3,
598 FeatureD16,
599 FeatureAvoidPartialCPSR,
600 FeatureT2XtPk]>;
Javed Absar5c5e3c52015-04-09 14:07:28 +0000[diff] [blame]601
Quentin Colombetb1b66e72012-12-21 04:35:05 +0000[diff] [blame]602// FIXME: R5 has currently the same ProcessorModel as A8.
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]603def : ProcessorModel<"cortex-r5", CortexA8Model, [ARMv7r, ProcR5,
604 FeatureHasRAS,
605 FeatureVFP3,
606 FeatureD16,
607 FeatureSlowFPBrcc,
608 FeatureHWDivARM,
609 FeatureHasSlowFPVMLx,
610 FeatureAvoidPartialCPSR,
611 FeatureT2XtPk]>;
Evan Cheng49e02fc2010-08-11 06:30:38 +0000[diff] [blame]612
Bradley Smith26c99222015-02-18 10:33:30 +0000[diff] [blame]613// FIXME: R7 has currently the same ProcessorModel as A8 and is modelled as R5.
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]614def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7,
615 FeatureHasRAS,
616 FeatureVFP3,
617 FeatureVFPOnlySP,
618 FeatureD16,
Bradley Smithd5a1f472015-12-07 10:54:36 +0000[diff] [blame]619 FeatureFP16,
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]620 FeatureMP,
621 FeatureSlowFPBrcc,
622 FeatureHWDivARM,
623 FeatureHasSlowFPVMLx,
624 FeatureAvoidPartialCPSR,
625 FeatureT2XtPk]>;
Bradley Smith26c99222015-02-18 10:33:30 +0000[diff] [blame]626
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]627def : ProcNoItin<"cortex-m3", [ARMv7m]>;
628def : ProcNoItin<"sc300", [ARMv7m]>;
Evan Cheng8b2bda02011-07-07 03:55:05 +0000[diff] [blame]629
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]630def : ProcNoItin<"cortex-m4", [ARMv7em,
631 FeatureVFP4,
632 FeatureVFPOnlySP,
633 FeatureD16]>;
634
635def : ProcNoItin<"cortex-m7", [ARMv7em,
636 FeatureFPARMv8,
637 FeatureD16]>;
Oliver Stannard37e4daa2014-10-01 09:02:17 +0000[diff] [blame]638
Anton Korobeynikov0b91cc42009-05-23 19:51:43 +0000[diff] [blame]639
Christof Douma8b5dc2c2015-12-02 11:53:44 +0000[diff] [blame]640def : ProcNoItin<"cortex-a35", [ARMv8a, ProcA35,
641 FeatureHWDiv,
642 FeatureHWDivARM,
643 FeatureT2XtPk,
644 FeatureCrypto,
645 FeatureCRC]>;
646
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]647def : ProcNoItin<"cortex-a53", [ARMv8a, ProcA53,
648 FeatureHWDiv,
649 FeatureHWDivARM,
650 FeatureT2XtPk,
651 FeatureCrypto,
652 FeatureCRC]>;
Bob Wilsone8a549c2012-09-29 21:43:49 +0000[diff] [blame]653
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]654def : ProcNoItin<"cortex-a57", [ARMv8a, ProcA57,
655 FeatureHWDiv,
656 FeatureHWDivARM,
657 FeatureT2XtPk,
658 FeatureCrypto,
659 FeatureCRC]>;
660
661def : ProcNoItin<"cortex-a72", [ARMv8a, ProcA72,
662 FeatureHWDiv,
663 FeatureHWDivARM,
664 FeatureT2XtPk,
665 FeatureCrypto,
666 FeatureCRC]>;
Joey Goulyb3f550e2013-06-26 16:58:26 +0000[diff] [blame]667
Tim Northover13510302014-04-01 13:22:02 +0000[diff] [blame]668// Cyclone is very similar to swift
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]669def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift,
670 FeatureHasRAS,
671 FeatureNEONForFP,
672 FeatureT2XtPk,
673 FeatureVFP4,
674 FeatureMP,
675 FeatureHWDiv,
676 FeatureHWDivARM,
677 FeatureAvoidPartialCPSR,
678 FeatureAvoidMOVsShOp,
679 FeatureHasSlowFPVMLx,
680 FeatureCrypto,
681 FeatureZCZeroing]>;
682
MinSeong Kima7385eb2016-01-05 12:51:59 +0000[diff] [blame]683def : ProcNoItin<"exynos-m1", [ARMv8a, ProcExynosM1,
684 FeatureHWDiv,
685 FeatureHWDivARM,
686 FeatureT2XtPk,
687 FeatureCrypto,
688 FeatureCRC]>;
Ana Pazos93a07c22013-12-06 22:48:17 +0000[diff] [blame]689
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]690//===----------------------------------------------------------------------===//
Rafael Espindolaffdc24b2006-05-14 22:18:28 +0000[diff] [blame]691// Register File Description
692//===----------------------------------------------------------------------===//
693
694include "ARMRegisterInfo.td"
695
Bob Wilsona4c22902009-04-17 19:07:39 +0000[diff] [blame]696include "ARMCallingConv.td"
697
Rafael Espindolaffdc24b2006-05-14 22:18:28 +0000[diff] [blame]698//===----------------------------------------------------------------------===//
699// Instruction Descriptions
700//===----------------------------------------------------------------------===//
701
702include "ARMInstrInfo.td"
703
Jakob Stoklund Olesenb93331f2010-04-05 03:10:20 +0000[diff] [blame]704def ARMInstrInfo : InstrInfo;
Rafael Espindolaffdc24b2006-05-14 22:18:28 +0000[diff] [blame]705
706//===----------------------------------------------------------------------===//
707// Declare the target which we are implementing
708//===----------------------------------------------------------------------===//
709
Akira Hatanakaee974752015-03-27 23:41:42 +0000[diff] [blame]710def ARMAsmWriter : AsmWriter {
711 string AsmWriterClassName = "InstPrinter";
712 int PassSubtarget = 1;
713 int Variant = 0;
714 bit isMCAsmWriter = 1;
715}
716
Colin LeMahieu8a0453e2015-11-09 00:31:07 +0000[diff] [blame]717def ARMAsmParserVariant : AsmParserVariant {
718 int Variant = 0;
719 string Name = "ARM";
720 string BreakCharacters = ".";
721}
722
Rafael Espindolaffdc24b2006-05-14 22:18:28 +0000[diff] [blame]723def ARM : Target {
Rafael Espindolaffdc24b2006-05-14 22:18:28 +0000[diff] [blame]724 // Pull in Instruction Info:
725 let InstructionSet = ARMInstrInfo;
Akira Hatanakaee974752015-03-27 23:41:42 +0000[diff] [blame]726 let AssemblyWriters = [ARMAsmWriter];
Colin LeMahieu8a0453e2015-11-09 00:31:07 +0000[diff] [blame]727 let AssemblyParserVariants = [ARMAsmParserVariant];
Rafael Espindolaffdc24b2006-05-14 22:18:28 +0000[diff] [blame]728}