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Quentin Colombet2ad1f852016-02-11 17:44:59 +00001//===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.cpp - MIBuilder--*- C++ -*-==//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9/// \file
10/// This file implements the MachineIRBuidler class.
11//===----------------------------------------------------------------------===//
12#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
13
14#include "llvm/CodeGen/MachineFunction.h"
15#include "llvm/CodeGen/MachineInstr.h"
16#include "llvm/CodeGen/MachineInstrBuilder.h"
Tim Northover0f140c72016-09-09 11:46:34 +000017#include "llvm/CodeGen/MachineRegisterInfo.h"
Tim Northover09aac4a2017-01-26 23:39:14 +000018#include "llvm/IR/DebugInfo.h"
Quentin Colombet2ad1f852016-02-11 17:44:59 +000019#include "llvm/Target/TargetInstrInfo.h"
Quentin Colombet8fd67182016-02-11 21:16:56 +000020#include "llvm/Target/TargetOpcodes.h"
Quentin Colombet2ad1f852016-02-11 17:44:59 +000021#include "llvm/Target/TargetSubtargetInfo.h"
22
23using namespace llvm;
24
Quentin Colombet000b5802016-03-11 17:27:51 +000025void MachineIRBuilder::setMF(MachineFunction &MF) {
Quentin Colombet2ad1f852016-02-11 17:44:59 +000026 this->MF = &MF;
27 this->MBB = nullptr;
Tim Northover0f140c72016-09-09 11:46:34 +000028 this->MRI = &MF.getRegInfo();
Quentin Colombet2ad1f852016-02-11 17:44:59 +000029 this->TII = MF.getSubtarget().getInstrInfo();
30 this->DL = DebugLoc();
Tim Northover05cc4852016-12-07 21:05:38 +000031 this->II = MachineBasicBlock::iterator();
Tim Northover438c77c2016-08-25 17:37:32 +000032 this->InsertedInstr = nullptr;
Quentin Colombet2ad1f852016-02-11 17:44:59 +000033}
34
Tim Northover05cc4852016-12-07 21:05:38 +000035void MachineIRBuilder::setMBB(MachineBasicBlock &MBB) {
Quentin Colombet2ad1f852016-02-11 17:44:59 +000036 this->MBB = &MBB;
Tim Northover05cc4852016-12-07 21:05:38 +000037 this->II = MBB.end();
Quentin Colombet2ad1f852016-02-11 17:44:59 +000038 assert(&getMF() == MBB.getParent() &&
39 "Basic block is in a different function");
40}
41
Tim Northover05cc4852016-12-07 21:05:38 +000042void MachineIRBuilder::setInstr(MachineInstr &MI) {
Quentin Colombet2ad1f852016-02-11 17:44:59 +000043 assert(MI.getParent() && "Instruction is not part of a basic block");
Quentin Colombet91ebd712016-03-11 17:27:47 +000044 setMBB(*MI.getParent());
Tim Northover05cc4852016-12-07 21:05:38 +000045 this->II = MI.getIterator();
Quentin Colombet2ad1f852016-02-11 17:44:59 +000046}
47
Tim Northover05cc4852016-12-07 21:05:38 +000048void MachineIRBuilder::setInsertPt(MachineBasicBlock &MBB,
49 MachineBasicBlock::iterator II) {
50 assert(MBB.getParent() == &getMF() &&
51 "Basic block is in a different function");
52 this->MBB = &MBB;
53 this->II = II;
Quentin Colombet2ad1f852016-02-11 17:44:59 +000054}
55
Tim Northover438c77c2016-08-25 17:37:32 +000056void MachineIRBuilder::recordInsertions(
57 std::function<void(MachineInstr *)> Inserted) {
Benjamin Kramer061f4a52017-01-13 14:39:03 +000058 InsertedInstr = std::move(Inserted);
Tim Northover438c77c2016-08-25 17:37:32 +000059}
60
61void MachineIRBuilder::stopRecordingInsertions() {
62 InsertedInstr = nullptr;
63}
64
Quentin Colombetf9b49342016-03-11 17:27:58 +000065//------------------------------------------------------------------------------
66// Build instruction variants.
67//------------------------------------------------------------------------------
Tim Northovercc5f7622016-07-26 16:45:26 +000068
Tim Northover0f140c72016-09-09 11:46:34 +000069MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opcode) {
Tim Northovera5e38fa2016-09-22 13:49:25 +000070 return insertInstr(buildInstrNoInsert(Opcode));
71}
72
73MachineInstrBuilder MachineIRBuilder::buildInstrNoInsert(unsigned Opcode) {
Tim Northovera51575f2016-07-29 17:43:52 +000074 MachineInstrBuilder MIB = BuildMI(getMF(), DL, getTII().get(Opcode));
Tim Northovera5e38fa2016-09-22 13:49:25 +000075 return MIB;
76}
77
78
79MachineInstrBuilder MachineIRBuilder::insertInstr(MachineInstrBuilder MIB) {
Tim Northovera51575f2016-07-29 17:43:52 +000080 getMBB().insert(getInsertPt(), MIB);
Tim Northover438c77c2016-08-25 17:37:32 +000081 if (InsertedInstr)
82 InsertedInstr(MIB);
Tim Northovera51575f2016-07-29 17:43:52 +000083 return MIB;
Quentin Colombet74d7d2f2016-02-11 18:53:28 +000084}
85
Tim Northover09aac4a2017-01-26 23:39:14 +000086MachineInstrBuilder MachineIRBuilder::buildDirectDbgValue(
87 unsigned Reg, const MDNode *Variable, const MDNode *Expr) {
88 assert(isa<DILocalVariable>(Variable) && "not a variable");
89 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
90 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
91 "Expected inlined-at fields to agree");
92 return buildInstr(TargetOpcode::DBG_VALUE)
93 .addReg(Reg, RegState::Debug)
94 .addReg(0, RegState::Debug)
95 .addMetadata(Variable)
96 .addMetadata(Expr);
97}
98
99MachineInstrBuilder MachineIRBuilder::buildIndirectDbgValue(
100 unsigned Reg, unsigned Offset, const MDNode *Variable, const MDNode *Expr) {
101 assert(isa<DILocalVariable>(Variable) && "not a variable");
102 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
103 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
104 "Expected inlined-at fields to agree");
105 return buildInstr(TargetOpcode::DBG_VALUE)
106 .addReg(Reg, RegState::Debug)
107 .addImm(Offset)
108 .addMetadata(Variable)
109 .addMetadata(Expr);
110}
111
112MachineInstrBuilder MachineIRBuilder::buildFIDbgValue(int FI,
113 const MDNode *Variable,
114 const MDNode *Expr) {
115 assert(isa<DILocalVariable>(Variable) && "not a variable");
116 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
117 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
118 "Expected inlined-at fields to agree");
119 return buildInstr(TargetOpcode::DBG_VALUE)
120 .addFrameIndex(FI)
121 .addImm(0)
122 .addMetadata(Variable)
123 .addMetadata(Expr);
124}
125
126MachineInstrBuilder MachineIRBuilder::buildConstDbgValue(const Constant &C,
127 unsigned Offset,
128 const MDNode *Variable,
129 const MDNode *Expr) {
130 assert(isa<DILocalVariable>(Variable) && "not a variable");
131 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
132 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
133 "Expected inlined-at fields to agree");
134 auto MIB = buildInstr(TargetOpcode::DBG_VALUE);
135 if (auto *CI = dyn_cast<ConstantInt>(&C)) {
136 if (CI->getBitWidth() > 64)
137 MIB.addCImm(CI);
138 else
139 MIB.addImm(CI->getZExtValue());
Ahmed Bougacha4826bae2017-03-07 20:34:20 +0000140 } else if (auto *CFP = dyn_cast<ConstantFP>(&C)) {
Ahmed Bougachaadce3ee2017-03-07 20:52:57 +0000141 MIB.addFPImm(CFP);
Ahmed Bougacha4826bae2017-03-07 20:34:20 +0000142 } else {
143 // Insert %noreg if we didn't find a usable constant and had to drop it.
144 MIB.addReg(0U);
145 }
Tim Northover09aac4a2017-01-26 23:39:14 +0000146
147 return MIB.addImm(Offset).addMetadata(Variable).addMetadata(Expr);
148}
149
Tim Northover0f140c72016-09-09 11:46:34 +0000150MachineInstrBuilder MachineIRBuilder::buildFrameIndex(unsigned Res, int Idx) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000151 assert(MRI->getType(Res).isPointer() && "invalid operand type");
Tim Northover0f140c72016-09-09 11:46:34 +0000152 return buildInstr(TargetOpcode::G_FRAME_INDEX)
Tim Northovera51575f2016-07-29 17:43:52 +0000153 .addDef(Res)
154 .addFrameIndex(Idx);
Tim Northoverbd505462016-07-22 16:59:52 +0000155}
Tim Northover33b07d62016-07-22 20:03:43 +0000156
Tim Northover032548f2016-09-12 12:10:41 +0000157MachineInstrBuilder MachineIRBuilder::buildGlobalValue(unsigned Res,
158 const GlobalValue *GV) {
159 assert(MRI->getType(Res).isPointer() && "invalid operand type");
160 assert(MRI->getType(Res).getAddressSpace() ==
161 GV->getType()->getAddressSpace() &&
162 "address space mismatch");
163
164 return buildInstr(TargetOpcode::G_GLOBAL_VALUE)
165 .addDef(Res)
166 .addGlobalAddress(GV);
167}
168
Tim Northover0f140c72016-09-09 11:46:34 +0000169MachineInstrBuilder MachineIRBuilder::buildAdd(unsigned Res, unsigned Op0,
170 unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000171 assert((MRI->getType(Res).isScalar() || MRI->getType(Res).isVector()) &&
172 "invalid operand type");
173 assert(MRI->getType(Res) == MRI->getType(Op0) &&
174 MRI->getType(Res) == MRI->getType(Op1) && "type mismatch");
175
Tim Northover0f140c72016-09-09 11:46:34 +0000176 return buildInstr(TargetOpcode::G_ADD)
Tim Northovera51575f2016-07-29 17:43:52 +0000177 .addDef(Res)
178 .addUse(Op0)
179 .addUse(Op1);
Tim Northover33b07d62016-07-22 20:03:43 +0000180}
181
Tim Northovera7653b32016-09-12 11:20:22 +0000182MachineInstrBuilder MachineIRBuilder::buildGEP(unsigned Res, unsigned Op0,
183 unsigned Op1) {
184 assert(MRI->getType(Res).isPointer() &&
185 MRI->getType(Res) == MRI->getType(Op0) && "type mismatch");
186 assert(MRI->getType(Op1).isScalar() && "invalid offset type");
187
188 return buildInstr(TargetOpcode::G_GEP)
189 .addDef(Res)
190 .addUse(Op0)
191 .addUse(Op1);
192}
193
Daniel Sanders4e523662017-06-13 23:42:32 +0000194Optional<MachineInstrBuilder>
195MachineIRBuilder::materializeGEP(unsigned &Res, unsigned Op0,
196 const LLT &ValueTy, uint64_t Value) {
197 assert(Res == 0 && "Res is a result argument");
198 assert(ValueTy.isScalar() && "invalid offset type");
199
200 if (Value == 0) {
201 Res = Op0;
202 return None;
203 }
204
205 Res = MRI->createGenericVirtualRegister(MRI->getType(Op0));
206 unsigned TmpReg = MRI->createGenericVirtualRegister(ValueTy);
207
208 buildConstant(TmpReg, Value);
209 return buildGEP(Res, Op0, TmpReg);
210}
211
Tim Northoverc2f89562017-02-14 20:56:18 +0000212MachineInstrBuilder MachineIRBuilder::buildPtrMask(unsigned Res, unsigned Op0,
213 uint32_t NumBits) {
214 assert(MRI->getType(Res).isPointer() &&
215 MRI->getType(Res) == MRI->getType(Op0) && "type mismatch");
216
217 return buildInstr(TargetOpcode::G_PTR_MASK)
218 .addDef(Res)
219 .addUse(Op0)
220 .addImm(NumBits);
221}
222
Tim Northover0f140c72016-09-09 11:46:34 +0000223MachineInstrBuilder MachineIRBuilder::buildSub(unsigned Res, unsigned Op0,
224 unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000225 assert((MRI->getType(Res).isScalar() || MRI->getType(Res).isVector()) &&
226 "invalid operand type");
227 assert(MRI->getType(Res) == MRI->getType(Op0) &&
228 MRI->getType(Res) == MRI->getType(Op1) && "type mismatch");
229
Tim Northover0f140c72016-09-09 11:46:34 +0000230 return buildInstr(TargetOpcode::G_SUB)
Tim Northovercecee562016-08-26 17:46:13 +0000231 .addDef(Res)
232 .addUse(Op0)
233 .addUse(Op1);
234}
235
Tim Northover0f140c72016-09-09 11:46:34 +0000236MachineInstrBuilder MachineIRBuilder::buildMul(unsigned Res, unsigned Op0,
237 unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000238 assert((MRI->getType(Res).isScalar() || MRI->getType(Res).isVector()) &&
239 "invalid operand type");
240 assert(MRI->getType(Res) == MRI->getType(Op0) &&
241 MRI->getType(Res) == MRI->getType(Op1) && "type mismatch");
242
Tim Northover0f140c72016-09-09 11:46:34 +0000243 return buildInstr(TargetOpcode::G_MUL)
Tim Northovercecee562016-08-26 17:46:13 +0000244 .addDef(Res)
245 .addUse(Op0)
246 .addUse(Op1);
247}
248
Tim Northoverc3e3f592017-02-03 18:22:45 +0000249MachineInstrBuilder MachineIRBuilder::buildAnd(unsigned Res, unsigned Op0,
250 unsigned Op1) {
251 assert((MRI->getType(Res).isScalar() || MRI->getType(Res).isVector()) &&
252 "invalid operand type");
253 assert(MRI->getType(Res) == MRI->getType(Op0) &&
254 MRI->getType(Res) == MRI->getType(Op1) && "type mismatch");
255
256 return buildInstr(TargetOpcode::G_AND)
257 .addDef(Res)
258 .addUse(Op0)
259 .addUse(Op1);
260}
261
Tim Northovera51575f2016-07-29 17:43:52 +0000262MachineInstrBuilder MachineIRBuilder::buildBr(MachineBasicBlock &Dest) {
Tim Northover0f140c72016-09-09 11:46:34 +0000263 return buildInstr(TargetOpcode::G_BR).addMBB(&Dest);
Tim Northovercc5f7622016-07-26 16:45:26 +0000264}
265
Kristof Beyls65a12c02017-01-30 09:13:18 +0000266MachineInstrBuilder MachineIRBuilder::buildBrIndirect(unsigned Tgt) {
Tim Northoverc9902362017-06-27 22:45:35 +0000267 assert(MRI->getType(Tgt).isPointer() && "invalid branch destination");
Kristof Beyls65a12c02017-01-30 09:13:18 +0000268 return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt);
269}
270
Tim Northovera51575f2016-07-29 17:43:52 +0000271MachineInstrBuilder MachineIRBuilder::buildCopy(unsigned Res, unsigned Op) {
Tim Northover849fcca2017-06-27 21:41:40 +0000272 assert(MRI->getType(Res) == LLT() || MRI->getType(Op) == LLT() ||
273 MRI->getType(Res) == MRI->getType(Op));
Tim Northovera51575f2016-07-29 17:43:52 +0000274 return buildInstr(TargetOpcode::COPY).addDef(Res).addUse(Op);
Tim Northover756eca32016-07-26 16:45:30 +0000275}
276
Tim Northover9267ac52016-12-05 21:47:07 +0000277MachineInstrBuilder MachineIRBuilder::buildConstant(unsigned Res,
278 const ConstantInt &Val) {
279 LLT Ty = MRI->getType(Res);
Tim Northover1f8b1db2016-09-09 11:46:58 +0000280
Sam McCall03435f52016-12-06 10:14:36 +0000281 assert((Ty.isScalar() || Ty.isPointer()) && "invalid operand type");
Tim Northover9267ac52016-12-05 21:47:07 +0000282
283 const ConstantInt *NewVal = &Val;
284 if (Ty.getSizeInBits() != Val.getBitWidth())
285 NewVal = ConstantInt::get(MF->getFunction()->getContext(),
286 Val.getValue().sextOrTrunc(Ty.getSizeInBits()));
287
288 return buildInstr(TargetOpcode::G_CONSTANT).addDef(Res).addCImm(NewVal);
289}
290
291MachineInstrBuilder MachineIRBuilder::buildConstant(unsigned Res,
292 int64_t Val) {
293 auto IntN = IntegerType::get(MF->getFunction()->getContext(),
294 MRI->getType(Res).getSizeInBits());
295 ConstantInt *CI = ConstantInt::get(IntN, Val, true);
296 return buildConstant(Res, *CI);
Tim Northover9656f142016-08-04 20:54:13 +0000297}
298
Tim Northover0f140c72016-09-09 11:46:34 +0000299MachineInstrBuilder MachineIRBuilder::buildFConstant(unsigned Res,
300 const ConstantFP &Val) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000301 assert(MRI->getType(Res).isScalar() && "invalid operand type");
302
Tim Northover0f140c72016-09-09 11:46:34 +0000303 return buildInstr(TargetOpcode::G_FCONSTANT).addDef(Res).addFPImm(&Val);
Tim Northoverb16734f2016-08-19 20:09:15 +0000304}
305
Tim Northover0f140c72016-09-09 11:46:34 +0000306MachineInstrBuilder MachineIRBuilder::buildBrCond(unsigned Tst,
Tim Northover69c2ba52016-07-29 17:58:00 +0000307 MachineBasicBlock &Dest) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000308 assert(MRI->getType(Tst).isScalar() && "invalid operand type");
309
Tim Northover0f140c72016-09-09 11:46:34 +0000310 return buildInstr(TargetOpcode::G_BRCOND).addUse(Tst).addMBB(&Dest);
Tim Northover69c2ba52016-07-29 17:58:00 +0000311}
312
Tim Northover0f140c72016-09-09 11:46:34 +0000313MachineInstrBuilder MachineIRBuilder::buildLoad(unsigned Res, unsigned Addr,
314 MachineMemOperand &MMO) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000315 assert(MRI->getType(Res).isValid() && "invalid operand type");
316 assert(MRI->getType(Addr).isPointer() && "invalid operand type");
317
Tim Northover0f140c72016-09-09 11:46:34 +0000318 return buildInstr(TargetOpcode::G_LOAD)
Tim Northovera51575f2016-07-29 17:43:52 +0000319 .addDef(Res)
320 .addUse(Addr)
321 .addMemOperand(&MMO);
Tim Northoverad2b7172016-07-26 20:23:26 +0000322}
323
Tim Northover0f140c72016-09-09 11:46:34 +0000324MachineInstrBuilder MachineIRBuilder::buildStore(unsigned Val, unsigned Addr,
325 MachineMemOperand &MMO) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000326 assert(MRI->getType(Val).isValid() && "invalid operand type");
327 assert(MRI->getType(Addr).isPointer() && "invalid operand type");
328
Tim Northover0f140c72016-09-09 11:46:34 +0000329 return buildInstr(TargetOpcode::G_STORE)
Tim Northovera51575f2016-07-29 17:43:52 +0000330 .addUse(Val)
331 .addUse(Addr)
332 .addMemOperand(&MMO);
Tim Northoverad2b7172016-07-26 20:23:26 +0000333}
334
Tim Northover0f140c72016-09-09 11:46:34 +0000335MachineInstrBuilder MachineIRBuilder::buildUAdde(unsigned Res,
336 unsigned CarryOut,
337 unsigned Op0, unsigned Op1,
338 unsigned CarryIn) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000339 assert(MRI->getType(Res).isScalar() && "invalid operand type");
340 assert(MRI->getType(Res) == MRI->getType(Op0) &&
341 MRI->getType(Res) == MRI->getType(Op1) && "type mismatch");
342 assert(MRI->getType(CarryOut).isScalar() && "invalid operand type");
343 assert(MRI->getType(CarryOut) == MRI->getType(CarryIn) && "type mismatch");
344
Tim Northover0f140c72016-09-09 11:46:34 +0000345 return buildInstr(TargetOpcode::G_UADDE)
Tim Northover9656f142016-08-04 20:54:13 +0000346 .addDef(Res)
347 .addDef(CarryOut)
348 .addUse(Op0)
349 .addUse(Op1)
350 .addUse(CarryIn);
351}
352
Tim Northover0f140c72016-09-09 11:46:34 +0000353MachineInstrBuilder MachineIRBuilder::buildAnyExt(unsigned Res, unsigned Op) {
354 validateTruncExt(Res, Op, true);
355 return buildInstr(TargetOpcode::G_ANYEXT).addDef(Res).addUse(Op);
Tim Northover32335812016-08-04 18:35:11 +0000356}
357
Tim Northover0f140c72016-09-09 11:46:34 +0000358MachineInstrBuilder MachineIRBuilder::buildSExt(unsigned Res, unsigned Op) {
359 validateTruncExt(Res, Op, true);
360 return buildInstr(TargetOpcode::G_SEXT).addDef(Res).addUse(Op);
Tim Northover6cd4b232016-08-23 21:01:26 +0000361}
362
Tim Northover0f140c72016-09-09 11:46:34 +0000363MachineInstrBuilder MachineIRBuilder::buildZExt(unsigned Res, unsigned Op) {
364 validateTruncExt(Res, Op, true);
365 return buildInstr(TargetOpcode::G_ZEXT).addDef(Res).addUse(Op);
Tim Northover6cd4b232016-08-23 21:01:26 +0000366}
367
Tim Northovera7653b32016-09-12 11:20:22 +0000368MachineInstrBuilder MachineIRBuilder::buildSExtOrTrunc(unsigned Res,
369 unsigned Op) {
Tim Northoverc9902362017-06-27 22:45:35 +0000370 assert(MRI->getType(Res).isScalar() || MRI->getType(Res).isVector());
371 assert(MRI->getType(Res).isScalar() == MRI->getType(Op).isScalar());
372
Tim Northovera7653b32016-09-12 11:20:22 +0000373 unsigned Opcode = TargetOpcode::COPY;
374 if (MRI->getType(Res).getSizeInBits() > MRI->getType(Op).getSizeInBits())
375 Opcode = TargetOpcode::G_SEXT;
376 else if (MRI->getType(Res).getSizeInBits() < MRI->getType(Op).getSizeInBits())
377 Opcode = TargetOpcode::G_TRUNC;
Tim Northoverc9902362017-06-27 22:45:35 +0000378 else
379 assert(MRI->getType(Res) == MRI->getType(Op));
Tim Northovera7653b32016-09-12 11:20:22 +0000380
381 return buildInstr(Opcode).addDef(Res).addUse(Op);
382}
383
Tim Northoverc3e3f592017-02-03 18:22:45 +0000384MachineInstrBuilder MachineIRBuilder::buildZExtOrTrunc(unsigned Res,
385 unsigned Op) {
Tim Northoverc9902362017-06-27 22:45:35 +0000386 assert(MRI->getType(Res).isScalar() || MRI->getType(Res).isVector());
387 assert(MRI->getType(Res).isScalar() == MRI->getType(Op).isScalar());
388
Tim Northoverc3e3f592017-02-03 18:22:45 +0000389 unsigned Opcode = TargetOpcode::COPY;
390 if (MRI->getType(Res).getSizeInBits() > MRI->getType(Op).getSizeInBits())
391 Opcode = TargetOpcode::G_ZEXT;
392 else if (MRI->getType(Res).getSizeInBits() < MRI->getType(Op).getSizeInBits())
393 Opcode = TargetOpcode::G_TRUNC;
Tim Northoverc9902362017-06-27 22:45:35 +0000394 else
395 assert(MRI->getType(Res) == MRI->getType(Op));
Tim Northoverc3e3f592017-02-03 18:22:45 +0000396
397 return buildInstr(Opcode).addDef(Res).addUse(Op);
398}
399
Tim Northover95b6d5f2017-03-06 19:04:17 +0000400MachineInstrBuilder MachineIRBuilder::buildCast(unsigned Dst, unsigned Src) {
401 LLT SrcTy = MRI->getType(Src);
402 LLT DstTy = MRI->getType(Dst);
403 if (SrcTy == DstTy)
404 return buildCopy(Dst, Src);
405
406 unsigned Opcode;
407 if (SrcTy.isPointer() && DstTy.isScalar())
408 Opcode = TargetOpcode::G_PTRTOINT;
409 else if (DstTy.isPointer() && SrcTy.isScalar())
410 Opcode = TargetOpcode::G_INTTOPTR;
411 else {
412 assert(!SrcTy.isPointer() && !DstTy.isPointer() && "n G_ADDRCAST yet");
413 Opcode = TargetOpcode::G_BITCAST;
414 }
415
416 return buildInstr(Opcode).addDef(Dst).addUse(Src);
417}
418
Tim Northoverc2c545b2017-03-06 23:50:28 +0000419MachineInstrBuilder MachineIRBuilder::buildExtract(unsigned Res, unsigned Src,
420 uint64_t Index) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000421#ifndef NDEBUG
Tim Northover1f8b1db2016-09-09 11:46:58 +0000422 assert(MRI->getType(Src).isValid() && "invalid operand type");
Tim Northoverc2c545b2017-03-06 23:50:28 +0000423 assert(MRI->getType(Res).isValid() && "invalid operand type");
424 assert(Index + MRI->getType(Res).getSizeInBits() <=
425 MRI->getType(Src).getSizeInBits() &&
426 "extracting off end of register");
Tim Northover1f8b1db2016-09-09 11:46:58 +0000427#endif
428
Tim Northoverc2c545b2017-03-06 23:50:28 +0000429 if (MRI->getType(Res).getSizeInBits() == MRI->getType(Src).getSizeInBits()) {
430 assert(Index == 0 && "insertion past the end of a register");
431 return buildCast(Res, Src);
432 }
Tim Northover33b07d62016-07-22 20:03:43 +0000433
Tim Northoverc2c545b2017-03-06 23:50:28 +0000434 return buildInstr(TargetOpcode::G_EXTRACT)
435 .addDef(Res)
436 .addUse(Src)
437 .addImm(Index);
Tim Northover33b07d62016-07-22 20:03:43 +0000438}
439
Tim Northoverb57bf2a2017-06-23 16:15:37 +0000440void MachineIRBuilder::buildSequence(unsigned Res, ArrayRef<unsigned> Ops,
441 ArrayRef<uint64_t> Indices) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000442#ifndef NDEBUG
Tim Northover0f140c72016-09-09 11:46:34 +0000443 assert(Ops.size() == Indices.size() && "incompatible args");
Tim Northover26b76f22016-08-19 18:32:14 +0000444 assert(!Ops.empty() && "invalid trivial sequence");
Tim Northover991b12b2016-08-30 20:51:25 +0000445 assert(std::is_sorted(Indices.begin(), Indices.end()) &&
446 "sequence offsets must be in ascending order");
Tim Northover91c81732016-08-19 17:17:06 +0000447
Tim Northover1f8b1db2016-09-09 11:46:58 +0000448 assert(MRI->getType(Res).isValid() && "invalid operand type");
449 for (auto Op : Ops)
450 assert(MRI->getType(Op).isValid() && "invalid operand type");
451#endif
452
Tim Northoverb57bf2a2017-06-23 16:15:37 +0000453 LLT ResTy = MRI->getType(Res);
454 LLT OpTy = MRI->getType(Ops[0]);
455 unsigned OpSize = OpTy.getSizeInBits();
456 bool MaybeMerge = true;
Tim Northover91c81732016-08-19 17:17:06 +0000457 for (unsigned i = 0; i < Ops.size(); ++i) {
Tim Northoverb57bf2a2017-06-23 16:15:37 +0000458 if (MRI->getType(Ops[i]) != OpTy || Indices[i] != i * OpSize) {
459 MaybeMerge = false;
460 break;
461 }
Tim Northover91c81732016-08-19 17:17:06 +0000462 }
Tim Northoverb57bf2a2017-06-23 16:15:37 +0000463
464 if (MaybeMerge && Ops.size() * OpSize == ResTy.getSizeInBits()) {
465 buildMerge(Res, Ops);
466 return;
467 }
468
469 unsigned ResIn = MRI->createGenericVirtualRegister(ResTy);
470 buildUndef(ResIn);
471
472 for (unsigned i = 0; i < Ops.size(); ++i) {
473 unsigned ResOut =
474 i + 1 == Ops.size() ? Res : MRI->createGenericVirtualRegister(ResTy);
475 buildInsert(ResOut, ResIn, Ops[i], Indices[i]);
476 ResIn = ResOut;
477 }
Tim Northover33b07d62016-07-22 20:03:43 +0000478}
Tim Northover5fb414d2016-07-29 22:32:36 +0000479
Tim Northover81dafc12017-03-06 18:36:40 +0000480MachineInstrBuilder MachineIRBuilder::buildUndef(unsigned Res) {
481 return buildInstr(TargetOpcode::IMPLICIT_DEF).addDef(Res);
482}
483
Tim Northoverbf017292017-03-03 22:46:09 +0000484MachineInstrBuilder MachineIRBuilder::buildMerge(unsigned Res,
485 ArrayRef<unsigned> Ops) {
486
487#ifndef NDEBUG
488 assert(!Ops.empty() && "invalid trivial sequence");
489 LLT Ty = MRI->getType(Ops[0]);
490 for (auto Reg : Ops)
491 assert(MRI->getType(Reg) == Ty && "type mismatch in input list");
492 assert(Ops.size() * MRI->getType(Ops[0]).getSizeInBits() ==
493 MRI->getType(Res).getSizeInBits() &&
494 "input operands do not cover output register");
495#endif
496
Tim Northoverc2d5e6d2017-06-26 20:34:13 +0000497 if (Ops.size() == 1)
Tim Northover849fcca2017-06-27 21:41:40 +0000498 return buildCast(Res, Ops[0]);
Tim Northoverc2d5e6d2017-06-26 20:34:13 +0000499
Tim Northoverbf017292017-03-03 22:46:09 +0000500 MachineInstrBuilder MIB = buildInstr(TargetOpcode::G_MERGE_VALUES);
501 MIB.addDef(Res);
502 for (unsigned i = 0; i < Ops.size(); ++i)
503 MIB.addUse(Ops[i]);
504 return MIB;
505}
506
507MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<unsigned> Res,
508 unsigned Op) {
509
510#ifndef NDEBUG
511 assert(!Res.empty() && "invalid trivial sequence");
512 LLT Ty = MRI->getType(Res[0]);
513 for (auto Reg : Res)
514 assert(MRI->getType(Reg) == Ty && "type mismatch in input list");
515 assert(Res.size() * MRI->getType(Res[0]).getSizeInBits() ==
516 MRI->getType(Op).getSizeInBits() &&
517 "input operands do not cover output register");
518#endif
519
520 MachineInstrBuilder MIB = buildInstr(TargetOpcode::G_UNMERGE_VALUES);
521 for (unsigned i = 0; i < Res.size(); ++i)
522 MIB.addDef(Res[i]);
523 MIB.addUse(Op);
524 return MIB;
525}
526
Tim Northover3e6a7af2017-03-03 23:05:47 +0000527MachineInstrBuilder MachineIRBuilder::buildInsert(unsigned Res, unsigned Src,
528 unsigned Op, unsigned Index) {
Tim Northoverc9902362017-06-27 22:45:35 +0000529 assert(Index + MRI->getType(Op).getSizeInBits() <=
530 MRI->getType(Res).getSizeInBits() &&
531 "insertion past the end of a register");
532
Tim Northover95b6d5f2017-03-06 19:04:17 +0000533 if (MRI->getType(Res).getSizeInBits() == MRI->getType(Op).getSizeInBits()) {
Tim Northover95b6d5f2017-03-06 19:04:17 +0000534 return buildCast(Res, Op);
535 }
536
Tim Northover3e6a7af2017-03-03 23:05:47 +0000537 return buildInstr(TargetOpcode::G_INSERT)
538 .addDef(Res)
539 .addUse(Src)
540 .addUse(Op)
541 .addImm(Index);
542}
543
Tim Northover0f140c72016-09-09 11:46:34 +0000544MachineInstrBuilder MachineIRBuilder::buildIntrinsic(Intrinsic::ID ID,
Tim Northover5fb414d2016-07-29 22:32:36 +0000545 unsigned Res,
546 bool HasSideEffects) {
547 auto MIB =
548 buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
Tim Northover0f140c72016-09-09 11:46:34 +0000549 : TargetOpcode::G_INTRINSIC);
Tim Northover5fb414d2016-07-29 22:32:36 +0000550 if (Res)
551 MIB.addDef(Res);
552 MIB.addIntrinsicID(ID);
553 return MIB;
554}
Tim Northover32335812016-08-04 18:35:11 +0000555
Tim Northover0f140c72016-09-09 11:46:34 +0000556MachineInstrBuilder MachineIRBuilder::buildTrunc(unsigned Res, unsigned Op) {
557 validateTruncExt(Res, Op, false);
558 return buildInstr(TargetOpcode::G_TRUNC).addDef(Res).addUse(Op);
Tim Northover32335812016-08-04 18:35:11 +0000559}
Tim Northoverde3aea0412016-08-17 20:25:25 +0000560
Tim Northover0f140c72016-09-09 11:46:34 +0000561MachineInstrBuilder MachineIRBuilder::buildFPTrunc(unsigned Res, unsigned Op) {
562 validateTruncExt(Res, Op, false);
563 return buildInstr(TargetOpcode::G_FPTRUNC).addDef(Res).addUse(Op);
Tim Northovera11be042016-08-19 22:40:08 +0000564}
565
Tim Northover0f140c72016-09-09 11:46:34 +0000566MachineInstrBuilder MachineIRBuilder::buildICmp(CmpInst::Predicate Pred,
Tim Northoverde3aea0412016-08-17 20:25:25 +0000567 unsigned Res, unsigned Op0,
568 unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000569#ifndef NDEBUG
Tim Northover1f8b1db2016-09-09 11:46:58 +0000570 assert(MRI->getType(Op0) == MRI->getType(Op0) && "type mismatch");
571 assert(CmpInst::isIntPredicate(Pred) && "invalid predicate");
Tim Northover4cf0a482016-09-15 10:40:38 +0000572 if (MRI->getType(Op0).isScalar() || MRI->getType(Op0).isPointer())
Tim Northover1f8b1db2016-09-09 11:46:58 +0000573 assert(MRI->getType(Res).isScalar() && "type mismatch");
574 else
575 assert(MRI->getType(Res).isVector() &&
576 MRI->getType(Res).getNumElements() ==
577 MRI->getType(Op0).getNumElements() &&
578 "type mismatch");
579#endif
580
Tim Northover0f140c72016-09-09 11:46:34 +0000581 return buildInstr(TargetOpcode::G_ICMP)
Tim Northoverde3aea0412016-08-17 20:25:25 +0000582 .addDef(Res)
583 .addPredicate(Pred)
584 .addUse(Op0)
585 .addUse(Op1);
586}
Tim Northover5a28c362016-08-19 20:09:07 +0000587
Tim Northover0f140c72016-09-09 11:46:34 +0000588MachineInstrBuilder MachineIRBuilder::buildFCmp(CmpInst::Predicate Pred,
Tim Northoverd5c23bc2016-08-19 20:48:16 +0000589 unsigned Res, unsigned Op0,
590 unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000591#ifndef NDEBUG
592 assert((MRI->getType(Op0).isScalar() || MRI->getType(Op0).isVector()) &&
593 "invalid operand type");
594 assert(MRI->getType(Op0) == MRI->getType(Op1) && "type mismatch");
595 assert(CmpInst::isFPPredicate(Pred) && "invalid predicate");
596 if (MRI->getType(Op0).isScalar())
597 assert(MRI->getType(Res).isScalar() && "type mismatch");
598 else
599 assert(MRI->getType(Res).isVector() &&
600 MRI->getType(Res).getNumElements() ==
601 MRI->getType(Op0).getNumElements() &&
602 "type mismatch");
603#endif
604
Tim Northover0f140c72016-09-09 11:46:34 +0000605 return buildInstr(TargetOpcode::G_FCMP)
Tim Northoverd5c23bc2016-08-19 20:48:16 +0000606 .addDef(Res)
607 .addPredicate(Pred)
608 .addUse(Op0)
609 .addUse(Op1);
610}
611
Tim Northover0f140c72016-09-09 11:46:34 +0000612MachineInstrBuilder MachineIRBuilder::buildSelect(unsigned Res, unsigned Tst,
Tim Northover5a28c362016-08-19 20:09:07 +0000613 unsigned Op0, unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000614#ifndef NDEBUG
Tim Northoverf50f2f32016-12-06 18:38:34 +0000615 LLT ResTy = MRI->getType(Res);
616 assert((ResTy.isScalar() || ResTy.isVector() || ResTy.isPointer()) &&
Tim Northover1f8b1db2016-09-09 11:46:58 +0000617 "invalid operand type");
Tim Northoverf50f2f32016-12-06 18:38:34 +0000618 assert(ResTy == MRI->getType(Op0) && ResTy == MRI->getType(Op1) &&
619 "type mismatch");
620 if (ResTy.isScalar() || ResTy.isPointer())
Tim Northover1f8b1db2016-09-09 11:46:58 +0000621 assert(MRI->getType(Tst).isScalar() && "type mismatch");
622 else
Ahmed Bougacha38455ea2017-03-07 20:53:03 +0000623 assert((MRI->getType(Tst).isScalar() ||
624 (MRI->getType(Tst).isVector() &&
625 MRI->getType(Tst).getNumElements() ==
626 MRI->getType(Op0).getNumElements())) &&
Tim Northover1f8b1db2016-09-09 11:46:58 +0000627 "type mismatch");
628#endif
629
Tim Northover0f140c72016-09-09 11:46:34 +0000630 return buildInstr(TargetOpcode::G_SELECT)
Tim Northover5a28c362016-08-19 20:09:07 +0000631 .addDef(Res)
632 .addUse(Tst)
633 .addUse(Op0)
634 .addUse(Op1);
635}
Tim Northoverbdf67c92016-08-23 21:01:33 +0000636
Volkan Keles04cb08c2017-03-10 19:08:28 +0000637MachineInstrBuilder MachineIRBuilder::buildInsertVectorElement(unsigned Res,
638 unsigned Val,
639 unsigned Elt,
640 unsigned Idx) {
641#ifndef NDEBUG
642 LLT ResTy = MRI->getType(Res);
643 LLT ValTy = MRI->getType(Val);
644 LLT EltTy = MRI->getType(Elt);
645 LLT IdxTy = MRI->getType(Idx);
646 assert(ResTy.isVector() && ValTy.isVector() && "invalid operand type");
Kristof Beyls0f36e682017-04-19 07:23:57 +0000647 assert(IdxTy.isScalar() && "invalid operand type");
Volkan Keles04cb08c2017-03-10 19:08:28 +0000648 assert(ResTy.getNumElements() == ValTy.getNumElements() && "type mismatch");
649 assert(ResTy.getElementType() == EltTy && "type mismatch");
650#endif
651
652 return buildInstr(TargetOpcode::G_INSERT_VECTOR_ELT)
653 .addDef(Res)
654 .addUse(Val)
655 .addUse(Elt)
656 .addUse(Idx);
657}
658
659MachineInstrBuilder MachineIRBuilder::buildExtractVectorElement(unsigned Res,
660 unsigned Val,
661 unsigned Idx) {
662#ifndef NDEBUG
663 LLT ResTy = MRI->getType(Res);
664 LLT ValTy = MRI->getType(Val);
665 LLT IdxTy = MRI->getType(Idx);
666 assert(ValTy.isVector() && "invalid operand type");
Kristof Beyls0f36e682017-04-19 07:23:57 +0000667 assert((ResTy.isScalar() || ResTy.isPointer()) && "invalid operand type");
668 assert(IdxTy.isScalar() && "invalid operand type");
Volkan Keles04cb08c2017-03-10 19:08:28 +0000669 assert(ValTy.getElementType() == ResTy && "type mismatch");
670#endif
671
672 return buildInstr(TargetOpcode::G_EXTRACT_VECTOR_ELT)
673 .addDef(Res)
674 .addUse(Val)
675 .addUse(Idx);
676}
677
Tim Northover0f140c72016-09-09 11:46:34 +0000678void MachineIRBuilder::validateTruncExt(unsigned Dst, unsigned Src,
679 bool IsExtend) {
Richard Smith418237b2016-08-23 22:14:15 +0000680#ifndef NDEBUG
Tim Northover0f140c72016-09-09 11:46:34 +0000681 LLT SrcTy = MRI->getType(Src);
682 LLT DstTy = MRI->getType(Dst);
Tim Northoverbdf67c92016-08-23 21:01:33 +0000683
684 if (DstTy.isVector()) {
685 assert(SrcTy.isVector() && "mismatched cast between vecot and non-vector");
686 assert(SrcTy.getNumElements() == DstTy.getNumElements() &&
687 "different number of elements in a trunc/ext");
688 } else
689 assert(DstTy.isScalar() && SrcTy.isScalar() && "invalid extend/trunc");
690
691 if (IsExtend)
692 assert(DstTy.getSizeInBits() > SrcTy.getSizeInBits() &&
693 "invalid narrowing extend");
694 else
695 assert(DstTy.getSizeInBits() < SrcTy.getSizeInBits() &&
696 "invalid widening trunc");
Richard Smith418237b2016-08-23 22:14:15 +0000697#endif
Tim Northoverbdf67c92016-08-23 21:01:33 +0000698}