| Alex Bradbury | ffc435e | 2017-11-21 08:11:03 +0000 | [diff] [blame^] | 1 | ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| 2 | ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ |
| 3 | ; RUN: | FileCheck %s -check-prefix=RV32I |
| 4 | |
| 5 | define i32 @square(i32 %a) { |
| 6 | ; RV32I-LABEL: square: |
| 7 | ; RV32I: # BB#0: |
| 8 | ; RV32I-NEXT: sw ra, 12(s0) |
| 9 | ; RV32I-NEXT: lui a1, %hi(__mulsi3) |
| 10 | ; RV32I-NEXT: addi a2, a1, %lo(__mulsi3) |
| 11 | ; RV32I-NEXT: addi a1, a0, 0 |
| 12 | ; RV32I-NEXT: jalr ra, a2, 0 |
| 13 | ; RV32I-NEXT: lw ra, 12(s0) |
| 14 | ; RV32I-NEXT: jalr zero, ra, 0 |
| 15 | %1 = mul i32 %a, %a |
| 16 | ret i32 %1 |
| 17 | } |
| 18 | |
| 19 | define i32 @mul(i32 %a, i32 %b) { |
| 20 | ; RV32I-LABEL: mul: |
| 21 | ; RV32I: # BB#0: |
| 22 | ; RV32I-NEXT: sw ra, 12(s0) |
| 23 | ; RV32I-NEXT: lui a2, %hi(__mulsi3) |
| 24 | ; RV32I-NEXT: addi a2, a2, %lo(__mulsi3) |
| 25 | ; RV32I-NEXT: jalr ra, a2, 0 |
| 26 | ; RV32I-NEXT: lw ra, 12(s0) |
| 27 | ; RV32I-NEXT: jalr zero, ra, 0 |
| 28 | %1 = mul i32 %a, %b |
| 29 | ret i32 %1 |
| 30 | } |
| 31 | |
| 32 | define i32 @mul_constant(i32 %a) { |
| 33 | ; RV32I-LABEL: mul_constant: |
| 34 | ; RV32I: # BB#0: |
| 35 | ; RV32I-NEXT: sw ra, 12(s0) |
| 36 | ; RV32I-NEXT: lui a1, %hi(__mulsi3) |
| 37 | ; RV32I-NEXT: addi a2, a1, %lo(__mulsi3) |
| 38 | ; RV32I-NEXT: addi a1, zero, 5 |
| 39 | ; RV32I-NEXT: jalr ra, a2, 0 |
| 40 | ; RV32I-NEXT: lw ra, 12(s0) |
| 41 | ; RV32I-NEXT: jalr zero, ra, 0 |
| 42 | %1 = mul i32 %a, 5 |
| 43 | ret i32 %1 |
| 44 | } |
| 45 | |
| 46 | define i32 @mul_pow2(i32 %a) { |
| 47 | ; RV32I-LABEL: mul_pow2: |
| 48 | ; RV32I: # BB#0: |
| 49 | ; RV32I-NEXT: slli a0, a0, 3 |
| 50 | ; RV32I-NEXT: jalr zero, ra, 0 |
| 51 | %1 = mul i32 %a, 8 |
| 52 | ret i32 %1 |
| 53 | } |
| 54 | |
| 55 | define i64 @mul64(i64 %a, i64 %b) { |
| 56 | ; RV32I-LABEL: mul64: |
| 57 | ; RV32I: # BB#0: |
| 58 | ; RV32I-NEXT: sw ra, 12(s0) |
| 59 | ; RV32I-NEXT: lui a4, %hi(__muldi3) |
| 60 | ; RV32I-NEXT: addi a4, a4, %lo(__muldi3) |
| 61 | ; RV32I-NEXT: jalr ra, a4, 0 |
| 62 | ; RV32I-NEXT: lw ra, 12(s0) |
| 63 | ; RV32I-NEXT: jalr zero, ra, 0 |
| 64 | %1 = mul i64 %a, %b |
| 65 | ret i64 %1 |
| 66 | } |
| 67 | |
| 68 | define i64 @mul64_constant(i64 %a) { |
| 69 | ; RV32I-LABEL: mul64_constant: |
| 70 | ; RV32I: # BB#0: |
| 71 | ; RV32I-NEXT: sw ra, 12(s0) |
| 72 | ; RV32I-NEXT: lui a2, %hi(__muldi3) |
| 73 | ; RV32I-NEXT: addi a4, a2, %lo(__muldi3) |
| 74 | ; RV32I-NEXT: addi a2, zero, 5 |
| 75 | ; RV32I-NEXT: addi a3, zero, 0 |
| 76 | ; RV32I-NEXT: jalr ra, a4, 0 |
| 77 | ; RV32I-NEXT: lw ra, 12(s0) |
| 78 | ; RV32I-NEXT: jalr zero, ra, 0 |
| 79 | %1 = mul i64 %a, 5 |
| 80 | ret i64 %1 |
| 81 | } |