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gerrit-public.fairphone.software / toolchain / llvm-project / 03c2c65b2d288b936f5b298473314d665c89ef45 / llvm / lib / Target / ARM / Disassembler / ARMDisassembler.cpp
  1. 963da5b [ARM] v8.3-a complex number support by Sam Parker · 8 years ago
  2. 640527f [ARM] Fix assembly and disassembly for VMRS/VMSR by Andre Vieira · 8 years ago
  3. 076468c [ARM] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). by Eugene Zelenko · 8 years ago
  4. 7426c97 [ARM] Assembler support for the ARMv8.2a dot product instructions by Sjoerd Meijer · 8 years ago
  5. f370f2e Revert "[ARM] Fix assembly and disassembly for VMRS/VMSR" by Tim Northover · 8 years ago
  6. 7dffb9b [ARM] Fix assembly and disassembly for VMRS/VMSR by Andre Vieira · 8 years ago
  7. 6269d39 [llvm-objdump] Handle invalid instruction gracefully on ARM by Eugene Leviant · 8 years ago
  8. 6bda14b Sort the remaining #include lines in include/... and lib/.... by Chandler Carruth · 8 years ago
  9. aea3a99 ARMDisassembler: loop over ARM decode tables by Sjoerd Meijer · 9 years ago
  10. e79c077 [ARM] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). by Eugene Zelenko · 9 years ago
  11. f42454b Move the global variables representing each Target behind accessor function by Mehdi Amini · 9 years ago
  12. cd1d5aa Replace a few more "fall through" comments with LLVM_FALLTHROUGH by Justin Bogner · 9 years ago
  13. 39d2d09 [ARM] Add support for mrrc/mrrc2 intrinsics. by Ranjeet Singh · 9 years ago
  14. 0db7be8 Reverting r272778 because there's an assertion by Ranjeet Singh · 9 years ago
  15. 351364f [ARM] Add support for mrrc/mrrc2 intrinsics. by Ranjeet Singh · 9 years ago
  16. 933e1aa [ARM] Reverting r272544 because clang patch needs by Ranjeet Singh · 9 years ago
  17. 8feacb3 [ARM] Add mrrc/mrrc2 co-processor intrinsics by Ranjeet Singh · 9 years ago
  18. d906bf1 RAS extensions are part of ARMv8.2-A. This change enables them by introducing a by Sjoerd Meijer · 9 years ago
  19. f57c197 Reflect the MC/MCDisassembler split on the include/ level. by Benjamin Kramer · 10 years ago
  20. f277c8a [ARM] Add new system registers to ARMv8-M Baseline/Mainline by Bradley Smith · 10 years ago
  21. 65b8538 [ARM] Add ARMv8.2-A FP16 scalar instructions by Oliver Stannard · 10 years ago
  22. 47f2452 # This is a combination of 2 commits. # The first commit's message is: by Reid Kleckner · 10 years ago
  23. 42f6e90 [ARM] Add new system registers to ARMv8-M Baseline/Mainline by Bradley Smith · 10 years ago
  24. 187d33e Revert "[ARM] Add ARMv8.2-A FP16 scalar instructions" by Reid Kleckner · 10 years ago
  25. 2de8c16 [ARM] Add ARMv8.2-A FP16 vector instructions by Oliver Stannard · 10 years ago
  26. 48568cb [ARM] Add ARMv8.2-A FP16 scalar instructions by Oliver Stannard · 10 years ago
  27. 67cf33d Test commit by Vinicius Tinti · 10 years ago
  28. b4398107 [ARM] Allow SP in rGPR, starting from ARMv8 by Artyom Skrobov · 10 years ago
  29. cf29644 [ARM] Handle +t2dsp feature as an ArchExtKind in ARMTargetParser.def by Artyom Skrobov · 10 years ago
  30. f97999d Explicitly clear the MI operand list when getInstruction() is called. Call MI.clear() within MCD::OPC_Decode case and inside of translateInstruction() for the X86 target. Remove now unnecessary MI.clear() from ARMDisassembler. by Cameron Esfahani · 10 years ago
  31. f00654e Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC) by Alexander Kornienko · 10 years ago
  32. 70bc5f1 Fixed/added namespace ending comments using clang-tidy. NFC by Alexander Kornienko · 10 years ago
  33. db0712f Use std::bitset for SubtargetFeatures. by Michael Kuperstein · 10 years ago
  34. e9119e4 MC: Modernize MCOperand API naming. NFC. by Jim Grosbach · 10 years ago
  35. c3434b3 Reverting r237234, "Use std::bitset for SubtargetFeatures" by Michael Kuperstein · 10 years ago
  36. aba4a34 Use std::bitset for SubtargetFeatures by Michael Kuperstein · 10 years ago
  37. 0e0f8d2 [ARM] Add v8.1a "Privileged Access Never" extension by Vladimir Sukharev · 11 years ago
  38. f817c1c Use 'override/final' instead of 'virtual' for overridden methods by Alexander Kornienko · 11 years ago
  39. 29704e7 Revert "Use std::bitset for SubtargetFeatures" by Michael Kuperstein · 11 years ago
  40. 774b441 Use std::bitset for SubtargetFeatures by Michael Kuperstein · 11 years ago
  41. efd7a96 Reverting r229831 due to multiple ARM/PPC/MIPS build-bot failures. by Michael Kuperstein · 11 years ago
  42. ba5b04c Use std::bitset for SubtargetFeatures by Michael Kuperstein · 11 years ago
  43. 3131e85 [ARM] SSAT/USAT with an 'asr #32' shift should result in an undefined encoding rather than unpredictable by Bradley Smith · 11 years ago
  44. cdfa931 Remove unused function. by Asiri Rathnayake · 11 years ago
  45. 30895f9 Add post-decode checking of HVC instruction. by Charlie Turner · 11 years ago
  46. 7fc5b87 Pass an ArrayRef to MCDisassembler::getInstruction. by Rafael Espindola · 11 years ago
  47. 4aa6bea Misc style fixes. NFC. by Rafael Espindola · 11 years ago
  48. f2572c5 [ARM] Remove dead code identified by the Clang static analyzer. by Tilmann Scheller · 11 years ago
  49. 9e89d8c [ARM] Honor FeatureD16 in the assembler and disassembler by Oliver Stannard · 11 years ago
  50. 39a85ab [Thumb2] Improve disassembly of memory hints by Oliver Stannard · 11 years ago
  51. 92c816c Thumb2 M-class MSR instruction support changes by Renato Golin · 11 years ago
  52. ee843ef ARM: implement MRS/MSR (banked reg) system instructions. by Tim Northover · 11 years ago
  53. 137ce60 Allow only disassembling of M-class MSR masks that the assembler knows how to assemble back. by James Molloy · 11 years ago
  54. 84e68b2 [Modules] Fix potential ODR violations by sinking the DEBUG_TYPE by Chandler Carruth · 12 years ago
  55. a1bc0f5 [MC] Require an MCContext when constructing an MCDisassembler. by Lang Hames · 12 years ago
  56. dc9ff75 ARM: rename ARMle/ARMbe with ARMLE/ARMBE, and Thumble/Thumbbe with ThumbLE/ThumbBE by Christian Pirker · 12 years ago
  57. 2a11160 Add ARM big endian Target (armeb, thumbeb) by Christian Pirker · 12 years ago
  58. ca7e3e5 [C++11] Add 'override' keyword to virtual methods that override their base class. by Craig Topper · 12 years ago
  59. e686cec [ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (ARM encodings) by Artyom Skrobov · 12 years ago
  60. c1be9c1 [ARM] NEON instructions were erroneously decoded from certain invalid encodings by Artyom Skrobov · 12 years ago
  61. 08a8660 ARM: provide diagnostics on more writeback LDM/STM instructions by Tim Northover · 12 years ago
  62. 510de64 [ARM] Remove an unused function from the disassembler. by Joey Gouly · 12 years ago
  63. 3308909 [ARMv8] Add support for the v8 cryptography extensions. by Amara Emerson · 12 years ago
  64. c34bf73 This corrects creation of operands for t2PLDW. It also removes the definition of t2PLDWpci, by Mihai Popa · 12 years ago
  65. df68600 [ARMv8] Add support for the NEON instructions vmaxnm/vminnm. by Joey Gouly · 12 years ago
  66. 18ce7e4 Remove an unneeded call to 'UpdateThumbVFPPredicate', spotted by Amaury. by Joey Gouly · 12 years ago
  67. cc4ff9e Add support for MC assembling and disassembling of vsel{ge, gt, eq, vs} instructions. by Joey Gouly · 12 years ago
  68. 8449c0d ARM: check predicate bits for thumb instructions by Amaury de la Vieuville · 12 years ago
  69. 8175bda ARM: rGPR is meant to be unpredictable, not undefined by Amaury de la Vieuville · 12 years ago
  70. 2f0ac8d ARM: fix IT decoding by Amaury de la Vieuville · 12 years ago
  71. 4b6c076 ARM: enable decoding of pc-relative PLD/PLI by Amaury de la Vieuville · 12 years ago
  72. 4d3e3f2 ARM: fix thumb literal loads decoding by Amaury de la Vieuville · 12 years ago
  73. e2bb1d1 ARM: thumb stores cannot use PC as dest register by Amaury de la Vieuville · 12 years ago
  74. bd2b610 ARM: fix B decoding by Amaury de la Vieuville · 12 years ago
  75. 064546c ARM: Enforce decoding rules for VLDn instructions by Amaury de la Vieuville · 12 years ago
  76. 53ff029 ARM: Fix STREX/LDREX reecoding by Amaury de la Vieuville · 12 years ago
  77. 43cb13a ARM: ISB cannot be passed the same options as DMB by Amaury de la Vieuville · 12 years ago
  78. f4ec0c85 ARM: fix VMOVvnf32 decoding when ambiguous with VCVT by Amaury de la Vieuville · 12 years ago
  79. 68bcd02 ARM: enforce SRS decoding constraints by Amaury de la Vieuville · 12 years ago
  80. 631df63 ARM: fix CPS decoding when ambiguous with QADD by Amaury de la Vieuville · 12 years ago
  81. ea7bb57 ARM: fix VCVT decoding by Amaury de la Vieuville · 12 years ago
  82. 4173e29 ARM: add fstmx and fldmx instructions for assembly by Tim Northover · 12 years ago
  83. df1ecbd7 Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros. by Michael J. Spencer · 12 years ago
  84. 534d3a4 Remove the Copied parameter from MemoryObject::readBytes. by Benjamin Kramer · 12 years ago
  85. ad1084d Add MCSymbolizer for symbolic/annotated disassembly. by Ahmed Bougacha · 12 years ago
  86. f41e3f5 VSTn instructions have a number of encoding constraints which are not implemented. I have added these using wrapper methods around the original custom decoder (incidentally - this is a huge poorly written method that should be cleaned up. I have left it as is since the changes would be much to hard to review). by Mihai Popa · 12 years ago
  87. dcf0922 Q registers are encoded in fields of the same length as D registers. As Q registers are half as many, the ARM reference manual mandates the least significant bit to be zeroed out. Failure to do so should result in an undefined instruction. With this change test/MC/Disassembler/ARM/invalid-VQADD-arm.txt is passing (removed XFAIL). by Mihai Popa · 12 years ago
  88. 8bad66e Replace some bit operations with simpler ones. No functionality change. by Benjamin Kramer · 12 years ago
  89. dc1764c5 The purpose of the patch is to fix the syntax of ARM mrc and mrc2 instructions when they are used to write to the APSR. In this case, the destination operand should be APSR_nzcv, and the encoding of the target should be 0b1111 (same as for PC). In pre-UAL syntax, this form used the PC register as a textual target. This is still allowed for backward compatibility. by Mihai Popa · 12 years ago
  90. a83d5e9 ARM: Fix encoding of hint instruction for Thumb. by Quentin Colombet · 13 years ago
  91. 27ff504 ARM: Permit "sp" in ARM variant of STREXD instructions by Tim Northover · 13 years ago
  92. a155ab2 ARM: permit "sp" in ARM variants of MOVW/MOVT instructions by Tim Northover · 13 years ago
  93. 6f03f62 Fix treatment of ARM unallocated hint instructions. by Quentin Colombet · 13 years ago
  94. 772cf46 Fix issue with disassembler decoding CBZ/CBNZ immediates as negatives when the upper bit is set. by Gordon Keiser · 13 years ago
  95. f686be4 Patch by Gordon Keiser! by Joe Abbey · 13 years ago
  96. e3d3230 Remove edis - the enhanced disassembler. Fixes PR14654. by Roman Divacky · 13 years ago
  97. ed0881b Use the new script to sort the includes of every file under lib. by Chandler Carruth · 13 years ago
  98. 136d674 Fixed the arm disassembly of invalid BFI instructions to not build a bad MCInst by Kevin Enderby · 13 years ago
  99. 6fd9624 Fix ARM's b.w instruction for thumb 2 and the encoding T4. The branch target by Kevin Enderby · 13 years ago
  100. b23926d Fix a bug where a 32-bit address with the high bit does not get symbolicated by Kevin Enderby · 13 years ago