- 7daf6a4 Hide the pre-RA-sched= option. by Andrew Trick · 12 years ago
- ea2db45 Add a machine code print in DEBUG() following instruction selection. by Jim Grosbach · 12 years ago
- ee08897 Reland "Fix miscompile of MS inline assembly with stack realignment" by Reid Kleckner · 12 years ago
- 0a9509f Revert "Fix miscompile of MS inline assembly with stack realignment" by Reid Kleckner · 12 years ago
- 7f10a8c Fix miscompile of MS inline assembly with stack realignment by Reid Kleckner · 12 years ago
- b021c6f Fixed tryFoldToZero() for vector types that need expansion. by Daniel Sanders · 12 years ago
- d89125a Teach ISel not to optimize 'optnone' functions (revised). by Paul Robinson · 12 years ago
- 43aa939 Revert r195317 (and r195333), "Teach ISel not to optimize 'optnone' functions." by NAKAMURA Takumi · 12 years ago
- b379efe Teach ISel not to optimize 'optnone' functions. by Paul Robinson · 12 years ago
- d4b22dc long line correction by Jack Carter · 12 years ago
- b348710 [DAG] Refactor vector splitting code in SelectionDAG. No functional change intended. by Juergen Ributzka · 12 years ago
- 50b8041 Fix illegal DAG produced by SelectionDAG::getConstant() for v2i64 type by Daniel Sanders · 12 years ago
- a7afa71 Fix some assert messages to say the correct opcode name. Looks like one assert got copy and pasted to many places. by Craig Topper · 12 years ago
- a1bbc32 Add OPC_CheckChildSame0-3 to the DAG isel matcher. This replaces sequences of MoveChild, CheckSame, MoveParent. Saves 846 bytes from the X86 DAG isel matcher, ~300 from ARM, ~840 from Hexagon. by Craig Topper · 12 years ago
- f01b562 Debug info: Don't crash in SelectionDAGISel when a vreg that is being by Adrian Prantl · 12 years ago
- d9a6cc0 Revert r191940 to see if it fixes the build bots. by Craig Topper · 12 years ago
- a2efe9e Add OPC_CheckChildSame0-3 to the DAG isel matcher. This replaces sequences of MoveChild, CheckSame, MoveParent. Saves 846 bytes from the X86 DAG isel matcher, ~300 from ARM, ~840 from Hexagon. by Craig Topper · 12 years ago
- 44fee4e Remove several unused variables. by Rafael Espindola · 12 years ago
- 71e8bb6 Added temp flag -misched-bench for staging in default changes. by Andrew Trick · 12 years ago
- 6f5aad7 whitespace by Andrew Trick · 12 years ago
- 5e3600c [stackprotector] Allow for copies from vreg -> vreg to be in a terminator sequence. by Michael Gottesman · 12 years ago
- 31d093c ISelDAG: spot chain cycles involving MachineNodes by Tim Northover · 12 years ago
- db3e26d Debug info: Fix PR16736 and rdar://problem/14990587. by Adrian Prantl · 12 years ago
- 1adac35 [stackprotector] When finding the split point to splice off the end of a parentmbb into a successmbb, include any DBG_VALUE MI. by Michael Gottesman · 12 years ago
- f7e1203 Remove unused variables that crept in. by Michael Gottesman · 12 years ago
- b27f0f1 Teach selectiondag how to handle the stackprotectorcheck intrinsic. by Michael Gottesman · 12 years ago
- 06c2a68 ARM: Fix more fast-isel verifier failures. by Jim Grosbach · 12 years ago
- d9c2783 Replace getValueType().getSimpleVT() with getSimpleValueType(). by Craig Topper · 12 years ago
- 0b68245 Reimplement isPotentiallyReachable to make nocapture deduction much stronger. by Nick Lewycky · 12 years ago
- 418d1d1 Reapply an improved version of r180816/180817. by Adrian Prantl · 12 years ago
- fee2a20 Simplify landing pad lowering. by Jakob Stoklund Olesen · 12 years ago
- a1f5b90 Revert r185595-185596 which broke buildbots. by Jakob Stoklund Olesen · 12 years ago
- fa6a7b9 Simplify landing pad lowering. by Jakob Stoklund Olesen · 12 years ago
- af0ad9e Use SmallVectorImpl::const_iterator instead of SmallVector to avoid specifying the vector size. by Craig Topper · 12 years ago
- a3cd350 Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change. by Bill Wendling · 12 years ago
- 0252265b Debug Info: Simplify Frame Index handling in DBG_VALUE Machine Instructions by David Blaikie · 12 years ago
- f771908 Cache the TargetLowering info object as a pointer. by Bill Wendling · 12 years ago
- 8db01cb Don't cache the TargetLoweringInfo object inside of the FunctionLowering object. by Bill Wendling · 12 years ago
- e2431c6 Track IR ordering of SelectionDAG nodes 3/4. by Andrew Trick · 12 years ago
- ef9de2a Track IR ordering of SelectionDAG nodes 2/4. by Andrew Trick · 12 years ago
- a2888e7 Temporarily revert "Change the informal convention of DBG_VALUE so that we can express a" by Adrian Prantl · 13 years ago
- 9a57664 Change the informal convention of DBG_VALUE so that we can express a by Adrian Prantl · 13 years ago
- 90dd3e7 Move TryToFoldFastISelLoad to FastISel, where it belongs. In general, I'm by Eli Bendersky · 13 years ago
- b53d896 ArrayRefize getMachineNode(). No functionality change. by Michael Liao · 13 years ago
- dbeefaa Use dbgs() consistently for -debug printouts by Eli Bendersky · 13 years ago
- 6084f45 Add some more stats for fast isel vs. SelectionDAG, w.r.t lowering function by Eli Bendersky · 13 years ago
- c2d2c89 Move SDNode order propagation to SDNodeOrdering, which also fixes a missed by Justin Holewinski · 13 years ago
- d068943 Propagate DAG node ordering during type legalization and instruction selection by Justin Holewinski · 13 years ago
- 965bd58 Reset some of the target options which affect code generation. by Bill Wendling · 13 years ago
- 7857a64 Disable statistics on Release builds and move tests that depend on -stats. by Jan Wen Voung · 13 years ago
- fdf362b ArrayRefize some code. No functionality change. by Benjamin Kramer · 13 years ago
- 40cda80 No need to go through int64 and APInt when generating a new constant. by Nadav Rotem · 13 years ago
- b1caf3c Remove duplicate line and move another closer to its actual use by Eli Bendersky · 13 years ago
- 33ebf83 A small refactoring + adding comments. by Eli Bendersky · 13 years ago
- 10d35e9 Remove unnecessary cast to void. by Eric Christopher · 13 years ago
- c29095f Silence the unused variable warning. by Nadav Rotem · 13 years ago
- 00b75dd The FastISEL should be fast. But when we record statistics we use atomic operations to increment the counters. by Nadav Rotem · 13 years ago
- 0587597 Fix wording. by Chad Rosier · 13 years ago
- a92ef4b [fast-isel] Add X86FastIsel::FastLowerArguments to handle functions with 6 or by Chad Rosier · 13 years ago
- 3489bcc [ms-inline asm] Remove a redundant call to the setHasMSInlineAsm function. by Chad Rosier · 13 years ago
- 68426c7 [ms-inline asm] Fix undefined behavior to reset hasMSInlineAsm in advance of SelectAllBasicBlocks(). by NAKAMURA Takumi · 13 years ago
- 925c9b4 [ms-inline asm] Do not omit the frame pointer if we have ms-inline assembly. by Chad Rosier · 13 years ago
- aef9c37 Use the 'target-features' and 'target-cpu' attributes to reset the subtarget features. by Bill Wendling · 13 years ago
- 615620c Currently, codegen may spent some time in SDISel passes even if an entire by Evan Cheng · 13 years ago
- d3e7355 Move TargetTransformInfo to live under the Analysis library. This no by Chandler Carruth · 13 years ago
- 42e9611 Funnel the actual TargetTransformInfo pass from the SelectionDAGISel by Chandler Carruth · 13 years ago
- 9fb823b Move all of the header files which are involved in modelling the LLVM IR by Chandler Carruth · 13 years ago
- 2705333 Use MachineInstrBuilder for PHI nodes in SelectionDAGISel. by Jakob Stoklund Olesen · 13 years ago
- df42cf3 Fall back to the selection dag isel to select tail calls. by Chad Rosier · 13 years ago
- bac8ae6 Use dyn_cast instead of isa and cast. No functionality change. by Jakub Staszak · 13 years ago
- ed0881b Use the new script to sort the includes of every file under lib. by Chandler Carruth · 13 years ago
- 108c88c misched: Allow subtargets to enable misched and dependent options. by Andrew Trick · 13 years ago
- 57e3106 Freeze the reserved registers as soon as isel is complete. by Jakob Stoklund Olesen · 13 years ago
- 04b4e83 Fix bad comment. No functional change. by Craig Topper · 13 years ago
- 7c277da Add a new optimization pass: Stack Coloring, that merges disjoint static allocations (allocas). Allocas are known to be by Nadav Rotem · 13 years ago
- cf10446 BranchProb: modify the definition of an edge in BranchProbabilityInfo to handle by Manman Ren · 13 years ago
- a538d83 Add a getName function to MachineFunction. Use it in places that previously did getFunction()->getName(). Remove includes of Function.h that are no longer needed. by Craig Topper · 13 years ago
- 3e6fa46 Fall back to selection DAG isel for calls to builtin functions. by Bob Wilson · 13 years ago
- 1af8c80 Provide function name in 'Cannot select' fatal error. by Jim Grosbach · 13 years ago
- e38859d Move lib/Analysis/DebugInfo.cpp to lib/VMCore/DebugInfo.cpp and by Bill Wendling · 13 years ago
- cec09b2 Add some constantness. No functionality change. by Jakub Staszak · 14 years ago
- d114da6 Fix PR12599. by Jakob Stoklund Olesen · 14 years ago
- e3a891c Make ISelPosition a local variable. by Jakob Stoklund Olesen · 14 years ago
- beb9469 Register DAGUpdateListeners with SelectionDAG. by Jakob Stoklund Olesen · 14 years ago
- ba0a6ca Always compute all the bits in ComputeMaskedBits. by Rafael Espindola · 14 years ago
- 60cf03e misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles. by Andrew Trick · 14 years ago
- 5297d8d whitespace by Andrew Trick · 14 years ago
- 29d6ed6 Rename getExceptionAddressRegister() to getExceptionPointerRegister() for consistency with setExceptionPointerRegister(...). by Lang Hames · 14 years ago
- 0aef16a [unwind removal] Remove all of the code for the dead 'unwind' instruction. There by Bill Wendling · 14 years ago
- d06df96 VLIW specific scheduler framework that utilizes deterministic finite automaton (DFA). by Andrew Trick · 14 years ago
- a423765 Remove the eh.exception and eh.selector intrinsics. Also remove a hack to copy by Bill Wendling · 14 years ago
- 46a9f01 More dead code removal (using -Wunreachable-code) by David Blaikie · 14 years ago
- 9349351d Add a RegisterMaskSDNode class. by Jakob Stoklund Olesen · 14 years ago
- 09cc429 Allow targets to select source order pre-RA scheduler. by Evan Cheng · 14 years ago
- 73a3fab Add comment. by Chad Rosier · 14 years ago
- a379b181 Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch by David Blaikie · 14 years ago
- d6cb764 Allow inlining of functions with returns_twice calls, if they have the by Joerg Sonnenberger · 14 years ago
- 7bbc1e5 Update DebugLoc while merging nodes at -O0. by Devang Patel · 14 years ago
- 2f8347e [fast-isel] Guard "exhastive" fast-isel output with -fast-isel-verbose2. by Chad Rosier · 14 years ago
- bb15fec Enhance both TargetLibraryInfo and SelectionDAGBuilder so that the latter can use the former to prevent the formation of libm SDNode's when -fno-builtin is passed. by Owen Anderson · 14 years ago