1. 8b61764 [LegacyPassManager] Remove TargetMachine constructors by Francis Visoiu Mistrih · 8 years ago
  2. 86b0a54 [AMDGPU] added SIInstrInfo::getAddNoCarry() helper by Stanislav Mekhanoshin · 9 years ago
  3. dbc9ba3 Fix -Wunused-value warning by Reid Kleckner · 9 years ago
  4. d026f79 [AMDGPU] Combine DS operations with offsets bigger than byte by Stanislav Mekhanoshin · 9 years ago
  5. 6620376 [AMDGPU] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). by Eugene Zelenko · 9 years ago
  6. 116bbab [CodeGen] Rename MachineInstrBuilder::addOperand. NFC by Diana Picus · 9 years ago
  7. f867a40 [AMDGPU][CodeGen] To improve CGEMM performance: combine LDS reads. by Alexander Timofeev · 9 years ago
  8. 7b0e25b AMDGPU: Fix SILoadStoreOptimizer when writes cannot be merged due register dependencies by Nicolai Haehnle · 9 years ago
  9. 117296c Use StringRef in Pass/PassManager APIs (NFC) by Mehdi Amini · 9 years ago
  10. 9720f57 SILoadStoreOptimizer.cpp: Fix a warning in r279991. [-Wunused-variable] by NAKAMURA Takumi · 9 years ago
  11. c2ff0eb AMDGPU/SI: Improve SILoadStoreOptimizer and run it before the scheduler by Tom Stellard · 9 years ago
  12. e175d8a AMDGPU/SI: Canonicalize offset order for merged DS instructions by Tom Stellard · 9 years ago
  13. 90799ce MachineFunction: Introduce NoPHIs property by Matthias Braun · 9 years ago
  14. 0dd9ed1 Fix more dereferenced end() iterators after r278532 by Hans Wennborg · 9 years ago
  15. 03d8584 AMDGPU: Move subtarget feature checks into passes by Matt Arsenault · 9 years ago
  16. 43e92fe AMDGPU: Cleanup subtarget handling. by Matt Arsenault · 9 years ago
  17. 4897588 Delete some dead code. by Rafael Espindola · 9 years ago
  18. 7de74af Add optimization bisect opt-in calls for AMDGPU passes by Andrew Kaylor · 10 years ago
  19. ecc7cbf Test commit access by Konstantin Zhuravlyov · 10 years ago
  20. 3ac9cc6 CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFC by Duncan P. N. Exon Smith · 10 years ago
  21. 84db5d9 AMDGPU/SI: Fix read2 merging into a super register. by Matt Arsenault · 10 years ago
  22. 45bb48e R600 -> AMDGPU rename by Tom Stellard · 10 years ago[Renamed from llvm/lib/Target/R600/SILoadStoreOptimizer.cpp]
  23. 381a94a R600/SI: Remove explicit m0 operand from DS instructions by Tom Stellard · 10 years ago
  24. 799003b Re-sort includes with sort-includes.py and insert raw_ostream.h where it's used. by Benjamin Kramer · 11 years ago
  25. 065e3d4 R600/SI: Move gds operand to the end of operand list by Tom Stellard · 11 years ago
  26. 7792e32 Reuse a bunch of cached subtargets and remove getSubtarget calls by Eric Christopher · 11 years ago
  27. 0d2832a R600/SI: Fix live range error hidden by SIFoldOperands by Matt Arsenault · 11 years ago
  28. a99ada5 R600/SI: Emit s_mov_b32 m0, -1 before every DS instruction by Tom Stellard · 11 years ago
  29. da00cf5 Work around bugs in MSVC "14" CTP 3's conversion logic by Reid Kleckner · 11 years ago
  30. fe0a2e6 R600/SI: Match read2/write2 stride 64 versions by Matt Arsenault · 11 years ago
  31. 4103328 R600/SI: Add load / store machine optimizer pass. by Matt Arsenault · 11 years ago