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gerrit-public.fairphone.software / toolchain / llvm-project / 1e4d9a17c21fd5c9908024df450bae31d160ebd3 / llvm / lib / Target / ARM / ARMInstrInfo.cpp
  1. 1e4d9a1 First part of refactoring ARM addrmode2 (load/store) instructions to be more by Jim Grosbach · 15 years ago
  2. a8ad977 Slightly change the meaning of the reMaterialize target hook when the original by Jakob Stoklund Olesen · 16 years ago
  3. 047a767 Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor of by Dan Gohman · 16 years ago
  4. 6ad7da9 - Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo. by Evan Cheng · 16 years ago
  5. fe86442 Refactor code. by Evan Cheng · 16 years ago
  6. 207b246 - Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative by Evan Cheng · 16 years ago
  7. 14635da Use NEON reg-reg moves, where profitable. This reduces "domain-cross" stalls, when we used to mix vfp and neon code (the former were used for reg-reg moves) by Anton Korobeynikov · 16 years ago
  8. 73789b8 Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate the by Bob Wilson · 16 years ago
  9. 5457a96 Trim more includes. by Evan Cheng · 16 years ago
  10. 83e0d48 Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudo by Evan Cheng · 16 years ago
  11. c30d816 Fix thinko in my recent movt commit: it's not safe to remat movt, since it has input reg argument. by Anton Korobeynikov · 16 years ago
  12. 7c2b1e7 Use movt/movw pair to materialize 32 bit constants on ARMv6T2+. by Anton Korobeynikov · 16 years ago
  13. 7b26fce Rename TargetAsmInfo (and its subclasses) to MCAsmInfo. by Chris Lattner · 16 years ago
  14. f43cf70 Remove ARM specific getInlineAsmLength. We'll rely on the simpler (and faster) generic algorithm for now. If more accurate computation is needed, we'll rely on the disassembler. by Evan Cheng · 16 years ago
  15. e98a3c3 Move the getInlineAsmLength virtual method from TAI to TII, where by Chris Lattner · 16 years ago
  16. 780748d - More refactoring. This gets rid of all of the getOpcode calls. by Evan Cheng · 16 years ago
  17. 38b7eee More DCE. by Evan Cheng · 16 years ago
  18. 18688f4 Get rid of more dead code. by Evan Cheng · 16 years ago
  19. 056c669 Get rid of some more getOpcode calls. by Evan Cheng · 16 years ago
  20. c47e109 Use t2LDRi12 and t2STRi12 to load / store to / from stack frames. Eliminate more getOpcode calls. by Evan Cheng · 16 years ago
  21. f3a1fce Change Thumb2 jumptable codegen to one that uses two level jumps: by Evan Cheng · 16 years ago
  22. 6cfbe61 FLDD, FLDS, FCPYD, FCPYS, FSTD, FSTS, VMOVD, VMOVQ maps to the same instructions on all sub-targets. by Evan Cheng · 16 years ago
  23. cdd405d Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen. by David Goodwin · 16 years ago
  24. 6deba28 Fix frame index elimination to correctly handle thumb-2 addressing modes that don't allow negative offsets. During frame elimination convert *i12 opcode to a *i8 when necessary due to a negative offset. by David Goodwin · 16 years ago
  25. 8451744 Let callers decide the sub-register index on the def operand of rematerialized instructions. by Evan Cheng · 16 years ago
  26. 03ab0bb Generalize opcode selection in ARMBaseRegisterInfo. by David Goodwin · 16 years ago
  27. af7451b Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first. by David Goodwin · 16 years ago
  28. ade05a3 Checkpoint refactoring of ThumbInstrInfo and ThumbRegisterInfo into Thumb1InstrInfo, Thumb2InstrInfo, Thumb1RegisterInfo and Thumb2RegisterInfo. Move methods from ARMInstrInfo to ARMBaseInstrInfo to prepare for sharing with Thumb2. by David Goodwin · 16 years ago
  29. d379e89 Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details. by Evan Cheng · 16 years ago
  30. 28d6d87 Improve Thumb-2 jump table support. by David Goodwin · 16 years ago
  31. 27303cd Add conditional and unconditional thumb-2 branch. Add thumb-2 jump table. by David Goodwin · 16 years ago
  32. 0f2158b Simplify a bit by Anton Korobeynikov · 16 years ago
  33. a1b5b18 ARM refactoring. Step 2: split RegisterInfo by Anton Korobeynikov · 16 years ago
  34. 99152f3 Split thumb-related stuff into separate classes. by Anton Korobeynikov · 16 years ago
  35. 2e076c4 Add support for ARM's Advanced SIMD (NEON) instruction set. by Bob Wilson · 16 years ago
  36. 5d28cb2 GNU as refuses to assemble "pop {}" instruction. Do not emit such by Anton Korobeynikov · 16 years ago
  37. 0692819 Update the names of the exception handling sjlj instrinsics to by Jim Grosbach · 17 years ago
  38. f7b83c7 Change MachineInstrBuilder::addReg() to take a flag instead of a list of by Bill Wendling · 17 years ago
  39. aeca45d Add support for GCC compatible builtin setjmp and longjmp intrinsics. This is by Jim Grosbach · 17 years ago
  40. fde2110 PR2985 / <rdar://problem/6584986> by Jim Grosbach · 17 years ago
  41. 6bedd59 Wrap some lines to fix indentation problems. by Bob Wilson · 17 years ago
  42. d24b794 Fix some comments. by Bob Wilson · 17 years ago
  43. 2af1f85 Factor out the code to add a MachineOperand to a MachineInstrBuilder. by Dan Gohman · 17 years ago
  44. 7647da6 Remove refs to non-DebugLoc versions of BuildMI from ARM. by Dale Johannesen · 17 years ago
  45. 6b8c76a Eliminate a couple of non-DebugLoc BuildMI variants. Modify callers. by Dale Johannesen · 17 years ago
  46. f6d609a Move debug loc info along when the spiller creates new instructions. by Bill Wendling · 17 years ago
  47. 64dfcac Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nasty by Evan Cheng · 17 years ago
  48. 066757e Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo. by Evan Cheng · 17 years ago
  49. e3c7836 Create DebugLoc information in FastISel. Several temporary methods were by Bill Wendling · 17 years ago
  50. c544cb0 Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well. by Evan Cheng · 17 years ago
  51. d502173 Preliminary ARM debug support based on patch by Mikael of FlexyCore. by Evan Cheng · 17 years ago
  52. 3f86b51 Split foldMemoryOperand into public non-virtual and protected virtual by Dan Gohman · 17 years ago
  53. 0b27325 Add more const qualifiers. This fixes build breakage from r59540. by Dan Gohman · 17 years ago
  54. 3620e68 Minor code restructuring. No functionality change. by Evan Cheng · 17 years ago
  55. 33332bc Const-ify several TargetInstrInfo methods. by Dan Gohman · 17 years ago
  56. 0d1e9a8 Switch the MachineOperand accessors back to the short names like by Dan Gohman · 17 years ago
  57. 27fb3dc Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested by Owen Anderson · 17 years ago
  58. 4f6bf04 Convert uses of std::vector in TargetInstrInfo to SmallVector. This change had to be propoagated down into all the targets and up into all clients of this API. by Owen Anderson · 17 years ago
  59. 3b46030 Pool-allocation for MachineInstrs, MachineBasicBlocks, and by Dan Gohman · 17 years ago
  60. 7d98a48 - Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. by Evan Cheng · 17 years ago
  61. 30cc028 Make LiveVariables even more optional, by making it optional in the call to TargetInstrInfo::convertToThreeAddressInstruction by Owen Anderson · 17 years ago
  62. fb19f94 Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminating by Dan Gohman · 17 years ago
  63. ae84bbd Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented by Nicolas Geoffray · 18 years ago
  64. ed6e34f Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo. by Evan Cheng · 18 years ago
  65. 0f760df Fix "Control reaches the end of non-void function" warnings, by Chris Lattner · 18 years ago
  66. 0e7b00d Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF. by Evan Cheng · 18 years ago
  67. 6325446 Refactor code. Remove duplicated functions that basically do the same thing as by Evan Cheng · 18 years ago
  68. 3a4be0f Rename MRegisterInfo to TargetRegisterInfo. by Dan Gohman · 18 years ago
  69. 3b3286d It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned. by Evan Cheng · 18 years ago
  70. 1ba66e0 Remove DefInst from LiveVariables::VarInfo. Use the facilities on MachineRegisterInfo instead. by Owen Anderson · 18 years ago
  71. 5968751 rename MachineInstr::setInstrDescriptor -> setDesc by Chris Lattner · 18 years ago
  72. 7250120 Only mark instructions that load a single value without extension as isSimpleLoad = 1. by Evan Cheng · 18 years ago
  73. 03ad885 rename TargetInstrDescriptor -> TargetInstrDesc. by Chris Lattner · 18 years ago
  74. e99a6ca Rename all the M_* flags to be namespace qualified enums, and switch by Chris Lattner · 18 years ago
  75. b0d06b4 Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptor by Chris Lattner · 18 years ago
  76. f0f438a remove MachineOpCode typedef. by Chris Lattner · 18 years ago
  77. a98c679 Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflects by Chris Lattner · 18 years ago
  78. 2a3be7b Move even more functionality from MRegisterInfo into TargetInstrInfo. by Owen Anderson · 18 years ago
  79. a4ce4f6 rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate. by Chris Lattner · 18 years ago
  80. 6bb0c52 Move some more functionality from MRegisterInfo to TargetInstrInfo. by Owen Anderson · 18 years ago
  81. eee1460 Move some more instruction creation methods from RegisterInfo into InstrInfo. by Owen Anderson · 18 years ago
  82. 25568e4 Fix a problem where lib/Target/TargetInstrInfo.h would include and use by Chris Lattner · 18 years ago
  83. 7a73ae9 Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the by Owen Anderson · 18 years ago
  84. a5bb370 Add new shorter predicates for testing machine operands for various types: by Chris Lattner · 18 years ago
  85. 5c46378 Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm by Chris Lattner · 18 years ago
  86. b3fd2d7 use simplified operand addition methods. by Chris Lattner · 18 years ago
  87. f3ebc3f Remove attribution from file headers, per discussion on llvmdev. by Chris Lattner · 18 years ago
  88. 9da02f5 Remove isReg, isImm, and isMBB, and change all their users to use by Dan Gohman · 18 years ago
  89. e2f23a3 Add lengthof and endof templates that hide a lot of sizeof computations. by Owen Anderson · 18 years ago
  90. 85ee72f ARM: make branch folder remove unconditional branches by Dale Johannesen · 18 years ago
  91. 9d41b31 Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit. by Evan Cheng · 18 years ago
  92. 3650b2c Incorrect check. by Evan Cheng · 18 years ago
  93. 94f04c6 Reflects the chanegs made to PredicateOperand. by Evan Cheng · 18 years ago
  94. e8c1e42 Revert the earlier change that removed the M_REMATERIALIZABLE machine by Dan Gohman · 18 years ago
  95. 9e82064 Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad by Dan Gohman · 18 years ago
  96. a7ca624 Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit. by Evan Cheng · 18 years ago
  97. 36b1f54 Instructions with unique labels or embedded jumptables cannot be duplicated during ifcvt. by Evan Cheng · 18 years ago
  98. c685546 Handle blocks with 2 unconditional branches in AnalyzeBranch. by Dale Johannesen · 18 years ago
  99. 5514bbe Add a utility routine to check for unpredicated terminator instruction. by Evan Cheng · 18 years ago
  100. 6740da9 Fix ARM condition code subsumission check. by Evan Cheng · 18 years ago