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gerrit-public.fairphone.software / toolchain / llvm-project / 265e94e65798b24038ea01fe92ff37be550e2c9c / llvm / lib / Target / AMDGPU / AMDGPUInstrInfo.cpp
  1. 2946cd7 Update the file headers across all of the LLVM projects in the monorepo by Chandler Carruth · 7 years ago
  2. 5bfbae5 AMDGPU: Refactor Subtarget classes by Tom Stellard · 7 years ago
  3. c5a154d AMDGPU: Separate R600 and GCN TableGen files by Tom Stellard · 7 years ago
  4. 7a9c03f AMDGPU: Select MIMG instructions manually in SITargetLowering by Nicolai Haehnle · 7 years ago
  5. e741d7e AMDGPU: Use generic tables instead of SearchableTable by Nicolai Haehnle · 7 years ago
  6. f267431 AMDGPU: Turn D16 for MIMG instructions into a regular operand by Nicolai Haehnle · 7 years ago
  7. 44b30b4 AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headers by Tom Stellard · 7 years ago
  8. 5f8f34e4 Remove \brief commands from doxygen comments. by Adrian Prantl · 8 years ago
  9. 2f5a738 AMDGPU: Dimension-aware image intrinsics by Nicolai Haehnle · 8 years ago
  10. 5d0d303 AMDGPU: Make getTgtMemIntrinsic table-driven for resource-based intrinsics by Nicolai Haehnle · 8 years ago
  11. 923712b Reapply "AMDGPU: Add 32-bit constant address space" by Matt Arsenault · 8 years ago
  12. bcf7bec AMDGPU: Fix layering issue by Matt Arsenault · 8 years ago
  13. 29fcf88 AMDGPU/SI: Adjust the encoding family for D16 buffer instructions when the target has UnpackedD16VMem feature. by Changpeng Fang · 8 years ago
  14. 44dfa1d AMDGPU/SI: Add d16 support for buffer intrinsics. by Changpeng Fang · 8 years ago
  15. cad7fa8 AMDGPU: Partially fix disassembly of MIMG instructions by Matt Arsenault · 8 years ago
  16. 68f0505 AMDGPU: Fix creating invalid copy when adjusting dmask by Matt Arsenault · 8 years ago
  17. a0342dc [AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev} by Dmitry Preobrazhensky · 8 years ago
  18. 1e32550 [AMDGPU][MC][GFX9] Added 16-bit renamed and "_legacy" VALU opcodes by Dmitry Preobrazhensky · 8 years ago
  19. b62a4eb AMDGPU: Initial implementation of calls by Matt Arsenault · 8 years ago
  20. 549c89d [AMDGPU] SDWA: merge VI and GFX9 pseudo instructions by Sam Kolton · 8 years ago
  21. 1a14bfa [AMDGPU] Get address space mapping by target triple environment by Yaxun Liu · 9 years ago
  22. e823d92 AMDGPU: Merge initial gfx9 support by Matt Arsenault · 9 years ago
  23. 115efcd MachineScheduler: Export function to construct "default" scheduler. by Matthias Braun · 9 years ago
  24. d4bb5e4 AMDGPU: Enable store clustering by Matt Arsenault · 9 years ago
  25. a3ec5c1 [AMDGPU] Assembler: support v_mac_f32 DPP and SDWA. Move getNamedOperandIdx to AMDGPUBaseInfo.h by Sam Kolton · 9 years ago
  26. 52a4d9b AMDGPU: Move R600 only pieces into R600 classes by Matt Arsenault · 9 years ago
  27. 634dde3 Fix "not all control paths return a value" warning on MSVC by Simon Pilgrim · 9 years ago
  28. 43e92fe AMDGPU: Cleanup subtarget handling. by Matt Arsenault · 9 years ago
  29. e440f99 [AMDGPU] Remove exit-on-error in test (PR27761) by Diana Picus · 9 years ago
  30. 2ff7262 AMDGPU: Move subtarget specific code out of AMDGPUInstrInfo.cpp by Tom Stellard · 10 years ago
  31. 2626094 Make a bunch of static arrays const. by Craig Topper · 10 years ago
  32. 5567baf Remove redundant TargetFrameLowering::getFrameIndexOffset virtual function. by James Y Knight · 10 years ago
  33. d8a1e54 Fix broken ArrayRef conversion from r243497. by Alex Lorenz · 10 years ago
  34. ef5c196 MIR Serialization: Serialize the target index machine operands. by Alex Lorenz · 10 years ago
  35. ba51d11 Remove TargetInstrInfo::canFoldMemoryOperand by Simon Pilgrim · 10 years ago
  36. 45bb48e R600 -> AMDGPU rename by Tom Stellard · 10 years ago[Renamed from llvm/lib/Target/R600/AMDGPUInstrInfo.cpp]
  37. c88bf54 [CodeGen] ArrayRef'ize cond/pred in various TII APIs. NFC. by Ahmed Bougacha · 10 years ago
  38. e70b31f [InstrInfo] Refactor foldOperandImpl to thread through InsertPt. NFC by Keno Fischer · 10 years ago
  39. 6c5b511 Remove the need to cache the subtarget in the R600 TargetRegisterInfo classes. by Eric Christopher · 11 years ago
  40. f1362f6 ArrayRefize memory operand folding. NFC. by Benjamin Kramer · 11 years ago
  41. 970eac4 Make helper functions/classes/globals static. NFC. by Benjamin Kramer · 11 years ago
  42. 7792e32 Reuse a bunch of cached subtargets and remove getSubtarget calls by Eric Christopher · 11 years ago
  43. a93603d R600/SI: Don't shrink instructions whose e32 encoding doesn't exist by Marek Olsak · 11 years ago
  44. 5df00d6 R600/SI: Add VI instructions by Marek Olsak · 11 years ago
  45. 1f0227a R600: Remove dead code by Matt Arsenault · 11 years ago
  46. d5f4de2 R600: Increase nearby load scheduling threshold. by Matt Arsenault · 11 years ago
  47. d913448 Remove the TargetMachine forwards for TargetSubtargetInfo based by Eric Christopher · 11 years ago
  48. 620155f Remove line with no effect by Matt Arsenault · 11 years ago
  49. 034d666 R600: Implement enableClusterLoads() by Matt Arsenault · 11 years ago
  50. bc5b537 R600: Remove AMDIL instruction and register definitions by Tom Stellard · 11 years ago
  51. 2e59a45 R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtarget by Tom Stellard · 11 years ago
  52. bfd480d R600: Drop use of cached TargetMachine in AMDGPUInstrInfo.cpp by Tom Stellard · 11 years ago
  53. c721a23 R600/SI: Refactor the VOP3_32 tablegen class by Tom Stellard · 11 years ago
  54. 062a2ba [C++] Use 'nullptr'. Target edition. by Craig Topper · 12 years ago
  55. d174b72 [cleanup] Lift using directives, DEBUG_TYPE definitions, and even some by Chandler Carruth · 12 years ago
  56. e1f1da3 Fix indentation by Matt Arsenault · 12 years ago
  57. eaa3a7e Use llvm_unreachable instead of assert(0) by Matt Arsenault · 12 years ago
  58. d12ccbd [weak vtables] Remove a bunch of weak vtables by Juergen Ributzka · 12 years ago
  59. 49109a2 Revert r194865 and r194874. by Alexey Samsonov · 12 years ago
  60. dbedae8 [weak vtables] Remove a bunch of weak vtables by Juergen Ributzka · 12 years ago
  61. 81d871d R600/SI: Add support for private address space load/store by Tom Stellard · 12 years ago
  62. 9ab670f Removing a switch statement that contains only a default label. This resolves an MSVC warning. No functional change intended. by Aaron Ballman · 12 years ago
  63. 26a3b67 R600: Simplify handling of private address space by Tom Stellard · 12 years ago
  64. 682bfbc R600/SI: Define a separate MIMG instruction for each possible output value type by Tom Stellard · 12 years ago
  65. 269708b R600: Enable -verify-machineinstrs in some tests. by Vincent Lejeune · 12 years ago
  66. 02661d9 R600: Use new getNamedOperandIdx function generated by TableGen by Tom Stellard · 12 years ago
  67. a6c6e1b R600: Rework subtarget info and remove AMDILDevice classes by Tom Stellard · 12 years ago
  68. 37e9adb Don't cache the instruction and register info from the TargetMachine, because by Bill Wendling · 12 years ago
  69. 635e368 R600: Hide symbols of implementation details. by Benjamin Kramer · 12 years ago
  70. f741fbf R600/SI: add VOP mapping functions by Christian Konig · 13 years ago
  71. f3b2a1e R600: Support for indirect addressing v4 by Tom Stellard · 13 years ago
  72. 75aadc2 Add R600 backend by Tom Stellard · 13 years ago