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gerrit-public.fairphone.software / toolchain / llvm-project / 31d6d9a0fb07d39d45f051377e35fb63aa7aaff1 / llvm / lib / CodeGen / SelectionDAG / ScheduleDAGSDNodes.cpp
  1. 70573dc Update SetVector to rely on the underlying set's insert to return a pair<iterator, bool> by David Blaikie · 11 years ago
  2. 7f416c8 Convert some EVTs to MVTs where only a SimpleValueType is needed. by Craig Topper · 11 years ago
  3. e4c7be5 ScheduleDAG: record PhysReg dependencies represented by CopyFromReg nodes by Tim Northover · 11 years ago
  4. edba30c Remove more calls to getSubtargetImpl from the schedulers and by Eric Christopher · 11 years ago
  5. 25d3c1c typos by Sanjay Patel · 11 years ago
  6. eb0cc1b typos by Sanjay Patel · 11 years ago
  7. 5f5b8cc Make this SmallVector size a power of two as suggested by Chandler by Hans Wennborg · 11 years ago
  8. 01416e6 Increase the size of this SmallVector in CloneNodeWithValues. by Hans Wennborg · 11 years ago
  9. fc6de42 Have MachineFunction cache a pointer to the subtarget to make lookups by Eric Christopher · 11 years ago
  10. d913448 Remove the TargetMachine forwards for TargetSubtargetInfo based by Eric Christopher · 11 years ago
  11. 131de82 Convert SelectionDAG::MorphNodeTo to use ArrayRef. by Craig Topper · 12 years ago
  12. 1b9dde0 [Modules] Remove potential ODR violations by sinking the DEBUG_TYPE by Chandler Carruth · 12 years ago
  13. abb4ac7 Convert SelectionDAG::getVTList to use ArrayRef by Craig Topper · 12 years ago
  14. c0196b1 [C++11] More 'nullptr' conversion. In some cases just using a boolean check instead of comparing to nullptr. by Craig Topper · 12 years ago
  15. 8d007bb Put a limit on ScheduleDAGSDNodes::ClusterNeighboringLoads to avoid blowing up compile time. by Andrew Trick · 12 years ago
  16. b6d0bd4 [C++11] Replace llvm::next and llvm::prior with std::next and std::prev. by Benjamin Kramer · 12 years ago
  17. 3684fdd [PATCH] Fix PR17168 (DAG scheduler inserts DBG_VALUE before PHI with fast-isel) by Bill Schmidt · 12 years ago
  18. b12cf01 Add a function object to compare the first or second component of a std::pair. by Benjamin Kramer · 12 years ago
  19. b94011f Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size. by Craig Topper · 12 years ago
  20. c66d26a Fix PR16143: Insert DEBUG_VALUE before terminator. by Andrew Trick · 12 years ago
  21. e2431c6 Track IR ordering of SelectionDAG nodes 3/4. by Andrew Trick · 12 years ago
  22. 0539435 Change TargetLowering::getRepRegClassFor to take an MVT, instead of EVT. by Patrik Hagglund · 13 years ago
  23. e98b7a0 Revert EVT->MVT changes, r169836-169851, due to buildbot failures. by Patrik Hagglund · 13 years ago
  24. 57b1694 Change TargetLowering::getRepRegClassFor to take an MVT, instead of EVT. by Patrik Hagglund · 13 years ago
  25. ed0881b Use the new script to sort the includes of every file under lib. by Chandler Carruth · 13 years ago
  26. baeaabb ScheduleDAG interface. Added OrderKind to distinguish nonregister dependencies. by Andrew Trick · 13 years ago
  27. 839fb65 Add a really faster pre-RA scheduler (-pre-RA-sched=linearize). It doesn't use by Evan Cheng · 13 years ago
  28. 19f49ac Release build: guard dump functions with by Manman Ren · 13 years ago
  29. 742534c Release build: guard dump functions with "ifndef NDEBUG" by Manman Ren · 13 years ago
  30. 833f049 Reapply 155668: Fix the SD scheduler to avoid gluing the same node twice. by Andrew Trick · 14 years ago
  31. 7a773ec Temporarily revert r155668: Fix the SD scheduler to avoid gluing. by Andrew Trick · 14 years ago
  32. 03fa574 Fix the SD scheduler to avoid gluing the same node twice. by Andrew Trick · 14 years ago
  33. 618d573 Insert the debugging instructions in one fell-swoop so that it doesn't call the by Bill Wendling · 14 years ago
  34. 52226d4 misched preparation: rename core scheduler methods for consistency. by Andrew Trick · 14 years ago
  35. 60cf03e misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles. by Andrew Trick · 14 years ago
  36. e932bb7 misched preparation: modularize schedule emission. by Andrew Trick · 14 years ago
  37. edee68c misched preparation: modularize schedule printing. by Andrew Trick · 14 years ago
  38. 46a5866 misched preparation: modularize schedule verification. by Andrew Trick · 14 years ago
  39. 1b2324d Cleanup in preparation for misched: Move DAG visualization logic. by Andrew Trick · 14 years ago
  40. 0d639a2 Rename TargetSubtarget to TargetSubtargetInfo for consistency. by Evan Cheng · 14 years ago
  41. 8264e27 Sink SubtargetFeature and TargetInstrItineraries (renamed MCInstrItineraries) into MC. by Evan Cheng · 14 years ago
  42. 6cc775f - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and by Evan Cheng · 14 years ago
  43. 31f25bc pre-RA-sched: Cleanup register pressure tracking. by Andrew Trick · 14 years ago
  44. 99adfec The scheduler needs to be aware on the existence of untyped nodes when it performs type propagation for EXTRACT_SUBREG. by Owen Anderson · 14 years ago
  45. e1fc29b Don't allocate empty read-only SmallVectors during SelectionDAG deallocation. by Benjamin Kramer · 14 years ago
  46. 3013b6a Added -stress-sched flag in the Asserts build. by Andrew Trick · 14 years ago
  47. 1355bbd Be careful about scheduling nodes above previous calls. It increase usages of by Evan Cheng · 15 years ago
  48. 0ab5e2c Fix a ton of comment typos found by codespell. Patch by by Chris Lattner · 15 years ago
  49. bfbd972 In the pre-RA scheduler, maintain cmp+br proximity. by Andrew Trick · 15 years ago
  50. b53a00d Recommit r129383. PreRA scheduler heuristic fixes: VRegCycle, TokenFactor latency. by Andrew Trick · 15 years ago
  51. 1b60ad6 Revert 129383. It causes some targets to hit a scheduler assert. by Andrew Trick · 15 years ago
  52. c5dd24a PreRA scheduler heuristic fixes: VRegCycle, TokenFactor latency. by Andrew Trick · 15 years ago
  53. 2ad0b37 Added a check in the preRA scheduler for potential interference on a by Andrew Trick · 15 years ago
  54. 072ed2e Improve pre-RA-sched register pressure tracking for duplicate operands. by Andrew Trick · 15 years ago
  55. 7238cba Fix some latent bugs if the nodes are unschedulable. We'd gotten away by Eric Christopher · 15 years ago
  56. d7f4c21 Fix for -sched-high-latency-cycles in sched=list-ilp mode. by Andrew Trick · 15 years ago
  57. 641e2d4 Increased the register pressure limit on x86_64 from 8 to 12 by Andrew Trick · 15 years ago
  58. d0548ae Introducing a new method of tracking register pressure. We can't by Andrew Trick · 15 years ago
  59. 3f924e4 whitespace by Andrew Trick · 15 years ago
  60. 92b7077 Reapply 124301 by Devang Patel · 15 years ago
  61. b370bf3 Revert 124301. by Devang Patel · 15 years ago
  62. 9d4eb2f Process valid SDDbgValues even if the node does not have any order assigned. by Devang Patel · 15 years ago
  63. 1448e7c Refactor. by Devang Patel · 15 years ago
  64. 04b649d This assertion is too restrictive, it does not apply for dangling dbg value nodes (nodes where dbg.value intrinsic preceds use of the value). by Devang Patel · 15 years ago
  65. 11a3381 flags -> glue for selectiondag by Chris Lattner · 15 years ago
  66. 3e5fbd7 rename MVT::Flag to MVT::Glue. "Flag" is a terrible name for by Chris Lattner · 15 years ago
  67. debf9c5 Two sets of changes. Sorry they are intermingled. by Evan Cheng · 15 years ago
  68. 6c1414f Avoiding overly aggressive latency scheduling. If the two nodes share an by Evan Cheng · 15 years ago
  69. ff31073 Re-commit 117518 and 117519 now that ARM MC test failures are out of the way. by Evan Cheng · 15 years ago
  70. e2c211c Revert 117518 and 117519 for now. They changed scheduling and cause MC tests to fail. Ugh. by Evan Cheng · 15 years ago
  71. 523fa3a Fix a major bug in operand latency computation. The use index must be adjusted by Evan Cheng · 15 years ago
  72. 49d4c0b - Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This by Evan Cheng · 15 years ago
  73. 4a010fd Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMP by Evan Cheng · 15 years ago
  74. bf40707 Teach if-converter to be more careful with predicating instructions that would by Evan Cheng · 15 years ago
  75. 23ef829 Add missing null check reported by Amaury Pouly. by Evan Cheng · 15 years ago
  76. a64a323 Fix a bug in the code which re-inserts DBG_VALUE nodes after scheduling; by Dan Gohman · 15 years ago
  77. d7b5ce3 Reapply bottom-up fast-isel, with several fixes for x86-32: by Dan Gohman · 15 years ago
  78. 6586e9b --- Reverse-merging r107947 into '.': by Bob Wilson · 15 years ago
  79. 0b5aa1c Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emitting by Dan Gohman · 15 years ago
  80. caf9b3a grammar tweak in comment. by Jim Grosbach · 15 years ago
  81. 38a7d7c Add a VT argument to getMinimalPhysRegClass and replace the copy related uses by Rafael Espindola · 15 years ago
  82. 2dc70be Remove variables which are assigned to but for which the value by Duncan Sands · 15 years ago
  83. 2d3c490 It's possible that a flag is added to the SDNode that points back to the by Bill Wendling · 15 years ago
  84. a136521 MorphNodeTo doesn't preserve the memory operands. Because we're morphing a node by Bill Wendling · 15 years ago
  85. dd41bba Use A.append(...) instead of A.insert(A.end(), ...) when A is a by Dan Gohman · 15 years ago
  86. 38f6560 Code refactoring, no functionality changes. by Evan Cheng · 15 years ago
  87. cc2efe1 Fix some latency computation bugs: if the use is not a machine opcode do not just return zero. by Evan Cheng · 15 years ago
  88. 4401f88 Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode. by Evan Cheng · 15 years ago
  89. bdd062d Add a hybrid bottom up scheduler that reduce register usage while avoiding by Evan Cheng · 15 years ago
  90. 70e506e Code clean up. by Evan Cheng · 15 years ago
  91. 25c1653 Get rid of the EdgeMapping map. Instead, just check for BasicBlock by Dan Gohman · 16 years ago
  92. 8acc8f7 EmitDbgValue doesn't need its EdgeMapping argument. by Dan Gohman · 16 years ago
  93. e098352 Add DBG_VALUE handling for byval parameters; this by Dale Johannesen · 16 years ago
  94. ed69b38 - Move TargetLowering::EmitTargetCodeForFrameDebugValue to TargetInstrInfo and rename it to emitFrameIndexDebugValue. by Evan Cheng · 16 years ago
  95. 1f0f214 Fix -Wcast-qual warnings. by Dan Gohman · 16 years ago
  96. 1889440 Scheduler assumes SDDbgValue nodes are in source order. That's true currently. But add an assertion to verify it. by Evan Cheng · 16 years ago
  97. 08b3364 Remove a fixme that doesn't make sense any more. by Evan Cheng · 16 years ago
  98. 563fe3c Change how dbg_value sdnodes are converted into machine instructions. Their placement should be determined by the relative order of incoming llvm instructions. The scheduler will now use the SDNode ordering information to determine where to insert them. A dbg_value instruction is inserted after the instruction with the last highest source order and before the instruction with the next highest source order. It will optimize the placement by inserting right after the instruction that produces the value if they have consecutive order numbers. by Evan Cheng · 16 years ago
  99. 00fd0b6 Rename SDDbgValue.h to SDNodeDbgValue.h for consistency. by Evan Cheng · 16 years ago
  100. 49de060 Progress towards shepherding debug info through SelectionDAG. by Dale Johannesen · 16 years ago