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gerrit-public.fairphone.software / toolchain / llvm-project / 369bddf5ad8cb1543d38d4afd12cce768292114a / llvm / utils / TableGen / CodeGenTarget.cpp
  1. 6b3396f Don't allow per-register spill size and alignment. by Jakob Stoklund Olesen · 15 years ago
  2. 0e34c1d Prefer cheap registers for busy live ranges. by Jakob Stoklund Olesen · 15 years ago
  3. eb52c23 Make the register enum value part of the CodeGenRegister struct. by Jim Grosbach · 15 years ago
  4. f910bf2 Trailing whitespace. by Jim Grosbach · 15 years ago
  5. 2a0a3b4 Flag -> Glue, the ongoing saga by Chris Lattner · 15 years ago
  6. 3e5fbd7 rename MVT::Flag to MVT::Glue. "Flag" is a terrible name for by Chris Lattner · 15 years ago
  7. 89dcb68 various cleanups to tblgen, patch by Garrison Venn! by Chris Lattner · 15 years ago
  8. 77d369c eliminate the Records global variable, patch by Garrison Venn! by Chris Lattner · 15 years ago
  9. 77d3ead a bunch of random cleanup, move a helper to CGT where it belongs. by Chris Lattner · 15 years ago
  10. a397716 eliminate the old InstFormatName which is always "AsmString", by Chris Lattner · 15 years ago
  11. 0e023ea fix a long standing wart: all the ComplexPattern's were being by Chris Lattner · 15 years ago
  12. 3538021 Add an MVT::x86mmx type. It will take the place of all current MMX vector types. by Bill Wendling · 15 years ago
  13. 02b701f Fix whitespace, because I'm OCD. by Bill Wendling · 15 years ago
  14. ddb2d65 Remove IntrWriteMem, as it's the default. Rename IntrWriteArgMem by Dan Gohman · 15 years ago
  15. 499f797 Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission and by Bill Wendling · 15 years ago
  16. 676a15b Add a new target independent COPY instruction and code to lower it. by Jakob Stoklund Olesen · 15 years ago
  17. 3b1657b Clean up TargetOpcodes.h a bit, and limit the number of places where the full by Jakob Stoklund Olesen · 15 years ago
  18. d1d7ed6 Add StringRef::compare_numeric and use it to sort TableGen register records. by Jakob Stoklund Olesen · 15 years ago
  19. edab242 Replace the tablegen RegisterClass field SubRegClassList with an alist-like data by Jakob Stoklund Olesen · 15 years ago
  20. 670a410 Adding a v8i64 512-bit vector type. This will be used to model ARM NEON intrinsics which translate into a pair of vld / vst instructions that can load / store 8 consecutive 64-bit (D) registers. by Evan Cheng · 15 years ago
  21. 6656153 Add a pseudo instruction REG_SEQUENCE that takes a list of registers and by Evan Cheng · 15 years ago
  22. 4a5f7be fix CodeGenTarget::getRegisterVTs to not return the by Chris Lattner · 16 years ago
  23. b424faa reject void in intrinsic type lists. by Chris Lattner · 16 years ago
  24. 2109cb4 Change intrinsic result type for void to store it as an empty list by Chris Lattner · 16 years ago
  25. 3e2bb70 Revert r99009 temporarily it seems to be breaking the bots. by Eric Christopher · 16 years ago
  26. 933b2cf Change intrinsic result type for void to store it as an empty list by Chris Lattner · 16 years ago
  27. 83aeaab add a new SDNPVariadic SDNP node flag, and use it in by Chris Lattner · 16 years ago
  28. 1802b17 Finally change the instruction looking map to be a densemap from by Chris Lattner · 16 years ago
  29. 4763dbe make inst_begin/inst_end iterate over InstructionsByEnumValue. by Chris Lattner · 16 years ago
  30. 2d822ab revert 98912 by Chris Lattner · 16 years ago
  31. 45e2fc5 make inst_begin/inst_end iterate over InstructionsByEnumValue. by Chris Lattner · 16 years ago
  32. 918be52 change Target.getInstructionsByEnumValue to return a reference by Chris Lattner · 16 years ago
  33. c9ae94c factor copy and paste code. by Chris Lattner · 16 years ago
  34. 9aec14b look up instructions by record, not by name. by Chris Lattner · 16 years ago
  35. cabe037 Completely rewrite tblgen's type inference mechanism, by Chris Lattner · 16 years ago
  36. b06015a move target-independent opcodes out of TargetInstrInfo by Chris Lattner · 16 years ago
  37. 881ba0b Remove DEBUG_DECLARE, looks like we don't need it. by Dale Johannesen · 16 years ago
  38. 237254d Add DEBUG_DECLARE. Not used yet. by Dale Johannesen · 16 years ago
  39. 8f04740 Add DEBUG_VALUE. Not used yet. by Dale Johannesen · 16 years ago
  40. b91411c Remove the CPAttrParentAsRoot code, which is unused, and inconvenient by Dan Gohman · 16 years ago
  41. dc9efe8 Introduce the TargetInstrInfo::KILL machine instruction and get rid of the by Jakob Stoklund Olesen · 16 years ago
  42. 9f94459 Split EVT into MVT and EVT, the former representing _just_ a primitive type, while by Owen Anderson · 16 years ago
  43. 781797f Fix a few more places in TableGen that need to handle EVT::vAny types. by Bob Wilson · 16 years ago
  44. 2cd5da8 Add a new overloaded EVT::vAny type for use in TableGen to allow intrinsic by Bob Wilson · 16 years ago
  45. 53aa7a9 Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. by Owen Anderson · 16 years ago
  46. 0033199 Match X86 register names to number. by Daniel Dunbar · 16 years ago
  47. 9ad1594 Remove the v3i32 and v3f32 value types: they are not by Duncan Sands · 16 years ago
  48. c6026b5 Revert 75308. by Bob Wilson · 16 years ago
  49. 73fd66c Add new vector types for 192-bit, 348-bit and 512-bit sizes. by Bob Wilson · 16 years ago
  50. bf8e4c1 Refactor TableGen's llvm::getName to share code with llvm::getEnumName, by Bob Wilson · 16 years ago
  51. 5832e7f Add new ValueType for metadata. by Devang Patel · 16 years ago
  52. 38a22bf Replace std::iostreams with raw_ostream in TableGen. by Daniel Dunbar · 16 years ago
  53. f92ba97 by David Greene · 16 years ago
  54. 5234d37 Revert 72707 and 72709, for the moment. by Dale Johannesen · 16 years ago
  55. 0b8ca79 Make the implicit inputs and outputs of target-independent by Dale Johannesen · 16 years ago
  56. b8c370a Fix PR3994: LLVMMatchType arguments do not refer to absolute return value by Bob Wilson · 17 years ago
  57. 6c14263 Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalize by Dan Gohman · 17 years ago
  58. 60a446a Add a new TargetInstrInfo MachineInstr opcode, COPY_TO_SUBCLASS. by Dan Gohman · 17 years ago
  59. b842d52 Reapply 63765. Patches for clang and llvm-gcc to follow. by Dale Johannesen · 17 years ago
  60. ae616c2 Reverting 63765. This broke the build of both clang and llvm-gcc. by Dale Johannesen · 17 years ago
  61. 6ae3aa8 New feature: add support for target intrinsics being defined in the by Nate Begeman · 17 years ago
  62. 9a3113a add nocapture attribute to llvm.mem* intrinsics and have tblgen by Chris Lattner · 17 years ago
  63. f76486a Improve support for type-generic vector intrinsics by teaching TableGen how by Bob Wilson · 17 years ago
  64. a501640 Added support for vector widening. by Mon P Wang · 17 years ago
  65. 9182147 Modify the intrinsics pattern to separate out the "return" types from the by Bill Wendling · 17 years ago
  66. 3e2225d Factor the code for determining the target-specific instruction by Dan Gohman · 17 years ago
  67. b93b489 Fix the string for MVT::isVoid. by Dan Gohman · 17 years ago
  68. 2c839d4 Added support for overloading intrinsics (atomics) based on pointers by Mon P Wang · 17 years ago
  69. fb19f94 Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminating by Dan Gohman · 17 years ago
  70. 6a49037 Added MemOperands to Atomic operations since Atomics touches memory. by Mon P Wang · 17 years ago
  71. 49bad4c - Add "Commutative" property to intrinsics. This allows tblgen to generate the commuted variants for dagisel matching code. by Evan Cheng · 17 years ago
  72. 13237ac Wrap MVT::ValueType in a struct to get type safety by Duncan Sands · 17 years ago
  73. fc4ad7de Move instruction flag inference out of InstrInfoEmitter and into by Dan Gohman · 18 years ago
  74. d3d0ad3 Make insert_subreg a two-address instruction, vastly simplifying LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register. by Christopher Lamb · 18 years ago
  75. 0e7b00d Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF. by Evan Cheng · 18 years ago
  76. efd142a SDIsel processes llvm.dbg.declare by recording the variable debug information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc. by Evan Cheng · 18 years ago
  77. 0592cf7 Allow ComplexExpressions in InstrInfo.td files to be slightly more... complex! ComplexExpressions can now have attributes which affect how TableGen interprets by Christopher Lamb · 18 years ago
  78. 317332f Start inferring side effect information more aggressively, and fix many bugs in the by Chris Lattner · 18 years ago
  79. ea2d52d Split the impl of CodeGenInstruction out to its own .cpp file, add a getName() accessor. by Chris Lattner · 18 years ago
  80. 8cab021 change getQualifiedName to be a global function. by Chris Lattner · 18 years ago
  81. 8adcd9f remove attributions from utils. by Chris Lattner · 18 years ago
  82. cb77f04 Add flags to indicate that there are "never" side effects or that there "may be" by Bill Wendling · 18 years ago
  83. 687567b Oops. Forgot these. by Evan Cheng · 18 years ago
  84. 933b5b7 Add a flag for indirect branch instructions. by Owen Anderson · 18 years ago
  85. 25a00a6 Add sqrt and powi intrinsics for long double. by Dale Johannesen · 18 years ago
  86. f73fb62 Add CopyCost to TargetRegisterClass. This specifies the cost of copying a value by Evan Cheng · 18 years ago
  87. febf946 Add MVT::fAny for overloading intrinsics on floating-point types. by Dan Gohman · 18 years ago
  88. 7132e00 This is the patch to provide clean intrinsic function overloading support in LLVM. It cleans up the intrinsic definitions and generally smooths the process for more complicated intrinsic writing. It will be used by the upcoming atomic intrinsics as well as vector and float intrinsics in the future. by Chandler Carruth · 18 years ago
  89. cde0ee5 Add target independent MachineInstr's to represent subreg insert/extract in MBB's. PR1350 by Christopher Lamb · 18 years ago
  90. c9ea294 Teach TableGen about the new vector types. by Christopher Lamb · 18 years ago
  91. 869852b No need for noResults anymore. by Evan Cheng · 18 years ago
  92. 94b5a80 Change instruction description to split OperandList into OutOperandList and by Evan Cheng · 18 years ago
  93. 10835d9 Eliminate an unused parameter. by Dan Gohman · 18 years ago
  94. 6e3c705 Try committing again. Add OptionalDefOperand. Remove clobbersPred. by Evan Cheng · 18 years ago
  95. 9835db5 ImmutablePredicateOperand is no more. by Evan Cheng · 18 years ago
  96. e32e7fb Instructions with ImmutablePredicateOperand aren't really predicable since their predicates are fixed at isel time. by Evan Cheng · 18 years ago
  97. e8c1e42 Revert the earlier change that removed the M_REMATERIALIZABLE machine by Dan Gohman · 18 years ago
  98. 9e82064 Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad by Dan Gohman · 18 years ago
  99. a7ca624 Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit. by Evan Cheng · 18 years ago
  100. f274efe Add support to tablegen for specifying subregister classes on a per register class basis. by Christopher Lamb · 18 years ago