Log - 3b36bb1d8780caeb122ee86cf2f44e397cb028ea - toolchain/llvm-project

3b36bb1 AMDGPU: Enable ConstrainCopy DAG mutation by Matt Arsenault · 9 years ago
d4bb5e4 AMDGPU: Enable store clustering by Matt Arsenault · 9 years ago
f42454b Move the global variables representing each Target behind accessor function by Mehdi Amini · 9 years ago
6bc43d8 BranchRelaxation: Support expanding unconditional branches by Matt Arsenault · 9 years ago
60a8373 [AMDGPU] Pass optimization level to SelectionDAGISel by Konstantin Zhuravlyov · 9 years ago
4658e5f [AMDGPU] Do not run scalar optimization passes at "-O0" by Konstantin Zhuravlyov · 9 years ago
e674075 AMDGPU: Partially fix control flow at -O0 by Matt Arsenault · 9 years ago
0efdd06 AMDGPU: Run LoadStoreVectorizer pass by default by Matt Arsenault · 9 years ago
0d23ebe AMDGPU/SI: Implement a custom MachineSchedStrategy by Tom Stellard · 9 years ago
c2ff0eb AMDGPU/SI: Improve SILoadStoreOptimizer and run it before the scheduler by Tom Stellard · 9 years ago
78fc9da AMDGPU: Split SILowerControlFlow into two pieces by Matt Arsenault · 9 years ago
67fc52f [PM] Port the always inliner to the new pass manager in a much more by Chandler Carruth · 9 years ago
e0b8718 [AMDGPU] Remove duplicate initialization of SIDebuggerInsertNops pass by Konstantin Zhuravlyov · 9 years ago
2ffe8fd AMDGPU: Prune includes by Matt Arsenault · 9 years ago
6756a2c [GlobalISel] Introduce an instruction selector. by Ahmed Bougacha · 9 years ago
33b07d6 GlobalISel: implement legalization pass, with just one transformation. by Tim Northover · 9 years ago
a1fe17c AMDGPU: Change fdiv lowering based on !fpmath metadata by Matt Arsenault · 9 years ago
ca7f570 AMDGPU/R600: Delete/rename intrinsics no longer used by mesa by Matt Arsenault · 9 years ago
418beb7 AMDGPU/SI: Add support for R_AMDGPU_GOTPCREL by Tom Stellard · 9 years ago
908b9e2 AMDGPU: Add option to run the load/store vectorizer by Matt Arsenault · 9 years ago
eb9025d AMDGPU: Fix global isel crashes by Matt Arsenault · 9 years ago
254a645 AMDGPU: Fix typo by Matt Arsenault · 9 years ago
55dff27 AMDGPU: Fix global isel build by Matt Arsenault · 9 years ago
59c0ffa AMDGPU: Implement per-function subtargets by Matt Arsenault · 9 years ago
03d8584 AMDGPU: Move subtarget feature checks into passes by Matt Arsenault · 9 years ago
86de486 AMDGPU: Add stub custom CodeGenPrepare pass by Matt Arsenault · 9 years ago
c581611 AMDGPU: Remove disable-irstructurizer subtarget feature by Matt Arsenault · 9 years ago
43e92fe AMDGPU: Cleanup subtarget handling. by Matt Arsenault · 9 years ago
4a07bf6 AMDGPU: Run verifier after 2nd run of SIShrinkInstructions by Matt Arsenault · 9 years ago
9babdf4 AMDGPU: Fix verifier errors in SILowerControlFlow by Matt Arsenault · 9 years ago
f42c692 AMDGPU: Run pointer optimization passes by Matt Arsenault · 9 years ago
e2bd9a3 AMDGPU: Run verifer after insert waits pass by Matt Arsenault · 9 years ago
c3a01ec AMDGPU: Properly initialize SIShrinkInstructions by Matt Arsenault · 9 years ago
8e00194 AMDGPU: Fix crashes on unknown processor name by Matt Arsenault · 9 years ago
d3e4c64 AMDGPU: SIDebuggerInsertNops preserves CFG by Matt Arsenault · 9 years ago
ec30eb5 AMDGPU: Remove unused address space by Matt Arsenault · 9 years ago
8c34dd8 Delete Reloc::Default. by Rafael Espindola · 9 years ago
bde8034 AMDGPU: Don't run passes that aren't useful by Matt Arsenault · 9 years ago
a791932 [AMDGPU][NFC] Rename SIInsertNops -> SIDebuggerInsertNops by Konstantin Zhuravlyov · 9 years ago
31d19d4 CodeGen: Move TargetPassConfig from Passes.h to an own header; NFC by Matthias Braun · 9 years ago
fcfaea4 AMDGPU/SI: Add support for AMD code object version 2. by Tom Stellard · 10 years ago
cb6ba62 AMDGPU/SI: Enable the post-ra scheduler by Tom Stellard · 10 years ago
cf2744f AMDGPU/SI: Move post regalloc run of SIShrinkInstructions by Matt Arsenault · 10 years ago
a40d835 [AMDGPU] Insert nop pass: take care of outstanding feedback by Konstantin Zhuravlyov · 10 years ago
8c273ad [AMDGPU] Add insert nops pass based on subtarget features instead of cl::opt by Konstantin Zhuravlyov · 10 years ago
3d1c1de AMDGPU: Run SIFoldOperands after PeepholeOptimizer by Matt Arsenault · 10 years ago
000c5af AMDGPU: Add skeleton GlobalIsel implementation by Tom Stellard · 10 years ago
723b73b AMDGPU: Remove SIFixSGPRLiveRanges pass by Nicolai Haehnle · 10 years ago
213e87f AMDGPU: Add SIWholeQuadMode pass by Nicolai Haehnle · 10 years ago
6b6a2c3 AMDGPU: R600 code splitting cleanup by Matt Arsenault · 10 years ago
cc7067a6 AMDGPU: Insert two S_NOP instructions for every high level source statement. by Tom Stellard · 10 years ago
bc4497b AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions by Tom Stellard · 10 years ago
55d49cf AMDGPU: Initialize SILowerControlFlow by Matt Arsenault · 10 years ago
5dde1d2 AMDGPU: Fix ordering of CPU and FS parameters in TargetMachine constructors by Tom Stellard · 10 years ago
6e1967e AMDGPU/SI: Correctly initialize SIInsertWaits pass by Tom Stellard · 10 years ago
8b17567 AMDGPU: Skip promote alloca with no optimizations by Matt Arsenault · 10 years ago
e013246 AMDGPU: Fix emitting invalid workitem intrinsics for HSA by Matt Arsenault · 10 years ago
b22828f AMDGPU: Fix default device handling by Matt Arsenault · 10 years ago
de008d3 AMDGPU/SI: Pass whether to use the SI scheduler via Target Attribute by Tom Stellard · 10 years ago
77a1777 Correctly initialize SIAnnotateControlFlow by Tom Stellard · 10 years ago
02c3291 AMDGPU/SI: Add SI Machine Scheduler by Nicolai Haehnle · 10 years ago
a6f24c6 AMDGPU/SI: Select constant loads with non-uniform addresses to MUBUF instructions by Tom Stellard · 10 years ago
c93fc11 AMDGPU/SI: Emit constant arrays in the .text section by Tom Stellard · 10 years ago
0e3d389 AMDGPU: Remove SIPrepareScratchRegs by Matt Arsenault · 10 years ago
3931948 AMDGPU: Add pass to detect used kernel features by Matt Arsenault · 10 years ago
782c03b AMDGPU: Initialize SIFixSGPRCopies so -print-after works by Matt Arsenault · 10 years ago
8c0ef8b AMDGPU: Register some more passes so -print-before works by Matt Arsenault · 10 years ago
468c998 CodeGen: print and verify after TargetPassConfig::insertPass by default by Justin Bogner · 10 years ago
187276f AMDGPU: Properly register passes by Matt Arsenault · 10 years ago
b87fc22 AMDGPU: Move SIFixSGPRLiveRanges to be a regalloc pass by Matt Arsenault · 10 years ago
e135ffd AMDGPU/SI: Use .hsatext section instead of .text for HSA by Tom Stellard · 10 years ago
0a10900 AMDGPU: Disable some passes that are not meaningful by Matt Arsenault · 10 years ago
a4e5d3c constify the Function parameter to the TTI creation callback and by Eric Christopher · 10 years ago
c8d8e4e AMDGPU: Make sure to run verifier after SIFixSGPRLiveRanges by Matt Arsenault · 10 years ago
fd25395 AMDGPU: Add pass to lower OpenCL image and sampler arguments. by Tom Stellard · 10 years ago
84db5d9 AMDGPU/SI: Fix read2 merging into a super register. by Matt Arsenault · 10 years ago
5010ebf Make TargetTransformInfo keeping a reference to the Module DataLayout by Mehdi Amini · 10 years ago
db7781c AMDGPU: Run SIInsertWaits as pre-emit pass by Matt Arsenault · 10 years ago
45bb48e R600 -> AMDGPU rename by Tom Stellard · 10 years ago[Renamed (99%) from llvm/lib/Target/R600/AMDGPUTargetMachine.cpp]
3e5de88 Replace string GNU Triples with llvm::Triple in TargetMachine. NFC. by Daniel Sanders · 10 years ago
ed64d62 Replace string GNU Triples with llvm::Triple in computeDataLayout(). NFC. by Daniel Sanders · 10 years ago
a73f1fd Replace string GNU Triples with llvm::Triple in MCSubtargetInfo and create*MCSubtargetInfo(). NFC. by Daniel Sanders · 10 years ago
28d13a4 R600/SI: add pass to mark CF live ranges as non-spillable by Tom Stellard · 10 years ago
8024d03 Grab a subtarget off of an AMDGPUTargetMachine rather than a by Eric Christopher · 11 years ago
93e1ea1 Move the DataLayout to the generic TargetMachine, making it mandatory. by Mehdi Amini · 11 years ago
30d69c2 [PM] Remove the old 'PassManager.h' header file at the top level of by Chandler Carruth · 11 years ago
de5b7b1 R600: Split AMDGPUPassConfig into R600PassConfig and GCNPassConfig by Tom Stellard · 11 years ago
c65b360 R600: Create an R600TargetMachine for pre-gcn GPUs by Tom Stellard · 11 years ago
8b04c0d [multiversion] Switch all of the targets over to use the by Chandler Carruth · 11 years ago
93dcdc4 [PM] Switch the TargetMachine interface from accepting a pass manager by Chandler Carruth · 11 years ago
705b185 [PM] Change the core design of the TTI analysis to use a polymorphic by Chandler Carruth · 11 years ago
40ce8af R600: Move DataLayout to AMDGPUTargetMachine by Tom Stellard · 11 years ago
42fb60e R600/SI: Spill VGPRs to scratch space for compute shaders by Tom Stellard · 11 years ago
49f8bfd R600/SI: Add a stub GCNTargetMachine by Tom Stellard · 11 years ago
7e37a5f [CodeGen] Add print and verify pass after each MachineFunctionPass by default by Matthias Braun · 11 years ago
01c7361 This reverts commit r224043 and r224042. by Rafael Espindola · 11 years ago
a7c82a9 [CodeGen] Add print and verify pass after each MachineFunctionPass by default by Matthias Braun · 11 years ago
05cd445 R600/SI: Move SIInsertWaits into AMDGPUPassConfig::addPreSched2() by Tom Stellard · 11 years ago
92105e8 R600/SI: Don't run SI passes on R600 subtargets by Tom Stellard · 11 years ago
691ae3d R600/SI: Fix running SILowerI1Copies a second time by Matt Arsenault · 11 years ago