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gerrit-public.fairphone.software / toolchain / llvm-project / 481cdab9199e6459d074da14cf1818c40b9cec16 / llvm / lib / Target / AMDGPU / R600Packetizer.cpp
  1. c5a154d AMDGPU: Separate R600 and GCN TableGen files by Tom Stellard · 7 years ago
  2. 44b30b4 AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headers by Tom Stellard · 7 years ago
  3. d34e60c Rename DEBUG macro to LLVM_DEBUG. by Nicola Zaghen · 7 years ago
  4. a2f57be AMDGPU/R600: Initialize more passes by Tom Stellard · 8 years ago
  5. 6bda14b Sort the remaining #include lines in include/... and lib/.... by Chandler Carruth · 8 years ago
  6. 8b61764 [LegacyPassManager] Remove TargetMachine constructors by Francis Visoiu Mistrih · 8 years ago
  7. e995a808 Fix spelling mistakes in AMDGPU target comments. NFC. by Simon Pilgrim · 9 years ago
  8. 117296c Use StringRef in Pass/PassManager APIs (NFC) by Mehdi Amini · 9 years ago
  9. 9cfc75c CodeGen: Use MachineInstr& in TargetInstrInfo, NFC by Duncan P. N. Exon Smith · 9 years ago
  10. 43e92fe AMDGPU: Cleanup subtarget handling. by Matt Arsenault · 9 years ago
  11. 8e00194 AMDGPU: Fix crashes on unknown processor name by Matt Arsenault · 9 years ago
  12. 8226fc4 AMDGPU: Simplify boolean conditional return statements by Matt Arsenault · 10 years ago
  13. 5702287 CodeGen: Update DFAPacketizer API to take MachineInstr&, NFC by Duncan P. N. Exon Smith · 10 years ago
  14. 6307eb5 CodeGen: TII: Take MachineInstr& in predicate API, NFC by Duncan P. N. Exon Smith · 10 years ago
  15. d84f600 CodeGen: Bring back MachineBasicBlock::iterator::getInstrIterator()... by Duncan P. N. Exon Smith · 10 years ago
  16. c5b668d Revert "CodeGen: MachineInstr::getIterator() => getInstrIterator(), NFC" by Duncan P. N. Exon Smith · 10 years ago
  17. dac7102 [Packetizer] Add AliasAnalysis as a parameter to the packetizer by Krzysztof Parzyszek · 10 years ago
  18. d44a1fd Add "const" to function arguments in DFAPacketizer by Krzysztof Parzyszek · 10 years ago
  19. 93563e7 ScheduleDAGInstrs: Remove IsPostRA flag; NFC by Matthias Braun · 10 years ago
  20. a73371a AMDGPU: Remove implicit ilist iterator conversions, NFC by Duncan P. N. Exon Smith · 10 years ago
  21. 45bb48e R600 -> AMDGPU rename by Tom Stellard · 10 years ago[Renamed from llvm/lib/Target/R600/R600Packetizer.cpp]
  22. 7792e32 Reuse a bunch of cached subtargets and remove getSubtarget calls by Eric Christopher · 11 years ago
  23. ea0aee6 Cleanup: Delete seemingly unused reference to MachineDominatorTree from ScheduleDAGInstrs. by Alexey Samsonov · 11 years ago
  24. fc6de42 Have MachineFunction cache a pointer to the subtarget to make lookups by Eric Christopher · 11 years ago
  25. d913448 Remove the TargetMachine forwards for TargetSubtargetInfo based by Eric Christopher · 11 years ago
  26. 2e59a45 R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtarget by Tom Stellard · 11 years ago
  27. 5656db4 [C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. R600 edition by Craig Topper · 12 years ago
  28. 84e68b2 [Modules] Fix potential ODR violations by sinking the DEBUG_TYPE by Chandler Carruth · 12 years ago
  29. b6d0bd4 [C++11] Replace llvm::next and llvm::prior with std::next and std::prev. by Benjamin Kramer · 12 years ago
  30. cb40291 Fix known typos by Alp Toker · 12 years ago
  31. 26a3b67 R600: Simplify handling of private address space by Tom Stellard · 12 years ago
  32. ed0ceec R600: Use StructurizeCFGPass for non SI targets by Tom Stellard · 12 years ago
  33. 7f6fa4c R600: Don't use trans slot for instructions that read LDS source registers by Tom Stellard · 12 years ago
  34. 7e2c832 R600: Non vector only instruction can be scheduled on trans unit by Vincent Lejeune · 12 years ago
  35. ca69a53 Revert "R600: Non vector only instruction can be scheduled on trans unit" by Tom Stellard · 12 years ago
  36. df18804 R600: Non vector only instruction can be scheduled on trans unit by Vincent Lejeune · 12 years ago
  37. 21de8ba R600: Don't mix LDS and non-LDS instructions in the same group by Vincent Lejeune · 12 years ago
  38. ce49974 R600: Do not predicated basic block with multiple alu clause by Vincent Lejeune · 12 years ago
  39. 77a8352 R600: Support schedule and packetization of trans-only inst by Vincent Lejeune · 12 years ago
  40. c026e8b R600: Add local memory support via LDS by Tom Stellard · 12 years ago
  41. ce54033 R600: Add support for GROUP_BARRIER instruction by Tom Stellard · 12 years ago
  42. 02661d9 R600: Use new getNamedOperandIdx function generated by TableGen by Tom Stellard · 12 years ago
  43. 91a942b R600: 3 op instructions have no write bit but the result are store in PV by Vincent Lejeune · 12 years ago
  44. d78bb46 Move passes from namespace llvm into anonymous namespaces. Sort includes while there. by Benjamin Kramer · 12 years ago
  45. 519f21e R600: Relax some vector constraints on Dot4. by Vincent Lejeune · 12 years ago
  46. 0fca91d R600: Some factorization by Vincent Lejeune · 12 years ago
  47. 2a44ae0 R600: If previous bundle is dot4, PV valid chan is always X by Vincent Lejeune · 13 years ago
  48. 147700b R600: Packetize instructions by Vincent Lejeune · 13 years ago