- 358c3d1 Do not emit copies for physical register output if it's not used. by Evan Cheng · 18 years ago
- c5549fc Instead of adding copyfromreg's to handle physical definitions. Now isel can by Evan Cheng · 18 years ago
- 18603b0 Teach DAG scheduling how to properly emit subreg insert/extract machine instructions. PR1350 by Christopher Lamb · 18 years ago
- 2182f06 Skeleton of post-RA scheduler; doesn't do anything yet. by Dale Johannesen · 18 years ago
- 5e90842 If the operand is marked M_OPTIONAL_DEF_OPERAND, then it's a def. by Evan Cheng · 18 years ago
- ff6f279 When a node value is only used by a CopyToReg, use the user's dest. This should not be restricted to nodes that produce only a single value. by Evan Cheng · 18 years ago
- 642be16 Change CalculateHeights and CalculateDepths to be non-recursive. by Evan Cheng · 18 years ago
- a7644dd Pass a SelectionDAG into SDNode::dump everywhere it's used, in prepration by Dan Gohman · 18 years ago
- 1baf5c8 Fix some VC++ warnings. by Jeff Cohen · 19 years ago
- 971aa18 Code clean up. by Lauro Ramos Venancio · 19 years ago
- 25878b4 CopyToReg source operand can be a physical register. by Lauro Ramos Venancio · 19 years ago
- 56e5fea print target nodes nicely by Chris Lattner · 19 years ago
- 68dcec6 fix indentation by Chris Lattner · 19 years ago
- 21ebae3 Apply B Scott Michel's patch for PR1184, which improves diagnostics in an by Chris Lattner · 19 years ago
- 09575ba For PR1195: by Reid Spencer · 19 years ago
- 19083a4 switch the VRBaseMap in the scheduler from an std::map to a DenseMap. This by Chris Lattner · 19 years ago
- f9e5445 Make LABEL a builtin opcode. by Jim Laskey · 19 years ago
- f5c96fa Renamed getTypeAlignmentShift() to getPreferredTypeAlignmentShift(). by Evan Cheng · 19 years ago
- be48a47 Remove the DoubleTy special case. by Evan Cheng · 19 years ago
- a8a0f2c Compensate for loss of DerivedTypes.h in TargetLowering.h by Reid Spencer · 19 years ago
- 376c9c4 CopyToReg source operand can be a register as well. e.g. Copy from GlobalBaseReg. by Evan Cheng · 19 years ago
- 22e978a Removing even more <iostream> includes. by Bill Wendling · 19 years ago
- 67fc141 Match TargetInstrInfo changes. by Evan Cheng · 19 years ago
- 20350c4 Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead by Evan Cheng · 19 years ago
- dbd3d29 Matches MachineInstr changes. by Evan Cheng · 19 years ago
- 979bbf4 Add methods to add implicit def use operands to a MI. by Evan Cheng · 19 years ago
- 8c9c6d7 Add implicit def / use operands to MachineInstr. by Evan Cheng · 19 years ago
- fd2c5dd Changes to use operand constraints to process two-address instructions. by Evan Cheng · 19 years ago
- 1fd360e handle global address constant sdnodes by Chris Lattner · 19 years ago
- 47fbeda Debug tweak. by Evan Cheng · 19 years ago
- 45fe3bc Added support for machine specific constantpool values. These are useful for by Evan Cheng · 19 years ago
- af23f9b Completely eliminate def&use operands. Now a register operand is EITHER a by Chris Lattner · 19 years ago
- d86418a switch the SUnit pred/succ sets from being std::sets to being smallvectors. by Chris Lattner · 19 years ago
- 1640ae5 Reverse the FlaggedNodes after scanning up for flagged preds or else the order would be reversed. by Evan Cheng · 19 years ago
- 4e153f1 Use an enumeration to eliminate data relocations. by Jim Laskey · 19 years ago
- f7300b2 It was pointed out that DEBUG() is only available with -debug. by Jim Laskey · 19 years ago
- c3d341e Ensure that dump calls that are associated with asserts are removed from by Jim Laskey · 19 years ago
- 55772cc Instructions with variable operands (variable_ops) can have a number required by Evan Cheng · 19 years ago
- 0c0996a commuteInstruction() does not always create a new MI! by Evan Cheng · 20 years ago
- 9d91caa Eliminate a memory leak. by Evan Cheng · 20 years ago
- d8e2f6e lib/Target/Target.td by Evan Cheng · 20 years ago
- 957cb67 Move function-live-in-handling code from the sdisel code to the scheduler. by Chris Lattner · 20 years ago
- 99f2f79 Fixing 2006-05-01-SchedCausingSpills.ll; some clean up by Evan Cheng · 20 years ago
- 8c2c1e9 Refactor a bunch of includes so that TargetMachine.h doesn't have to include by Owen Anderson · 20 years ago
- 095c9d9 Duh. That could take a long time. by Evan Cheng · 20 years ago
- afed73e Add capability to scheduler to commute nodes for profit. by Evan Cheng · 20 years ago
- d38c22b Refactor scheduler code. Move register-reduction list scheduler to a by Evan Cheng · 20 years ago
- 469647b Remove and simplify some more machineinstr/machineoperand stuff. by Chris Lattner · 20 years ago
- 10b71c0 Rename MO_VirtualRegister -> MO_Register. Clean up immediate handling. by Chris Lattner · 20 years ago
- 940cc97 Remove a bunch more SparcV9 specific stuff by Chris Lattner · 20 years ago
- 20a631f Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference. by Owen Anderson · 20 years ago
- 4ca2ea5 JumpTable support! What this represents is working asm and jit support for by Nate Begeman · 20 years ago
- 87b1ddd fix spello by Chris Lattner · 20 years ago
- 6b20104 TargetData doesn't know the alignment of vectors :( by Chris Lattner · 20 years ago
- a5b93b8 Move some simple-sched-specific instance vars to the simple scheduler. by Chris Lattner · 20 years ago
- e015178 prune #includes by Chris Lattner · 20 years ago
- 4b70ff7 move some simple scheduler methods into the simple scheduler by Chris Lattner · 20 years ago
- dc2f135 Make EmitNode take a SDNode instead of a NodeInfo* by Chris Lattner · 20 years ago
- b9d8fa0 Move the VRBase field from NodeInfo to being a separate, explicit, map. by Chris Lattner · 20 years ago
- 2f8c7c3 Push PrepareNodeInfo/IdentifyGroups down the inheritance hierarchy by Chris Lattner · 20 years ago
- 543832d Change the interface for getting a target HazardRecognizer to be more clean. by Chris Lattner · 20 years ago
- 2d945ba When a hazard recognizer needs noops to be inserted, do so. This represents by Chris Lattner · 20 years ago
- ed169db Added an offset field to ConstantPoolSDNode. by Evan Cheng · 20 years ago
- 5af3fde Pass all the flags to the asm printer, not just the # operands. by Chris Lattner · 20 years ago
- 2f8a794 rename NumOps -> NumVals to avoid shadowing a NumOps var in an outer scope. by Chris Lattner · 20 years ago
- 86c5100 Refactor operand adding out to a new AddOperand method by Chris Lattner · 20 years ago
- 571d964 Record all of the expanded registers in the DAG and machine instr, fixing by Chris Lattner · 20 years ago
- 4576bb7 Make MachineConstantPool entries alignments explicit by Chris Lattner · 20 years ago
- 95ae171 Fix VC++ warning. by Jeff Cohen · 20 years ago
- f9adce9 Get rid of some memory leaks identified by Valgrind by Evan Cheng · 20 years ago
- 3b48431 Add initial support for immediates. This allows us to compile this: by Chris Lattner · 20 years ago
- 32be2dc Allow the specification of explicit alignments for constant pool entries. by Evan Cheng · 20 years ago
- 2e56e89 Handle physreg input/outputs. We now compile this: by Chris Lattner · 20 years ago
- 4df279c Teach the scheduler to emit the appropriate INLINEASM MachineInstr for an by Chris Lattner · 20 years ago
- 1880f8d No need to keep track of top and bottom nodes in a group since the vector is by Evan Cheng · 20 years ago
- fbc88a6 Keep track of bottom / top element of a set of flagged nodes. by Evan Cheng · 20 years ago
- c1e1d97 Factor out more instruction scheduler code to the base class. by Evan Cheng · 20 years ago
- 739a6a4 Do some code refactoring on Jim's scheduler in preparation of the new list by Evan Cheng · 20 years ago
- fb6a914 purity++ by Duraid Madina · 20 years ago
- 9e296be Disengage DEBUG_LOC from non-PPC targets. by Jim Laskey · 20 years ago
- 9b9688a Amend comment. by Jim Laskey · 20 years ago
- ce23987 Create a strong dependency for loads following stores. This will leave a by Jim Laskey · 20 years ago
- c7cb351 Keep VC++ happy. by Jeff Cohen · 20 years ago
- c97b7d0 Fix a bug Sabre was having where the DAG root was a group. The group dominator by Jim Laskey · 20 years ago
- e220821 Groups were not emitted if the dominator node and the node in the ordering list by Jim Laskey · 20 years ago
- cf12118 Simplify code by Chris Lattner · 20 years ago
- 006bb04 Support multiple ValueTypes per RegisterClass, needed for upcoming vector by Nate Begeman · 20 years ago
- 0e0de2f Added an index field to GlobalAddressSDNode so it can represent X+12, etc. by Evan Cheng · 20 years ago
- bf4f2332 Switch the allnodes list from a vector of pointers to an ilist of nodes.This eliminates the vector, allows constant time removal of a node froma graph, and makes iteration over the all nodes list stable when adding by Chris Lattner · 20 years ago
- 3ba38cb Explicitly initialize some instance vars by Chris Lattner · 20 years ago
- 1d2f26a Let's try ignoring resource utilization on the backward pass. by Jim Laskey · 20 years ago
- 904dbb4 Fix logic bug in finding retry slot in tally. by Jim Laskey · 20 years ago
- ded4759 Fix a warning by Jim Laskey · 20 years ago
- e682b67 Scheduling now uses itinerary data. by Jim Laskey · 20 years ago
- 5ce0538 by Jim Laskey · 20 years ago
- dd5663d Reduce the number of copies emitted as machine instructions by by Chris Lattner · 20 years ago
- 5d7a50a Inhibit instructions from being pushed before function calls. This will by Jim Laskey · 20 years ago
- 63b1419 Finally committing to the new scheduler. Still -sched=none by default. by Jim Laskey · 20 years ago
- 0832f26 When emiting a CopyFromReg and the source is already a vreg, do not bother by Chris Lattner · 20 years ago
- 327d429 Reverting to version - until problem isolated. by Jim Laskey · 20 years ago