Log - 68f9accf51a0f718bf1d6c41d543be5ee37eccd7 - toolchain/llvm-project

0cd23f56 [CodeGen] Rename DEBUG_TYPE to match passnames by Evandro Menezes · 8 years ago
6bda14b Sort the remaining #include lines in include/... and lib/.... by Chandler Carruth · 8 years ago
9cfc75c CodeGen: Use MachineInstr& in TargetInstrInfo, NFC by Duncan P. N. Exon Smith · 9 years ago
43e92fe AMDGPU: Cleanup subtarget handling. by Matt Arsenault · 9 years ago
180e0d5 AMDGPU: Fix gcc warnings by Matt Arsenault · 9 years ago
45bb48e R600 -> AMDGPU rename by Tom Stellard · 10 years ago[Renamed from llvm/lib/Target/R600/R600MachineScheduler.cpp]
0795a2e Remove a few more calls to TargetMachine::getSubtarget from the R600 port. by Eric Christopher · 11 years ago
30d69c2 [PM] Remove the old 'PassManager.h' header file at the top level of by Chandler Carruth · 11 years ago
7792e32 Reuse a bunch of cached subtargets and remove getSubtarget calls by Eric Christopher · 11 years ago
cce5701 Fix float division-by-zero in R600 scheduler. by Alexey Samsonov · 11 years ago
efb3d53 R600: Remove unused include by Matt Arsenault · 11 years ago
2e59a45 R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtarget by Tom Stellard · 11 years ago
062a2ba [C++] Use 'nullptr'. Target edition. by Craig Topper · 12 years ago
84e68b2 [Modules] Fix potential ODR violations by sinking the DEBUG_TYPE by Chandler Carruth · 12 years ago
d7f890e Factor MI-Sched in preparation for post-ra scheduling support. by Andrew Trick · 12 years ago
8f9fc20 R600: Fix scheduling of instructions that use the LDS output queue by Tom Stellard · 12 years ago
7f6fa4c R600: Don't use trans slot for instructions that read LDS source registers by Tom Stellard · 12 years ago
7e2c832 R600: Non vector only instruction can be scheduled on trans unit by Vincent Lejeune · 12 years ago
ca69a53 Revert "R600: Non vector only instruction can be scheduled on trans unit" by Tom Stellard · 12 years ago
df18804 R600: Non vector only instruction can be scheduled on trans unit by Vincent Lejeune · 12 years ago
77a8352 R600: Support schedule and packetization of trans-only inst by Vincent Lejeune · 12 years ago
c026e8b R600: Add local memory support via LDS by Tom Stellard · 12 years ago
ce54033 R600: Add support for GROUP_BARRIER instruction by Tom Stellard · 12 years ago
d1a9d18 R600: Use a refined heuristic to choose when switching clause by Vincent Lejeune · 12 years ago
a6c6e1b R600: Rework subtarget info and remove AMDILDevice classes by Tom Stellard · 12 years ago
54476a1 R600: Remove leftover code in R600MachineScheduler.cpp by Vincent Lejeune · 12 years ago
4b5b849 R600: Schedule copy from phys register at beginning of block by Vincent Lejeune · 12 years ago
aad5376 R600: Make sure to schedule AR register uses and defs in the same clause by Tom Stellard · 12 years ago
d78bb46 Move passes from namespace llvm into anonymous namespaces. Sort includes while there. by Benjamin Kramer · 12 years ago
3d5118c R600: Use bottom up scheduling algorithm by Vincent Lejeune · 12 years ago
4c81d4d R600: Use depth first scheduling algorithm by Vincent Lejeune · 12 years ago
e958c8e R600: Replace big texture opcode switch in scheduler by usesTC/usesVC by Vincent Lejeune · 12 years ago
519f21e R600: Relax some vector constraints on Dot4. by Vincent Lejeune · 12 years ago
f9f4e1e R600: Factorize Fetch size limit inside AMDGPUSubTarget by Vincent Lejeune · 12 years ago
80031d9f R600: Factorize maximum alu per clause in a single location by Vincent Lejeune · 13 years ago
0a22bc4 R600: Factorize code handling Const Read Port limitation by Vincent Lejeune · 13 years ago
756cf88 R600MachineScheduler.cpp: Fix use cases of dbgs(). Don't include <iostream> here. by NAKAMURA Takumi · 13 years ago
68b6b6d R600: initial scheduler code by Vincent Lejeune · 13 years ago