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gerrit-public.fairphone.software / toolchain / llvm-project / 708a91a10366f0aa8f2b3912dd8e047ca1a66e5b / llvm / test / CodeGen / AMDGPU / ds-negative-offset-addressing-mode-loop.ll
  1. e4d0c14 AMDGPU: Add sdst operand to VOP2b instructions by Matt Arsenault · 10 years ago
  2. 706f930 AMDGPU/SI: Add debugging subtarget feature for DS offsets by Matt Arsenault · 10 years ago
  3. 45bb48e R600 -> AMDGPU rename by Tom Stellard · 10 years ago[Renamed from llvm/test/CodeGen/R600/ds-negative-offset-addressing-mode-loop.ll]
  4. 1f3416a R600/SI: Don't print offset0/offset1 DS operands when they are 0 by Tom Stellard · 11 years ago
  5. a79ac14 [opaque pointer type] Add textual IR support for explicit type parameter to load instruction by David Blaikie · 11 years ago
  6. 79e6c74 [opaque pointer type] Add textual IR support for explicit type parameter to getelementptr instruction by David Blaikie · 11 years ago
  7. 49f8bfd R600/SI: Add a stub GCNTargetMachine by Tom Stellard · 11 years ago
  8. 326d6ec R600/SI: Change all instruction assembly names to lowercase. by Tom Stellard · 11 years ago
  9. 61cc908 R600/SI: Change how DS offsets are printed by Matt Arsenault · 11 years ago
  10. 4103328 R600/SI: Add load / store machine optimizer pass. by Matt Arsenault · 11 years ago
  11. 79243d9 R600: Call EmitFunctionHeader() in the AsmPrinter to populate the ELF symbol table by Tom Stellard · 11 years ago
  12. 85e8b6d R600/SI: Use a ComplexPattern for DS loads and stores by Tom Stellard · 11 years ago
  13. 5015a89 R600/SI: Implement isLegalAddressingMode by Matt Arsenault · 11 years ago