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gerrit-public.fairphone.software / toolchain / llvm-project / 72a9d15aba28a07c93abf18222b51f0afcd365ed / llvm / lib / Target / ARM / Thumb2InstrInfo.cpp
  1. 6307eb5 CodeGen: TII: Take MachineInstr& in predicate API, NFC by Duncan P. N. Exon Smith · 10 years ago
  2. e40c8a2 PseudoSourceValue: Replace global manager with a manager in a machine function. by Alex Lorenz · 10 years ago
  3. e9119e4 MC: Modernize MCOperand API naming. NFC. by Jim Grosbach · 10 years ago
  4. 0a90504 [ARM] Do not generate invalid encoding for stack adjust, even if this is just by Quentin Colombet · 11 years ago
  5. 3408583 Remove the need to cache the subtarget in the ARM TargetRegisterInfo by Eric Christopher · 11 years ago
  6. 8e29dec Fix handling of negative offsets for AddrModeT2_i8s4 in rewriteT2FrameIndex. by Bob Wilson · 11 years ago
  7. 89e94fc Fix incorrect immediate size for AddrModeT2_i8s4 in rewriteT2FrameIndex. by Bob Wilson · 11 years ago
  8. dc08c30 [ARM] In dynamic-no-pic mode, ARM's post-RA pseudo expansion was incorrectly by Akira Hatanaka · 11 years ago
  9. e5b6e0d [stack protector] Fix a potential security bug in stack protector where the by Akira Hatanaka · 11 years ago
  10. a925326 Prune includes in ARM target. by Craig Topper · 12 years ago
  11. c9432eb ARM: remove unnecessary state-tracking during frame lowering. by Tim Northover · 12 years ago
  12. 87dacc3 Add hint disassembly syntax for 16-bit Thumb hint instructions. by Richard Barton · 12 years ago
  13. 286304a Fix PR 17372: Emitting PLD for stack address for ARM Thumb2 by Weiming Zhao · 12 years ago
  14. 841a9cc Reverting 190043 for now. by Tilmann Scheller · 12 years ago
  15. a1787a5 ARM: Add GPR register class excluding LR for use with the ADR instruction. by Tilmann Scheller · 12 years ago
  16. f95178e Don't cache the instruction and register info from the TargetMachine, because by Bill Wendling · 12 years ago
  17. df1ecbd7 Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros. by Michael J. Spencer · 12 years ago
  18. 798697d ARM: Use ldrd/strd to spill 64-bit pairs when available. by Tim Northover · 13 years ago
  19. b159b5f Remove the explicit MachineInstrBuilder(MI) constructor. by Jakob Stoklund Olesen · 13 years ago
  20. 9de596e Remove all references to TargetInstrInfoImpl. by Jakob Stoklund Olesen · 13 years ago
  21. 702bcc3 Remove the TII::scheduleTwoAddrSource() hook. by Jakob Stoklund Olesen · 13 years ago
  22. c7242e0 Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent. by Craig Topper · 14 years ago
  23. 1fcf5bc Prune some includes by Craig Topper · 14 years ago
  24. f6e7e12 Remove unnecessary llvm:: qualifications by Craig Topper · 14 years ago
  25. 188ed9d Reorder includes to match coding standards. Fix an issue or two exposed by that. by Craig Topper · 14 years ago
  26. 617f84dd ARM implement TargetInstrInfo::getNoopForMachoTarget() by Jim Grosbach · 14 years ago
  27. b22310f Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. by Jia Liu · 14 years ago
  28. 4fad5b2 Handle regmask operands in ARMInstrInfo. by Jakob Stoklund Olesen · 14 years ago
  29. 465101b Make use of MachinePointerInfo::getFixedStack. This removes all mention by Jay Foad · 14 years ago
  30. 1b8457a Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode. by Jim Grosbach · 14 years ago
  31. 12d13ef Handle new register classes in Thumb2 mode. Should fix the ARM buildbots. by Owen Anderson · 14 years ago
  32. a20cde3 Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ARM MC code from target. by Evan Cheng · 14 years ago
  33. e9cc901 Refact ARM Thumb1 tMOVr instruction family. by Jim Grosbach · 14 years ago
  34. b98ab91 Thumb1 register to register MOV instruction is predicable. by Jim Grosbach · 14 years ago
  35. cfe3b14 Kill dead code. by Jim Grosbach · 14 years ago
  36. a8a8067 Remove redundant Thumb2 ADD/SUB SP instruction definitions. by Jim Grosbach · 14 years ago
  37. 1e210d0 Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc by Evan Cheng · 14 years ago
  38. 6cc775f - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and by Evan Cheng · 14 years ago
  39. e7410dd Preliminary support for ARM frame save directives emission via MI flags. by Anton Korobeynikov · 15 years ago
  40. 666cf56 Guard against de-referencing MBB.end(). by Evan Cheng · 15 years ago
  41. 87a9f19 Skipping over debugvalue instructions to determine whether the split spot is in a IT block. rdar://9030770 by Evan Cheng · 15 years ago
  42. 62c7b5b Making use of VFP / NEON floating point multiply-accumulate / subtraction is by Evan Cheng · 15 years ago
  43. debf9c5 Two sets of changes. Sorry they are intermingled. by Evan Cheng · 15 years ago
  44. f31f33e Thread the determination of branch prediction hit rates back through the if-conversion heuristic APIs. For now, by Owen Anderson · 15 years ago
  45. 671d578 Provide an option to restore old-style if-conversion heuristics for Thumb2. by Owen Anderson · 15 years ago
  46. 88af7d0 Part one of switching to using a more sane heuristic for determining if-conversion profitability. by Owen Anderson · 15 years ago
  47. e3d864b convert targets to the new MF.getMachineMemOperand interface. by Chris Lattner · 15 years ago
  48. bf40707 Teach if-converter to be more careful with predicating instructions that would by Evan Cheng · 15 years ago
  49. d343166 Many Thumb2 instructions can reference the full ARM register set (i.e., by Jim Grosbach · 15 years ago
  50. d7b3300 Replace copyRegToReg with copyPhysReg for ARM. by Jakob Stoklund Olesen · 15 years ago
  51. 83b993a The t2MOVi16 and t2MOVTi16 instructions do not set CPSR. Trying to add by Bob Wilson · 15 years ago
  52. 0c30739 Change if-cvt options to something that actually as useable. by Evan Cheng · 15 years ago
  53. 02b184d Change if-conversion block size limit checks to add some flexibility. by Evan Cheng · 15 years ago
  54. 37bb617 Tail merging pass shall not break up IT blocks. rdar://8115404 by Evan Cheng · 15 years ago
  55. 2d51c7c Allow ARM if-converter to be run after post allocation scheduling. by Evan Cheng · 15 years ago
  56. 44f9dfc Next round of tail call changes. Register used in a tail by Dale Johannesen · 15 years ago
  57. a0746bd Allow target to place 2-address pass inserted copies in better spots. Thumb2 will use this to try to avoid breaking up IT blocks. by Evan Cheng · 15 years ago
  58. 84511e1 Clean up 80 column violations. No functional change. by Jim Grosbach · 15 years ago
  59. 779c69b Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it by Dan Gohman · 16 years ago
  60. efb126a Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot. by Evan Cheng · 16 years ago
  61. 25f8594 Handle register-to-register copies within the tGPR class. Radar 7896289 by Bob Wilson · 16 years ago
  62. 6f306d7 use DebugLoc default ctor instead of DebugLoc::getUnknownLoc() by Chris Lattner · 16 years ago
  63. 44313db Thumb2 storeFrom/LoadToStackSlot() need to handle tGPR regs directly, not pass by Jim Grosbach · 16 years ago
  64. 0bfbd9b Fix a crash compiling 254.gap for Thumb2. The Thumb2 add/sub with 12-bit by Bob Wilson · 16 years ago
  65. 5638c36 Handle AddrMode6 (for NEON load/stores) in Thumb2's rewriteT2FrameIndex. by Bob Wilson · 16 years ago
  66. bdc17f6 Remove predicates when changing an add into an unpredicable mov. by Jakob Stoklund Olesen · 16 years ago
  67. 047a767 Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor of by Dan Gohman · 16 years ago
  68. fe86442 Refactor code. by Evan Cheng · 16 years ago
  69. 4e9f379 80-column cleanup of file header comments by Jim Grosbach · 16 years ago
  70. 8b5278a t2ldrpci_pic can be used for blockaddress as well. by Evan Cheng · 16 years ago
  71. a8e8a7c Refactor code. Fix a potential missing check. Teach isIdentical() about tLDRpci_pic. by Evan Cheng · 16 years ago
  72. 7ff8319 - Add TargetInstrInfo::isIdentical(). It's similar to MachineInstr::isIdentical by Evan Cheng · 16 years ago
  73. 207b246 - Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative by Evan Cheng · 16 years ago
  74. 14635da Use NEON reg-reg moves, where profitable. This reduces "domain-cross" stalls, when we used to mix vfp and neon code (the former were used for reg-reg moves) by Anton Korobeynikov · 16 years ago
  75. 1a4492b Fix a couple more places where we are creating ld / st instructions without memoperands. by Evan Cheng · 16 years ago
  76. 73789b8 Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate the by Bob Wilson · 16 years ago
  77. 967bf27 Handle AddrMode4 for Thumb2 in rewriteT2FrameIndex. This occurs for by Bob Wilson · 16 years ago
  78. 7a37b1a Fix PR4789. Teach eliminateFrameIndex how to handle VLDRQ and VSTRQ which cannot fold any immediate offset. by Evan Cheng · 16 years ago
  79. f24f9d9 Whitespace cleanup. Remove trailing whitespace. by Jim Grosbach · 16 years ago
  80. 5b4c308 Always use the 16-bit tMOVgpr2gpr instead of the 32-bit t2MOVr. by Evan Cheng · 16 years ago
  81. f0237b1 Use 16-bit tMOVgpr2gpr instead of tMOVr to copy GPR registers in Thumb2 mode. by Evan Cheng · 16 years ago
  82. b972e56 It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing. by Evan Cheng · 16 years ago
  83. 8b9deeb Use the i12 variant of load / store opcodes if offset is zero. Now we pass all of multisource as well. by Evan Cheng · 16 years ago
  84. e98a3c3 Move the getInlineAsmLength virtual method from TAI to TII, where by Chris Lattner · 16 years ago
  85. c6d70ae Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword. by Evan Cheng · 16 years ago
  86. 0830980 Thumb-2: fix typo that caused incorrect stack elimination for VFP operations and very large stack frames. by David Goodwin · 16 years ago
  87. 780748d - More refactoring. This gets rid of all of the getOpcode calls. by Evan Cheng · 16 years ago
  88. 38b7eee More DCE. by Evan Cheng · 16 years ago
  89. 18688f4 Get rid of more dead code. by Evan Cheng · 16 years ago
  90. 056c669 Get rid of some more getOpcode calls. by Evan Cheng · 16 years ago
  91. c47e109 Use t2LDRi12 and t2STRi12 to load / store to / from stack frames. Eliminate more getOpcode calls. by Evan Cheng · 16 years ago
  92. 186332f Use the right instructions to copy between GPR and the more strictive tGPR classes. t2MOV does not match the RC requirements. by Evan Cheng · 16 years ago
  93. c1a5cfa Get rid of a couple of unnecessary getOpcode calls. by Evan Cheng · 16 years ago
  94. f3a1fce Change Thumb2 jumptable codegen to one that uses two level jumps: by Evan Cheng · 16 years ago
  95. 886f303 Clean up. by Evan Cheng · 16 years ago
  96. 6cfbe61 FLDD, FLDS, FCPYD, FCPYS, FSTD, FSTS, VMOVD, VMOVQ maps to the same instructions on all sub-targets. by Evan Cheng · 16 years ago
  97. cdd405d Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen. by David Goodwin · 16 years ago
  98. 6deba28 Fix frame index elimination to correctly handle thumb-2 addressing modes that don't allow negative offsets. During frame elimination convert *i12 opcode to a *i8 when necessary due to a negative offset. by David Goodwin · 16 years ago
  99. c5df7e2 Emit cross regclass register moves for thumb2. Minor code duplication cleanup. by Anton Korobeynikov · 16 years ago
  100. cd4cdd1 Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically. by Evan Cheng · 16 years ago