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gerrit-public.fairphone.software / toolchain / llvm-project / 73158e72012c88e8e9a6b2bc9f9d36868e43d8e7 / llvm / lib / CodeGen / SelectionDAG / LegalizeVectorOps.cpp
  1. ae527ac [Intrinsic] Expand SMULFIX to MUL, MULH[US], or [US]MUL_LOHI on vector arguments by Leonard Chan · 7 years ago
  2. 2946cd7 Update the file headers across all of the LLVM projects in the monorepo by Chandler Carruth · 7 years ago
  3. d3b86b7 Reapply "[CodeGen][X86] Expand USUBSAT to UMAX+SUB, also for vectors" by Nikita Popov · 7 years ago
  4. 5885eec Revert "[CodeGen][X86] Expand USUBSAT to UMAX+SUB, also for vectors" by Nikita Popov · 7 years ago
  5. 8e9a843 [CodeGen][X86] Expand USUBSAT to UMAX+SUB, also for vectors by Nikita Popov · 7 years ago
  6. ca0de03 [X86][AARCH64] Improve ISD::ABS support by Simon Pilgrim · 7 years ago
  7. 57fc891 [LegalizeVectorOps] Add FSHL/FSHR to the list of vector operations that should be handled. by Craig Topper · 7 years ago
  8. 77fc551 [TargetLowering] Add ISD::ROTL/ROTR vector expansion by Simon Pilgrim · 7 years ago
  9. 118e53f [Intrinsic] Signed Fixed Point Multiplication Intrinsic by Leonard Chan · 7 years ago
  10. 180639a [SelectionDAG] Initial support for FSHL/FSHR funnel shift opcodes (PR39467) by Simon Pilgrim · 7 years ago
  11. cd8a152 Remove superfluous comments. NFCI. by Simon Pilgrim · 7 years ago
  12. 129d529 [SelectionDAG][AArch64][X86] Move legalization of vector MULHS/MULHU from LegalizeDAG to LegalizeVectorOps by Craig Topper · 7 years ago
  13. 9e97054 [LegalizeVectorOps] After custom legalizing an extending load or a truncating store, make sure the custom code is also legal. by Craig Topper · 7 years ago
  14. 9757d5d [FPEnv] Add constrained CEIL/FLOOR/ROUND/TRUNC intrinsics by Cameron McInally · 7 years ago
  15. 1ba8618 [SelectionDAG] Remove special methods for creating *_EXTEND_VECTOR_INREG nodes. Move asserts into getNode. by Craig Topper · 7 years ago
  16. b34a052 [LegalizeDAG] Add generic vector CTPOP expansion (PR32655) by Simon Pilgrim · 7 years ago
  17. 2ad870e [FPEnv] [FPEnv] Add constrained intrinsics for MAXNUM and MINNUM by Cameron McInally · 7 years ago
  18. 905abe5 [Intrinsic] Signed and Unsigned Saturation Subtraction Intirnsics by Leonard Chan · 7 years ago
  19. 9b77f0c [VectorLegalizer] Enable TargetLowering::expandFP_TO_UINT support. by Simon Pilgrim · 7 years ago
  20. 838eb24 [TargetLowering] Improve vXi64 UINT_TO_FP vXf64 support (P38226) by Simon Pilgrim · 7 years ago
  21. 30f1d69 [NFC] Rename minnan and maxnan to minimum and maximum by Thomas Lively · 7 years ago
  22. d705ba9 [LegalizeDAG] Share Vector/Scalar CTLZ Expansion by Simon Pilgrim · 7 years ago
  23. 1e212e8 [LegalizeDAG] Remove unused variable by Benjamin Kramer · 7 years ago
  24. b975ff4 [LegalizeDAG] Share Vector/Scalar CTTZ Expansion by Simon Pilgrim · 7 years ago
  25. 0acfc6b [Intrinsic] Unigned Saturation Addition Intrinsic by Leonard Chan · 7 years ago
  26. 687ec75 DAG: Change behavior of fminnum/fmaxnum nodes by Matt Arsenault · 7 years ago
  27. 699b3b5 [Intrinsic] Signed Saturation Addition Intrinsic by Leonard Chan · 7 years ago
  28. 1c2051e [X86][SSE] Begin removing vector CTTZ custom lowering and use LegalizeDAG instead. by Simon Pilgrim · 7 years ago
  29. b926fd7 Pull out repeated value types. NFCI. by Simon Pilgrim · 7 years ago
  30. b8339c0 [SelectionDAG] Move VectorLegalizer::ExpandCTLZ codegen into SelectionDAGLegalize by Simon Pilgrim · 7 years ago
  31. cd38de8 [LegalizeDAG] Move legalization of scatter and masked store from LegalizeVectorOps to LegalizeDAG. by Craig Topper · 7 years ago
  32. e4d199e [LegalizeVectorOps] Make ExpandStrictFPOp return the result corresponding to the result number of the SDValue passed in. by Craig Topper · 7 years ago
  33. 7d2155e [X86][LegalizeVectorOps] Use MERGE_VALUES to return two results from LowerLoad. Remove special case code in LegalizeVectorOps that allowed us to only return one result. by Craig Topper · 7 years ago
  34. 94b9029 [FPEnv] Support constrained FREM intrinsic by Cameron McInally · 7 years ago
  35. f78650a Remove trailing space by Fangrui Song · 7 years ago
  36. 5f75371 Fix corruption of result number in LegalizeVectorOps.cpp by Ulrich Weigand · 7 years ago
  37. eac2ca4 [Legalize] Elide MERGE_VALUES created by scalarizeVectorLoad. by Nirav Dave · 7 years ago
  38. 7caac67 [FPEnv] Expand constrained FP POWI by Cameron McInally · 7 years ago
  39. f37bd01 [FPEnv] Expand constrained FP operations by Cameron McInally · 7 years ago
  40. d34e60c Rename DEBUG macro to LLVM_DEBUG. by Nicola Zaghen · 7 years ago
  41. 5f8f34e4 Remove \brief commands from doxygen comments. by Adrian Prantl · 8 years ago
  42. 540512c DAG: Fix not legalizing vector fcanonicalizes by Matt Arsenault · 8 years ago
  43. 2fa1436 [IR][CodeGen] Remove dependency on EVT from IR/Function.cpp. Move EVT to CodeGen layer. by Craig Topper · 8 years ago
  44. 36a0f22 Fix layering by moving ValueTypes.h from CodeGen to IR by David Blaikie · 8 years ago
  45. 13e77db Fix layering of MachineValueType.h by moving it from CodeGen to Support by David Blaikie · 8 years ago
  46. 2f29afb [VectorLegalizer] Fix uint64_t typo in ExpandUINT_TO_FLOAT (PR36391) by Simon Pilgrim · 8 years ago
  47. 7ad2886 [SelectionDAG] Fix codegen of vector stores with non byte-sized elements. by Jonas Paulsson · 8 years ago
  48. 9b395a1 [VectorLegalizer] Remove broken code in ExpandStore. by Jonas Paulsson · 8 years ago
  49. a4f9997 [SelectionDAG][X86][AArch64] Require targets to specify the promotion type when using setOperationAction Promote for INT_TO_FP and FP_TO_INT by Craig Topper · 8 years ago
  50. d5fed99 [SelectionDAG] Add some debug print messages to LegalizeVectorOps. by Craig Topper · 8 years ago
  51. cf461a0 [SelectionDAG][X86] Teach promotion legalization for fp_to_sint/fp_to_uint to insert an assertsext/assertzext based on the original type by Craig Topper · 8 years ago
  52. b655fa9 DAG: Add nuw when splitting loads and stores by Matt Arsenault · 8 years ago
  53. 88ffb5d [X86] Mark ISD::FP_TO_UINT v16i8/v16i16 as Promote under AVX512 instead of legal. Fix infinite loop in op legalization when promotion requires 2 steps. by Craig Topper · 8 years ago
  54. b3bde2e Fix a bunch more layering of CodeGen headers that are in Target by David Blaikie · 8 years ago
  55. fb7f792 [CodeGen] Fix some Clang-tidy modernize-use-bool-literals and Include What You Use warnings; other minor fixes (NFC). by Eugene Zelenko · 8 years ago
  56. bd79f73 Added LLVM_FALLTHROUGH to address warning: this statement may fall through. NFC. by Galina Kistanova · 8 years ago
  57. 5de8dc9 DAG: Do not scalarize fsub if fneg is legal by Matt Arsenault · 9 years ago
  58. 0a5ab5c Use SelectionDAG::getBuildVector/getSplatBuildVector helper functions where possible. NFCI. by Simon Pilgrim · 9 years ago
  59. f08dc90 [SelectionDAG] Add expansion and promotion of [US]MUL_LOHI by Nicolai Haehnle · 9 years ago
  60. 5662074 [VectorLegalizer] Remove EVT::getSizeInBits code duplications. NFCI. by Simon Pilgrim · 9 years ago
  61. d02c552 [VectorLegalizer] Expansion of CTLZ using CTPOP when possible by Simon Pilgrim · 9 years ago
  62. 1ed771f getVectorElementType().getSizeInBits() -> getScalarSizeInBits() ; NFCI by Sanjay Patel · 9 years ago
  63. b1f0a0f getValueType().getSizeInBits() -> getValueSizeInBits() ; NFCI by Sanjay Patel · 9 years ago
  64. bd6fca1 getScalarType().getSizeInBits() -> getScalarSizeInBits() ; NFCI by Sanjay Patel · 9 years ago
  65. cd1d5aa Replace a few more "fall through" comments with LLVM_FALLTHROUGH by Justin Bogner · 9 years ago
  66. 9c37581 [SelectionDAG] Get rid of bool parameters in SelectionDAG::getLoad, getStore, and friends. by Justin Lebar · 9 years ago
  67. 2bd8b4b [CodeGen,Target] Remove the version of DAG.getVectorShuffle that takes a pointer to a mask array. Convert all callers to use the ArrayRef version. No functional change intended. by Craig Topper · 9 years ago
  68. 89b89650 [SelectionDAG] Attempt to split BITREVERSE vector legalization into BSWAP and BITREVERSE stages by Simon Pilgrim · 9 years ago
  69. 1f5ad70 [SelectionDAG] BITREVERSE vector legalization of bit operations (REAPPLIED) by Simon Pilgrim · 9 years ago
  70. 1a14f0d Revert r268504 by Simon Pilgrim · 10 years ago
  71. b97c062 [SelectionDAG] BITREVERSE vector legalization of bit operations by Simon Pilgrim · 10 years ago
  72. 52cb5ec [SelectionDAG] Teach LegalizeVectorOps to directly Expand CTTZ_ZERO_UNDEF/CTLZ_ZERO_UNDEF to CTTZ/CTLZ directly if those ops are Legal/Custom instead of deferring it to LegalizeOps. by Craig Topper · 10 years ago
  73. 46ba316 LegalizeDAG: Don't replace vector store with integer if not legal by Matt Arsenault · 10 years ago
  74. a4b1b6e LegalizeDAG: Don't replace vector load with integer unless legal by Matt Arsenault · 10 years ago
  75. 61eb49e [X86][SSE] Reapplied: Improve vector ZERO_EXTEND by combining to ZERO_EXTEND_VECTOR_INREG by Simon Pilgrim · 10 years ago
  76. 93cff7f [CodeGen] Document and use getConstant's splat-building feature. NFC. by Ahmed Bougacha · 10 years ago
  77. f8dfb47 [CodeGen] Prefer "if (SDValue R = ...)" to "if (R.getNode())". NFCI. by Ahmed Bougacha · 10 years ago
  78. 4b1808d [SelectionDAG] Teach LegalizeVectorOps to not unroll CTLZ_ZERO_UNDEF and CTTZ_ZERO_UNDEF if the non-ZERO_UNDEF form is legal or custom. Will be used to simplify X86 code in a follow on commit. by Craig Topper · 10 years ago
  79. d079285 AMDGPU: Use generic bitreverse intrinsic by Matt Arsenault · 10 years ago
  80. cd8664c Revert r248483, r242546, r242545, and r242409 - absdiff intrinsics by Hal Finkel · 10 years ago
  81. 33e61ec AVX-512: Fixed masked load / store instruction selection for KNL. by Elena Demikhovsky · 10 years ago
  82. 4675c43 Fix some places where we were assuming that memory type had been legalized by Eric Christopher · 10 years ago
  83. 891c097 Do not use "else" when both branches return (NFC) by Mehdi Amini · 10 years ago
  84. c736863 Two switch blocks in VectorLegalizer::LegalizeOp already have a by Artyom Skrobov · 10 years ago
  85. b844fa7 Combining DIV+REM->DIVREM doesn't belong in LegalizeDAG; move it over into DAGCombiner. by Artyom Skrobov · 10 years ago
  86. e400a7d SelectionDAG: Remove implicit ilist iterator conversions, NFC by Duncan P. N. Exon Smith · 10 years ago
  87. 13f1dfd Codegen: Fix llvm.*absdiff semantic. by Mohammad Shahid · 10 years ago
  88. a260701 propagate fast-math-flags on DAG nodes by Sanjay Patel · 10 years ago
  89. 01cdecc Add new ISD nodes: ISD::FMINNAN and ISD::FMAXNAN by James Molloy · 10 years ago
  90. 7395a81 [Codegen] Add intrinsics 'absdiff' and corresponding SDNodes for absolute difference operation by James Molloy · 10 years ago
  91. 9639d65 Make TargetLowering::getShiftAmountTy() taking DataLayout as an argument by Mehdi Amini · 10 years ago
  92. 44ede33 Make TargetLowering::getPointerTy() taking DataLayout as an argument by Mehdi Amini · 10 years ago
  93. 8ac7a9d Redirect DataLayout from TargetMachine to Module in SelectionDAG by Mehdi Amini · 10 years ago
  94. 8fc121d Convert a bunch of loops to foreach. NFC. by Pete Cooper · 10 years ago
  95. f00654e Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC) by Alexander Kornienko · 10 years ago
  96. 70bc5f1 Fixed/added namespace ending comments using clang-tidy. NFC by Alexander Kornienko · 10 years ago
  97. 7e9776b Add SDNodes for umin, umax, smin and smax. by James Molloy · 10 years ago
  98. 1b60ed7 Masked gather and scatter intrinsics - enabled codegen for KNL. by Elena Demikhovsky · 11 years ago
  99. 842a51b Reapply r235977 "[DebugInfo] Add debug locations to constant SD nodes" by Sergey Dmitrouk · 11 years ago
  100. 48e93f7 Revert "[DebugInfo] Add debug locations to constant SD nodes" by Daniel Jasper · 11 years ago