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gerrit-public.fairphone.software / toolchain / llvm-project / 73982b94e3b2c8ed30c3648128aa734b8f56b4a3 / llvm / lib / CodeGen / RegAllocLinearScan.cpp
  1. 63a8eaf Tweak to ignoring reserved regs. The allocator was occasionally still looking by Jim Grosbach · 15 years ago
  2. d5e72a1 tidy up trailing whitespace and an 80 column violation. by Jim Grosbach · 15 years ago
  3. 9dce314 cleanup per feedback. use a helper function for getting the first non-reserved by Jim Grosbach · 15 years ago
  4. 5ccf18c The register allocator shouldn't consider allocating reserved registers. by Jim Grosbach · 15 years ago
  5. 27e1f26 Clean up the Spiller.h interface. by Jakob Stoklund Olesen · 15 years ago
  6. a7aed18 Reapply r110396, with fixes to appease the Linux buildbot gods. by Owen Anderson · 15 years ago
  7. bda59bd Revert r110396 to fix buildbots. by Owen Anderson · 15 years ago
  8. 755aceb Don't use PassInfo* as a type identifier for passes. Instead, use the address of the static by Owen Anderson · 15 years ago
  9. 7383cf0 Grammar by Jim Grosbach · 15 years ago
  10. a57b97e Fix batch of converting RegisterPass<> to INTIALIZE_PASS(). by Owen Anderson · 15 years ago
  11. 0fef9dd Change the createSpiller interface to take a MachineFunctionPass argument. by Jakob Stoklund Olesen · 15 years ago
  12. a58a7e7 Spillers may alter MachineLoopInfo when breaking critical edges, so make it by Jakob Stoklund Olesen · 15 years ago
  13. 37c42a3 Remove many calls to TII::isMoveInstr. Targets should be producing COPY anyway. by Jakob Stoklund Olesen · 15 years ago
  14. 0026462 Convert EXTRACT_SUBREG to COPY when emitting machine instrs. by Jakob Stoklund Olesen · 15 years ago
  15. 5e54160 80-col fixup. by Eric Christopher · 15 years ago
  16. 2b87d44c Don't return a std::vector in the Spiller interface, but take a reference to a by Jakob Stoklund Olesen · 15 years ago
  17. 93cd0f1c improve portability to systems that don't have powf/modf (e.g. solaris 9) by Chris Lattner · 15 years ago
  18. 2104b8d rename llvm::llvm_report_error -> llvm::report_fatal_error by Chris Lattner · 16 years ago
  19. 3917008 Remove dead code by Jakob Stoklund Olesen · 16 years ago
  20. 025e934 Change errs() to dbgs(). by David Greene · 16 years ago
  21. 740ab38 Fix a bunch of little errors that Clang complains about when its being pedantic by Douglas Gregor · 16 years ago
  22. d17e296 Moved spill weight calculation out of SimpleRegisterCoalescing and into its own pass: CalculateSpillWeights. by Lang Hames · 16 years ago
  23. 497161c Also attempt trivial coalescing for live intervals that end in a copy. by Jakob Stoklund Olesen · 16 years ago
  24. 1ab2b49 Added a new "splitting" spiller. by Lang Hames · 16 years ago
  25. f899862 Temporarily revert r90502. It was causing the llvm-gcc bootstrap on PPC to fail. by Bill Wendling · 16 years ago
  26. ca9cf65 Also attempt trivial coalescing for live intervals that end in a copy. by Jakob Stoklund Olesen · 16 years ago
  27. f46c37c by David Greene · 16 years ago
  28. c6e4345 Removed references to LiveStacks from Spiller.* . They're no longer needed. by Lang Hames · 16 years ago
  29. 50909c0 by David Greene · 16 years ago
  30. f37756d by David Greene · 16 years ago
  31. 6912be4 Added a new Spiller implementation which wraps LiveIntervals::addIntervalsForSpills. by Lang Hames · 16 years ago
  32. 05fb963 The Indexes Patch. by Lang Hames · 16 years ago
  33. 974e12b Remove includes of Support/Compiler.h that are no longer needed after the by Nick Lewycky · 16 years ago
  34. 02d5f77 Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces. by Nick Lewycky · 16 years ago
  35. 920301e Renamed MachineInstrIndex to LiveIndex. by Lang Hames · 16 years ago
  36. e603710 Simplify a few more uses of reg_iterator. by Dan Gohman · 16 years ago
  37. 3fffe62 Replaces uses of unsigned for indexes in LiveInterval and VNInfo with by Lang Hames · 16 years ago
  38. 1a25d73 Kill off more cerr/cout uses and prune includes a bit. by Benjamin Kramer · 16 years ago
  39. cddba73 Convert DOUT to DEBUG(errs()...). by Bill Wendling · 16 years ago
  40. 0402315 Use setPreservesAll and setPreservesCFG in CodeGen passes. by Dan Gohman · 16 years ago
  41. 0dd5e1e More migration to raw_ostream, the water has dried up around the iostream hole. by Daniel Dunbar · 16 years ago
  42. fbcc663 llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable. by Torok Edwin · 16 years ago
  43. 43edca2 Removed some junk code that snuck in to an earlier commit. by Lang Hames · 16 years ago
  44. ccb29cd Convert more assert(0)+abort() -> LLVM_UNREACHABLE, by Torok Edwin · 16 years ago
  45. d379e89 Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details. by Evan Cheng · 16 years ago
  46. 0dc101b Add a bit IsUndef to MachineOperand. This indicates the def / use register operand is defined by an implicit_def. That means it can def / use any register and passes (e.g. register scavenger) can feel free to ignore them. by Evan Cheng · 16 years ago
  47. 0e79603 - Update register allocation hint after coalescing. This is done by the target since the hint is target dependent. This is important for ARM register pair hints. by Evan Cheng · 16 years ago
  48. 16cab19 VNInfo cleanup. by Lang Hames · 16 years ago
  49. 1283c6a Part 1. by Evan Cheng · 16 years ago
  50. 085caf1 Move register allocation preference (or hint) from LiveInterval to MachineRegisterInfo. This allows more passes to set them. by Evan Cheng · 16 years ago
  51. fa0ac19 RALinScan::attemptTrivialCoalescing() was returning a virtual register instead of the physical register it is allocated to. This resulted in virtual register(s) being added the live-in sets. by Evan Cheng · 16 years ago
  52. 9ff058b A value defined by an implicit_def can be liven to a use BB. This is unfortunate. But register allocator still has to add it to the live-in set of the use BB. by Evan Cheng · 16 years ago
  53. aba72ed Remove a #include of <iostream>. by Dan Gohman · 16 years ago
  54. bb01ed9 Removed more testing code that snuck in earlier. by Lang Hames · 16 years ago
  55. 1dcd70c Fixed warning, removed some temporary validation code that snuck in during my last commit. by Lang Hames · 16 years ago
  56. fc968ef Update to in-place spilling framework. Includes live interval scaling and trivial rewriter. by Lang Hames · 16 years ago
  57. cf47d01 New Spiller interface and trivial implementation. by Lang Hames · 16 years ago
  58. df1aeee Teach TransferDeadness to delete truly dead instructions if they do not produce side effects. by Evan Cheng · 16 years ago
  59. ab68cf2 Renamed Spiller classes (plus uses and related files) to VirtRegRewriter. by Lang Hames · 17 years ago
  60. 210fc62 In some rare cases, the register allocator can spill registers but end up not utilizing registers at all. The fundamental problem is linearscan's backtracking can end up freeing more than one allocated registers. However, reloads and restores might be folded into uses / defs and freed registers might not be used at all. by Evan Cheng · 17 years ago
  61. f8949a6 Code clean up. Bye bye PhysRegTracker. by Evan Cheng · 17 years ago
  62. 9cce299 spillPhysRegAroundRegDefsUses() may have invalidated iterators stored in fixed_ IntervalPtrs. Reset them. by Evan Cheng · 17 years ago
  63. cfb4cae Determine allocation 'preference' with right register class. I haven't seen this changing codegen so no test case. by Evan Cheng · 17 years ago
  64. 1a99a5f It has finally happened. Spiller is now using live interval info. by Evan Cheng · 17 years ago
  65. 5dd2e29 - Remove an arbitrary spill weight tweak that should not have been there. by Evan Cheng · 17 years ago
  66. d67efaa Added a linearscan register allocation optimization. When the register allocator spill an interval with multiple uses in the same basic block, it creates a different virtual register for each of the reloads. e.g. by Evan Cheng · 17 years ago
  67. 7fe1b0f Fix a bug in spill weight computation. If the alias is a super-register, and the super-register is in the register class we are trying to allocate. Then add the weight to all sub-registers of the super-register even if they are not aliases. by Evan Cheng · 17 years ago
  68. f858466 Fix PR3391 and PR3864. Reg allocator infinite looping. by Evan Cheng · 17 years ago
  69. d37ddf5 Convert VirtRegMap to a MachineFunctionPass. by Owen Anderson · 17 years ago
  70. aabe06d Reorganization: Move the Spiller out of VirtRegMap.cpp into its own files. No (intended) functionality change. by Owen Anderson · 17 years ago
  71. c544cb0 Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well. by Evan Cheng · 17 years ago
  72. 8f79775 Make linear scan's trivial coalescer slightly more aggressive. by Evan Cheng · 17 years ago
  73. 906152a Tidy up #includes, deleting a bunch of unnecessary #includes. by Dan Gohman · 17 years ago
  74. ce3ccc1 - More pre-split fixes: spill slot live interval computation bug; restore point bug. by Evan Cheng · 17 years ago
  75. 938e201 - Rewrite code that update register live interval that's split. by Evan Cheng · 17 years ago
  76. d0d0317 Committing a good chunk of the pre-register allocation live interval splitting pass. It's handling simple cases and appear to do good things. Next: avoid splitting an interval multiple times; renumber registers when possible; record stack slot live intervals for coloring; rematerialize defs when possible. by Evan Cheng · 17 years ago
  77. 9c4b7d5 Fix command-line option printing to print two spaces where needed, by Dan Gohman · 17 years ago
  78. 1d338fc Add an option to enable StrongPHIElimination, for ease of testing. by Owen Anderson · 17 years ago
  79. 9156bd2 Re-apply 56835 along with header file changes. by Evan Cheng · 17 years ago
  80. 2b9adce Revert commit 56835 since it breaks the build. by Duncan Sands · 17 years ago
  81. 9469049 If a re-materializable instruction has a register operand, the spiller will change the register operand's spill weight to HUGE_VAL to avoid it being spilled. However, if the operand is already in the queue ready to be spilled, avoid re-materializing it. by Evan Cheng · 17 years ago
  82. c36660d Next round of earlyclobber handling. Approach the by Dale Johannesen · 17 years ago
  83. 9af7b3d Teach coalescer about earlyclobber bits. Check bits for preferred register. by Dale Johannesen · 17 years ago
  84. c042000 Fix PR2808. When regalloc runs out of register, it spill a physical register around the live interval being allocated. Do not continue to try to spill another register, just grab the physical register and move on. by Evan Cheng · 17 years ago
  85. 436aae6 Make earlyclobber stuff work when virtual regs by Dale Johannesen · 17 years ago
  86. e519bd4 Remove AsmThatEarlyClobber etc. from LiveIntervalAnalysis by Dale Johannesen · 17 years ago
  87. 3d9416c Somehow RegAllocLinearScan is keeping two pointers to MachineRegisterInfo. by Evan Cheng · 17 years ago
  88. f8610eb Add a bit to mark operands of asm's that conflict by Dale Johannesen · 17 years ago
  89. 53b728c Fix PR2757. Ignore liveinterval register allocation preference if the preference register is not in the right register class. This can happen due to sub-register coalescing. by Evan Cheng · 17 years ago
  90. a79db30 Tidy up several unbeseeming casts from pointer to intptr_t. by Dan Gohman · 17 years ago
  91. d669b9b Convert several std::vectors over to SmallVector, and use reserve() as appropriate for cases where std::vector is still used. by Owen Anderson · 17 years ago
  92. 99e911f Get rid of a use of std::map. by Owen Anderson · 17 years ago
  93. 51f689a Make the allocation of LiveIntervals explicit, rather than holding them in the r2iMap_ by value. This will prevent references to them from being invalidated by Owen Anderson · 17 years ago
  94. 7c800ad Fix a compile-time regression introduced by my heuristic-changing patch. I forgot by Owen Anderson · 17 years ago
  95. 029182f Change the heuristics used in the coalescer, register allocator, and within by Owen Anderson · 17 years ago
  96. 9cc3f68 A brief survey of priority_queue usage in the tree turned this up by Dan Gohman · 17 years ago
  97. efc67e7 Enhanced heuristic to determine the *best* register to spill. Instead of picking the register with the lowest spill weight. Consider (up to) 2 additional registers with spill weights that are close to the lowest spill weight. The one with fewest defs and uses that conflicts with the current interval (weighted by loop depth) is the spill candidate. by Evan Cheng · 17 years ago
  98. 6d7a144 Refine stack slot interval weight computation. by Evan Cheng · 17 years ago
  99. 12a0222 Add a stack slot coloring pass. Not yet enabled. by Evan Cheng · 17 years ago
  100. 305d268 Do not add empty live intervals to handled_. They should never be undone for backtracking. by Evan Cheng · 18 years ago