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gerrit-public.fairphone.software / toolchain / llvm-project / 781249833bfbcf30bfaa83022481ae54c39c82c0 / llvm / lib / Target / AMDGPU / R600MachineScheduler.cpp
  1. 9cfc75c CodeGen: Use MachineInstr& in TargetInstrInfo, NFC by Duncan P. N. Exon Smith · 9 years ago
  2. 43e92fe AMDGPU: Cleanup subtarget handling. by Matt Arsenault · 9 years ago
  3. 180e0d5 AMDGPU: Fix gcc warnings by Matt Arsenault · 9 years ago
  4. 45bb48e R600 -> AMDGPU rename by Tom Stellard · 10 years ago[Renamed from llvm/lib/Target/R600/R600MachineScheduler.cpp]
  5. 0795a2e Remove a few more calls to TargetMachine::getSubtarget from the R600 port. by Eric Christopher · 11 years ago
  6. 30d69c2 [PM] Remove the old 'PassManager.h' header file at the top level of by Chandler Carruth · 11 years ago
  7. 7792e32 Reuse a bunch of cached subtargets and remove getSubtarget calls by Eric Christopher · 11 years ago
  8. cce5701 Fix float division-by-zero in R600 scheduler. by Alexey Samsonov · 11 years ago
  9. efb3d53 R600: Remove unused include by Matt Arsenault · 11 years ago
  10. 2e59a45 R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtarget by Tom Stellard · 11 years ago
  11. 062a2ba [C++] Use 'nullptr'. Target edition. by Craig Topper · 12 years ago
  12. 84e68b2 [Modules] Fix potential ODR violations by sinking the DEBUG_TYPE by Chandler Carruth · 12 years ago
  13. d7f890e Factor MI-Sched in preparation for post-ra scheduling support. by Andrew Trick · 12 years ago
  14. 8f9fc20 R600: Fix scheduling of instructions that use the LDS output queue by Tom Stellard · 12 years ago
  15. 7f6fa4c R600: Don't use trans slot for instructions that read LDS source registers by Tom Stellard · 12 years ago
  16. 7e2c832 R600: Non vector only instruction can be scheduled on trans unit by Vincent Lejeune · 12 years ago
  17. ca69a53 Revert "R600: Non vector only instruction can be scheduled on trans unit" by Tom Stellard · 12 years ago
  18. df18804 R600: Non vector only instruction can be scheduled on trans unit by Vincent Lejeune · 12 years ago
  19. 77a8352 R600: Support schedule and packetization of trans-only inst by Vincent Lejeune · 12 years ago
  20. c026e8b R600: Add local memory support via LDS by Tom Stellard · 12 years ago
  21. ce54033 R600: Add support for GROUP_BARRIER instruction by Tom Stellard · 12 years ago
  22. d1a9d18 R600: Use a refined heuristic to choose when switching clause by Vincent Lejeune · 12 years ago
  23. a6c6e1b R600: Rework subtarget info and remove AMDILDevice classes by Tom Stellard · 12 years ago
  24. 54476a1 R600: Remove leftover code in R600MachineScheduler.cpp by Vincent Lejeune · 12 years ago
  25. 4b5b849 R600: Schedule copy from phys register at beginning of block by Vincent Lejeune · 12 years ago
  26. aad5376 R600: Make sure to schedule AR register uses and defs in the same clause by Tom Stellard · 12 years ago
  27. d78bb46 Move passes from namespace llvm into anonymous namespaces. Sort includes while there. by Benjamin Kramer · 12 years ago
  28. 3d5118c R600: Use bottom up scheduling algorithm by Vincent Lejeune · 12 years ago
  29. 4c81d4d R600: Use depth first scheduling algorithm by Vincent Lejeune · 12 years ago
  30. e958c8e R600: Replace big texture opcode switch in scheduler by usesTC/usesVC by Vincent Lejeune · 12 years ago
  31. 519f21e R600: Relax some vector constraints on Dot4. by Vincent Lejeune · 12 years ago
  32. f9f4e1e R600: Factorize Fetch size limit inside AMDGPUSubTarget by Vincent Lejeune · 12 years ago
  33. 80031d9f R600: Factorize maximum alu per clause in a single location by Vincent Lejeune · 13 years ago
  34. 0a22bc4 R600: Factorize code handling Const Read Port limitation by Vincent Lejeune · 13 years ago
  35. 756cf88 R600MachineScheduler.cpp: Fix use cases of dbgs(). Don't include <iostream> here. by NAKAMURA Takumi · 13 years ago
  36. 68b6b6d R600: initial scheduler code by Vincent Lejeune · 13 years ago