1. 15c1b82 fix a pasto by Chris Lattner · 19 years ago
  2. 4aff52b Fix a bug in my previous patch, grabbing the shift amount width from the by Chris Lattner · 19 years ago
  3. 9a861a8 Fold (x << c1)>> c2 into a single shift if the bits shifted out aren't used. by Chris Lattner · 19 years ago
  4. fb80151 Removed tabs everywhere except autogenerated & external files. Add make by Anton Korobeynikov · 19 years ago
  5. 784a68a Fix weirdness handling single element vectors. by Chris Lattner · 19 years ago
  6. 35f0417 remove dead target hooks. by Chris Lattner · 19 years ago
  7. 39f6533 remove some dead target hooks, subsumed by isLegalAddressingMode by Chris Lattner · 19 years ago
  8. f2d71d4 switch TL::getValueType to use MVT::getValueType. by Chris Lattner · 19 years ago
  9. ac3f815 add one addressing mode description hook to rule them all. by Chris Lattner · 19 years ago
  10. c2cba18 Remove isLegalAddressImmediate. by Evan Cheng · 19 years ago
  11. 3d7efa2 implement initial support for the silly X constraint. Testcase here: CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll by Chris Lattner · 19 years ago
  12. 843e445 Implement CodeGen/X86/2007-03-24-InlineAsmMultiRegConstraint.ll by Chris Lattner · 19 years ago
  13. d685514 switch TargetLowering::getConstraintType to take the entire constraint, by Chris Lattner · 19 years ago
  14. 0c6bb5e repair x86 performance, dejagnu problems from previous change by Dale Johannesen · 19 years ago
  15. bacf4ac do not share old induction variables when this would result in invalid by Dale Johannesen · 19 years ago
  16. a2a2fd1 Added isLegalAddressExpression hook to test if the given expression can be by Evan Cheng · 19 years ago
  17. b7004fd More flexible TargetLowering LSR hooks for testing whether an immediate is a legal target address immediate or scale. by Evan Cheng · 19 years ago
  18. 168c585 initialize a instance variable by Chris Lattner · 19 years ago
  19. d7ef3f8 Fix CodeGen/Generic/2007-02-23-DAGCombine-Miscompile.ll and PR1219 by Chris Lattner · 19 years ago
  20. 3e3a65b Need to init. by Jim Laskey · 19 years ago
  21. a9f917a Implement i/n/s constraints correctly. This fixes by Chris Lattner · 19 years ago
  22. d84d35b For PR1195: by Reid Spencer · 19 years ago
  23. d08d31f Fix PR1198, by adding initial i128 support. Patch by Dan Gohman. by Chris Lattner · 19 years ago
  24. 92658d5 Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. by Evan Cheng · 19 years ago
  25. 296a83c Fit in 80 columns by Chris Lattner · 19 years ago
  26. 53026f1 Allow the target to override the ISD::CondCode that's to be used to test the by Evan Cheng · 19 years ago
  27. ddf1421b8 Move a function out of line. by Reid Spencer · 19 years ago
  28. 61a4be8 Minor fix. by Evan Cheng · 19 years ago
  29. 31cbddf Store default libgcc routine names and allow them to be redefined by target. by Evan Cheng · 19 years ago
  30. 3b7c257 Cleaned setjmp/longjmp lowering interfaces. Now we're producing right by Anton Korobeynikov · 19 years ago
  31. 4eee724 Preliminary soft float support. by Evan Cheng · 19 years ago
  32. 5d5916b Fix the dag combiner bug corresponding to PR1014. by Chris Lattner · 19 years ago
  33. d550248 Add a mechanism to specify whether a target supports a particular indexed load / store. by Evan Cheng · 19 years ago
  34. de46e48 For PR786: by Reid Spencer · 19 years ago
  35. 8c6949e Change the prototype for TargetLowering::isOperandValidForConstraint by Chris Lattner · 19 years ago
  36. ab51cf2 Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode. by Evan Cheng · 19 years ago
  37. d35734b Naming consistency. by Evan Cheng · 19 years ago
  38. e71fe34d Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes. by Evan Cheng · 19 years ago
  39. a389a61 initialize ivar by Chris Lattner · 19 years ago
  40. 5d9fd97 Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an by Evan Cheng · 19 years ago
  41. 0dce331 Change the default to 0, which means 'default'. by Chris Lattner · 19 years ago
  42. 373be1d forgot this by Duraid Madina · 19 years ago
  43. 85ea83e Add some advice by Chris Lattner · 19 years ago[Renamed from llvm/lib/Target/TargetLowering.cpp]
  44. af5ae57 Fix a typo that causes 2006-07-07-ComputeMaskedBits.ll to fail. by Evan Cheng · 19 years ago
  45. c5bb8ab Port some bugfixes in shift handling from SimplifyDemandedBits over to by Chris Lattner · 19 years ago
  46. 8cac9cd TargetLowering::ComputeMaskedBits was not clearing reciprocal bits on shifts. by Jim Laskey · 19 years ago
  47. 0e57b2c Start on my todo list by Andrew Lenharth · 19 years ago
  48. 19aaaca Another typo. Pointed out by Nate Begeman. by Evan Cheng · 19 years ago
  49. 6dcec44 Fix an obvious bug in getPackedTypeBreakdown. Return 1 if type is legal. by Evan Cheng · 19 years ago
  50. 20eb2ce this should be 128 I think by Andrew Lenharth · 19 years ago
  51. 1dc9ec5 Move this code to a common place by Andrew Lenharth · 19 years ago
  52. 8c2c1e9 Refactor a bunch of includes so that TargetMachine.h doesn't have to include by Owen Anderson · 19 years ago
  53. 10c6537 When tracking demanded bits, if any bits from the sext of an SRA are demanded, by Chris Lattner · 20 years ago
  54. cd4a643 Use ComputeMaskedBits to determine # sign bits as a fallback. This allows us by Chris Lattner · 20 years ago
  55. 4f3de3e Add some more sign propagation cases by Chris Lattner · 20 years ago
  56. f860757 Add some more simple sign bit propagation cases. by Chris Lattner · 20 years ago
  57. 7206d74 Add some really really simple code for computing sign-bit propagation. by Chris Lattner · 20 years ago
  58. 86a1467 Fold (trunc (srl x, c)) -> (srl (trunc x), c) by Chris Lattner · 20 years ago
  59. 0f64932 Implement ComputeMaskedBits/SimplifyDemandedBits for ISD::TRUNCATE by Chris Lattner · 20 years ago
  60. 20a631f Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference. by Owen Anderson · 20 years ago
  61. 6c1321c relax assertion by Chris Lattner · 20 years ago
  62. e602552 Allow targets to compute masked bits for intrinsics. by Chris Lattner · 20 years ago
  63. 051f786 Was returning the wrong type. by Chris Lattner · 20 years ago
  64. f144dac Modify the TargetLowering::getPackedTypeBreakdown method to also return the by Chris Lattner · 20 years ago
  65. 549fb16 Implement TargetLowering::getPackedTypeBreakdown by Chris Lattner · 20 years ago
  66. 4b5b4e3 Typo by Evan Cheng · 20 years ago
  67. ad74844 set TransformToType correctly for vector types. by Chris Lattner · 20 years ago
  68. af598d2 Add LSR hooks. by Evan Cheng · 20 years ago
  69. 3d761b6 I can't convince myself that this is safe, remove the recursive call. by Chris Lattner · 20 years ago
  70. c726a5c Do not fold (add (shl x, c1), (shl c2, c1)) -> (shl (add x, c2), c1), by Chris Lattner · 20 years ago
  71. a7fb285 Number of NodeTypes now exceeds 128. by Evan Cheng · 20 years ago
  72. 4a2eeea Add interfaces for targets to provide target-specific dag combiner optimizations. by Chris Lattner · 20 years ago
  73. ab81640 Implement bit propagation through sub nodes, this (re)implements by Chris Lattner · 20 years ago
  74. a60751d Check RHS simplification before LHS simplification to avoid infinitely looping by Chris Lattner · 20 years ago
  75. 27220f8 Just like we use the RHS of an AND to simplify the LHS, use the LHS to by Chris Lattner · 20 years ago
  76. 118ddba Add a bunch of missed cases. Perhaps the most significant of which is that by Chris Lattner · 20 years ago
  77. 2a9e1e3 Recognize memory operand codes by Chris Lattner · 20 years ago
  78. 2e124af Don't return registers from register classes that aren't legal. by Chris Lattner · 20 years ago
  79. 7ad77df split register class handling from explicit physreg handling. by Chris Lattner · 20 years ago
  80. 7bb4696 Updates to match change of getRegForInlineAsmConstraint prototype by Chris Lattner · 20 years ago
  81. 983ca89 Add a fold for add that exchanges it with a constant shift if possible, so by Nate Begeman · 20 years ago
  82. 0d62ebd Fix bug noticed by VC++. by Jeff Cohen · 20 years ago
  83. 8a77efe Rework the SelectionDAG-based implementations of SimplifyDemandedBits by Nate Begeman · 20 years ago
  84. 4b40a42 Rename maxStoresPerMemSet to maxStoresPerMemset, etc. by Evan Cheng · 20 years ago
  85. ee1dadb implementation of some methods for inlineasm by Chris Lattner · 20 years ago
  86. 20a8942 Implement some feedback from sabre by Nate Begeman · 20 years ago
  87. dc7bba9 Add a framework for eliminating instructions that produces undemanded bits. by Nate Begeman · 20 years ago
  88. e0c60d6 Implement MaskedValueIsZero for ANY_EXTEND nodes by Chris Lattner · 20 years ago
  89. 7ed3101 Beef up the interface to inline asm constraint parsing, making it more general, useful, and easier to use. by Chris Lattner · 20 years ago
  90. f0b24d2 Move MaskedValueIsZero from the DAGCombiner to the TargetLowering interface,making isMaskedValueZeroForTargetNode simpler, and useable from other partsof the compiler. by Chris Lattner · 20 years ago
  91. c6fa028 adjust prototype by Chris Lattner · 20 years ago
  92. 8a4a3de clean up interface to ValueTypeActions by Chris Lattner · 20 years ago
  93. 32fef53 Implement a method for inline asm support by Chris Lattner · 20 years ago
  94. d07c864 initialize an instance var, apparently I forgot to commit this long ago by Chris Lattner · 20 years ago
  95. 030e002 Set SchedulingForLatency to be the default scheduling preference for all. by Evan Cheng · 20 years ago
  96. 1872908 Lefted out TargetLowering:: by Evan Cheng · 20 years ago
  97. 9cdc16c * Fix a GlobalAddress lowering bug. by Evan Cheng · 20 years ago
  98. 6af0263 Added a hook to print out names of target specific DAG nodes. by Evan Cheng · 20 years ago
  99. 89b049a Add the majority of the vector machien value types we expect to support, by Nate Begeman · 20 years ago
  100. 07890bb Rather than attempting to legalize 1 x float, make sure the SD ISel never by Nate Begeman · 20 years ago