Log - 81fe1fbf4abd00b24e078a80cb15a2d2c1343f11 - toolchain/llvm-project

f57d7d8 [AArch64] - Return address signing dwarf support by Luke Cheeseman · 7 years ago
b51480f [mir] Fix uninitialized variable in r349035 noticed by clang-atom-d525-fedora-rel and 3 other bots by Daniel Sanders · 7 years ago
9f3cf55 [mir] Serialize DILocation inline when not possible to use a metadata reference by Daniel Sanders · 7 years ago
6db3a6a Revert r347490 as it breaks address sanitizer builds by Luke Cheeseman · 7 years ago
d6dbd64 Revert r343341 by Luke Cheeseman · 7 years ago
a834038 MachineOperand/MIParser: Do not print debug-use flag, infer it by Matthias Braun · 7 years ago
7159daa MIRParser: Check that instructions only reference DILocation metadata by Matthias Braun · 7 years ago
10981cc Revert r343317 by Luke Cheeseman · 7 years ago
21f2955b Reapply changes reverted by r343235 by Luke Cheeseman · 7 years ago
8e5676b Revert r343192 as an ubsan build is currently failing by Luke Cheeseman · 7 years ago
f6844b3 Reapply changes reverted in r343114, lldb patch to follow shortly by Luke Cheeseman · 7 years ago
77aaa22 Revert r343112 as CallFrameString API change has broken lldb builds by Luke Cheeseman · 7 years ago
03ad881 [AArch64] - Return address signing dwarf support by Luke Cheeseman · 7 years ago
00b88bb Revert r343089 "[AArch64] - Return address signing dwarf support" by Hans Wennborg · 7 years ago
f755e68 [AArch64] - Return address signing dwarf support by Luke Cheeseman · 7 years ago
c72a725 add IR flags to MI by Michael Berg · 7 years ago
cc3f630 Consistently use MemoryLocation::UnknownSize to indicate unknown access size by Krzysztof Parzyszek · 7 years ago
75ca6be [x86/MIR] Implement support for pre- and post-instruction symbols, as by Chandler Carruth · 7 years ago
c73c030 [MI] Change the array of `MachineMemOperand` pointers to be by Chandler Carruth · 7 years ago
57dd5b3 CodeGen: Cleanup regmask construction; NFC by Matthias Braun · 7 years ago
cb0bab8 [CodeGen] Fix inconsistent declaration parameter name by Fangrui Song · 7 years ago
a245c76 [MIRParser] Update a diagnostic message to use the correct register sigil. NFC by Matt Davis · 7 years ago
d496cc8 [MIRParser] Add parser support for 'true' and 'false' i1s. by Amara Emerson · 7 years ago
5e51fac [MIRParser][GlobalISel] Parsing vector pointer types (<M x pA>) by Roman Tereshin · 7 years ago
c86da6b [MIRPraser] Improve error checking for typed immediate operands by Heejin Ahn · 7 years ago
c2ad096 [MIRParser] Allow register class names in the form of integer/scalar by Heejin Ahn · 7 years ago
7d1b25d MachineInst support mapping SDNode fast math flags for support in Back End code generation by Michael Berg · 7 years ago
399b46c [MIR] Adding support for Named Virtual Registers in MIR. by Puyan Lotfi · 8 years ago
3abf0573 [MIR] Allow frame-setup and frame-destroy on the same instruction by Francis Visoiu Mistrih · 8 years ago
e4718e8 [MIR] Add support for addrspace in MIR by Francis Visoiu Mistrih · 8 years ago
dbf2c48 [MIR] Add support for the frame-destroy MachineInstr flag by Francis Visoiu Mistrih · 8 years ago
f1caa28 MachineFunction: Return reference from getFunction(); NFC by Matthias Braun · 8 years ago
5de20e0 [MIR] Add support for missing CFI directives by Francis Visoiu Mistrih · 8 years ago
c468b64 Remove redundant includes from lib/CodeGen. by Michael Zolotukhin · 8 years ago
60c4310 [MachineOperand][MIR] Add isRenamable to MachineOperand. by Geoff Berry · 8 years ago
25528d6 [CodeGen] Unify MBB reference format in both MIR and debug output by Francis Visoiu Mistrih · 8 years ago
17d277b [mir] Print/Parse both MOLoad and MOStore when they occur together. by Daniel Sanders · 8 years ago
b3bde2e Fix a bunch more layering of CodeGen headers that are in Target by David Blaikie · 8 years ago
3f833ed Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering by David Blaikie · 8 years ago
66d2c26 [AsmPrinterDwarf] Add support for .cfi_restore directive by Francis Visoiu Mistrih · 8 years ago
b0d17d9 [MIParser] Ensure getHexUint doesn't produce APInts with a bitwidth of 0 by Jessica Paquette · 8 years ago
6d35334 Parse and print DIExpressions inline to ease IR and MIR testing by Reid Kleckner · 8 years ago
6748abe [MIR] Add support for printing and parsing target MMO flags by Geoff Berry · 8 years ago
bb80d3e Enhance synchscope representation by Konstantin Zhuravlyov · 8 years ago
6a391bb fix trivial typos, NFC by Hiroshi Inoue · 8 years ago
fb69e66 [CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). by Eugene Zelenko · 8 years ago
8940114 MIParser/MIRPrinter: Compute block successors if not explicitely specified by Matthias Braun · 8 years ago
4abfb3d Revert "[APInt] Fix a few places that use APInt::getRawData to operate within the normal API." by Renato Golin · 8 years ago
474e5de [APInt] Fix a few places that use APInt::getRawData to operate within the normal API. by Craig Topper · 8 years ago
0ef61ec [MIR] Support Customed Register Mask and CSRs by Oren Ben Simhon · 9 years ago
b73e309 MIR: parse & print the atomic parts of a MachineMemOperand. by Tim Northover · 9 years ago
bf48055 [MIRParser] Allow generic register specification on operand. by Ahmed Bougacha · 9 years ago
de5fea2 MIRParser: Allow regclass specification on operand by Matthias Braun · 9 years ago
3749f33 [GlobalISel] More fix for the size vs. type typo. NFC. by Quentin Colombet · 9 years ago
e08cc59 [MIRParser] Fix a typo in comment and error message. by Quentin Colombet · 9 years ago
9751e61 [MIRParser] Non-generic virtual register may have a type. by Quentin Colombet · 9 years ago
36ef5dc [MIRParser] Add parsing hex literals of arbitrary size as unsigned integers by Krzysztof Parzyszek · 9 years ago
91b5cf8 Extract LaneBitmask into a separate type by Krzysztof Parzyszek · 9 years ago
f23ef43 Move FrameInstructions from MachineModuleInfo to MachineFunction by Matthias Braun · 9 years ago
b51774a [MIRPrinter] Print raw branch probabilities as expected by MIRParser by Geoff Berry · 9 years ago
9c884e4 MIRParser: Add support for parsing vreg reg alloc hints by Tom Stellard · 9 years ago
06ac79c Fix Clang-tidy readability-redundant-string-cstr warnings by Malcolm Parsons · 9 years ago
d62669d [MIRParser] Parse lane masks for register live-ins by Krzysztof Parzyszek · 9 years ago
60cf6fc MIRParser: allow types on registers with a RegBank. by Tim Northover · 9 years ago
3d85ebe MIRParser: generic register operands with types by Matthias Braun · 9 years ago
74ad41c MIRParser: Rewrite register info initialization; mostly NFC by Matthias Braun · 9 years ago
0f8b5d6 [MIRParser] Delete dead code. NFCI. by Davide Italiano · 9 years ago
a53d49e Don't create a SymbolTable in Function when the LLVMContext discards value names (NFC) by Mehdi Amini · 9 years ago
32a078a GlobalISel: remove "unsized" LLT by Tim Northover · 9 years ago
5ae8350 GlobalISel: cache pointer sizes in LLT by Tim Northover · 9 years ago
d28d3cc GlobalISel: disambiguate types when printing MIR by Tim Northover · 9 years ago
adbf09e [CodeGen] Split out the notions of MI invariance and MI dereferenceability. by Justin Lebar · 9 years ago
0f140c7 GlobalISel: move type information to MachineRegisterInfo. by Tim Northover · 9 years ago
a5b1eef [MC] Move .cv_loc management logic out of MCContext by Reid Kleckner · 9 years ago
6cd4b23 GlobalISel: legalize integer comparisons on AArch64. by Tim Northover · 9 years ago
de3aea041 GlobalISel: support irtranslation of icmp instructions. by Tim Northover · 9 years ago
b03fd12 Replace "fallthrough" comments with LLVM_FALLTHROUGH by Justin Bogner · 9 years ago
6b3bd61 CodeGen: add new "intrinsic" MachineOperand kind. by Tim Northover · 9 years ago
941a705 MachineFunction: Return reference for getFrameInfo(); NFC by Matthias Braun · 9 years ago
d760de0 [MIRParser] Accept unsized generic instructions. by Ahmed Bougacha · 9 years ago
333e468 MIRParser: Use dot instead of colon to mark subregisters by Matthias Braun · 9 years ago
26e40bd GlobalISel: omit braces on MachineInstr types when there's only one. by Tim Northover · 9 years ago
98a56eb GlobalISel: allow multiple types on MachineInstrs. by Tim Northover · 9 years ago
bd50546 GlobalISel: implement alloca instruction by Tim Northover · 9 years ago
62ae568 GlobalISel: implement low-level type with just size & vector lanes. by Tim Northover · 9 years ago
5a59b24 [GlobalISel] Mark newly-created gvregs as having a bank. by Ahmed Bougacha · 9 years ago
5d00b32 MIParser: reject subregister indexes on physregs by Matthias Braun · 9 years ago
0af80cd [CodeGen] Take a MachineMemOperand::Flags in MachineFunction::getMachineMemOperand. by Justin Lebar · 9 years ago
e35861d MIRParser: Move SlotMapping and SourceMgr refs to PFS; NFC by Matthias Braun · 9 years ago
8394786 MIRParser: Move MachineFunction reference into PFS; NFC by Matthias Braun · 9 years ago
2c64696 [MIR] Check that generic virtual registers get a size. by Quentin Colombet · 9 years ago
3ef7df9 MIR: Fix parsing of stack object references in MachineMemOperands by Matthias Braun · 9 years ago
c25c9cc MIR: Support MachineMemOperands without associated value by Matthias Braun · 9 years ago
b74eb41 MIRParser: Add %subreg.xxx syntax for subregister index operands by Matthias Braun · 10 years ago
287c6bb [MIR] Teach the parser how to parse complex types of generic machine instructions. by Quentin Colombet · 10 years ago
8519967 [MIR] Teach the mir parser about types on generic machine instructions. by Quentin Colombet · 10 years ago
2a831fb [MIR] Teach the parser how to handle the size of generic virtual registers. by Quentin Colombet · 10 years ago
e5e035a3 Replace uint16_t with the MCPhysReg typedef in many places. A lot of physical register arrays already use this typedef. by Craig Topper · 10 years ago
d97c100 Replace all weight-based interfaces in MBB with probability-based interfaces, and update all uses of old interfaces. by Cong Hou · 10 years ago
1dbaf67 Revert r254348: "Replace all weight-based interfaces in MBB with probability-based interfaces, and update all uses of old interfaces." by Hans Wennborg · 10 years ago