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gerrit-public.fairphone.software / toolchain / llvm-project / 81fe1fbf4abd00b24e078a80cb15a2d2c1343f11 / llvm / lib / CodeGen / TargetSchedule.cpp
  1. 59313be [CodeGen] assume max/default throughput for unspecified instructions by Sanjay Patel · 7 years ago
  2. be8616f [MCSchedule] Add the ability to compute the latency and throughput information for MCInst. by Andrea Di Biagio · 7 years ago
  3. b9acf13 [MC] Moved all the remaining logic that computed instruction latency and reciprocal throughput from TargetSchedModel to MCSchedModel. by Andrea Di Biagio · 7 years ago
  4. 0d7df36 [TargetSchedule] shrink interface for init(); NFCI by Sanjay Patel · 7 years ago
  5. 7faea7c [MC] Move the reciprocal throughput computation from TargetSchedModel to MCSchedModel. by Andrea Di Biagio · 8 years ago
  6. 30c1ba4 [MC] Move the instruction latency computation from TargetSchedModel to MCSchedModel. by Andrea Di Biagio · 8 years ago
  7. 6d18d6e [TargetSchedule] Minor refactor in computeInstrLatency. NFC by Andrea Di Biagio · 8 years ago
  8. b3bde2e Fix a bunch more layering of CodeGen headers that are in Target by David Blaikie · 8 years ago
  9. 3f833ed Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering by David Blaikie · 8 years ago
  10. fdf9bf4 CodeGen: Minor cleanups to use MachineInstr::getMF. NFC by Justin Bogner · 8 years ago
  11. d1fefa3 This patch returns proper value to indicate the case when instruction throughput can't be calculated. by Andrew V. Tischenko · 8 years ago
  12. 3446ff4 Fix spelling mistake in getRThroughput static function names. NFCI. by Simon Pilgrim · 8 years ago
  13. 6bda14b Sort the remaining #include lines in include/... and lib/.... by Chandler Carruth · 8 years ago
  14. 75745d0 This patch closes PR#32216: Better testing of schedule model instruction latencies/throughputs. by Andrew V. Tischenko · 8 years ago
  15. 3d59437 Improve machine schedulers for in-order processors by Javed Absar · 9 years ago
  16. fa912a7 [CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). by Eugene Zelenko · 9 years ago
  17. 3a13315 TargetSchedule: Do not consider subregister definitions as reads. by Matthias Braun · 9 years ago
  18. 9cfc75c CodeGen: Use MachineInstr& in TargetInstrInfo, NFC by Duncan P. N. Exon Smith · 9 years ago
  19. 1181192 [TargetSchedule] Use 'isOutOfOrder' as possible to avoid magic number. NFC. by Junmo Park · 9 years ago
  20. 6307eb5 CodeGen: TII: Take MachineInstr& in predicate API, NFC by Duncan P. N. Exon Smith · 10 years ago
  21. 4a9a4e1 [MISched] Explanatory error message when machine model is not complete. NFC by MinSeong Kim · 10 years ago
  22. 244a677 Use llvm_unreachable() instead of report_fatal_error() if the machine model is incomplete by Matthias Braun · 10 years ago
  23. 7a247f7 Turn effective assert(0) into llvm_unreachable by Matthias Braun · 10 years ago
  24. 42e1e66 TargetSchedule: factor out common code; NFC by Matthias Braun · 10 years ago
  25. 307c2cb Remove unnecessary TargetMachine.h includes. by Eric Christopher · 11 years ago
  26. 1175945 Change MCSchedModel to be a struct of statically initialized data. by Pete Cooper · 11 years ago
  27. fc6de42 Have MachineFunction cache a pointer to the subtarget to make lookups by Eric Christopher · 11 years ago
  28. d913448 Remove the TargetMachine forwards for TargetSubtargetInfo based by Eric Christopher · 11 years ago
  29. 5e1207e MachineCombiner Pass for selecting faster instruction by Gerolf Hoflehner · 11 years ago
  30. e69170a Revert "Introduce a string_ostream string builder facilty" by Alp Toker · 11 years ago
  31. 6147173 Introduce a string_ostream string builder facilty by Alp Toker · 11 years ago
  32. d2f96b9 IfConverter: Use TargetSchedule for instruction latencies by Arnold Schwaighofer · 12 years ago
  33. b6854d8 Mark the x86 machine model as incomplete. PR17367. by Andrew Trick · 12 years ago
  34. 5d486186 MI-Sched: handle ReadAdvance latencies as used by Swift. by Andrew Trick · 12 years ago
  35. de2109e Machine Model: Add MicroOpBufferSize and resource BufferSize. by Andrew Trick · 12 years ago
  36. be2bccb MI-Sched cleanup. If an instruction has no valid sched class, do not attempt to check for a variant. by Andrew Trick · 12 years ago
  37. 6057017 Change the default latency for implicit defs. by Andrew Trick · 13 years ago
  38. ed0881b Use the new script to sort the includes of every file under lib. by Chandler Carruth · 13 years ago
  39. e96390e misched: TargetSchedule interface for machine resources. by Andrew Trick · 13 years ago
  40. 0b1d8d0 misched: Better handling of invalid latencies in the machine model by Andrew Trick · 13 years ago
  41. 5f35afb misched: Handle "transient" non-instructions. by Andrew Trick · 13 years ago
  42. c334bd4 misched: fall-back to a target hook for instr bundles. by Andrew Trick · 13 years ago
  43. dd79f0f misched: Use the TargetSchedModel interface wherever possible. by Andrew Trick · 13 years ago
  44. 780fae8 misched: Add computeInstrLatency to TargetSchedModel. by Andrew Trick · 13 years ago
  45. cfcf520 misched: Allow flags to disable hasInstrSchedModel/hasInstrItineraries for external users of TargetSchedule. by Andrew Trick · 13 years ago
  46. 8abcf4d Enable -schedmodel, but prefer itineraries until we have more benchmark data. by Andrew Trick · 13 years ago
  47. f2b70d9 TargetSchedule: cleanup computeOperandLatency logic & diagnostics. by Andrew Trick · 13 years ago
  48. 6e6d597 TargetSchedModel API. Implement latency lookup, disabled. by Andrew Trick · 13 years ago
  49. 8e7f202 Revert r164061-r164067. Most of the new subtarget emitter. by Andrew Trick · 13 years ago
  50. f403ee7 TargetSchedModel API. Implement latency lookup, disabled. by Andrew Trick · 13 years ago
  51. d2a19da TargetSchedModel interface. To be implemented... by Andrew Trick · 13 years ago