- 13d3371 [AMDGPU] Always pass TRI into findRegister[Use/Def]OperandIdx by Stanislav Mekhanoshin · 7 years ago
- 0da6350 AMDGPU: Remove remnants of old address space mapping by Matt Arsenault · 7 years ago
- 5ca4128 [PSV] Update API to be able to use TargetCustom without UB. by Marcello Maggioni · 7 years ago
- 5bfbae5 AMDGPU: Refactor Subtarget classes by Tom Stellard · 7 years ago
- c5a154d AMDGPU: Separate R600 and GCN TableGen files by Tom Stellard · 7 years ago
- 44b30b4 AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headers by Tom Stellard · 7 years ago
- b03c98d AMDGPU: Make getSubRegFromChannel a static member of AMDGPURegisterInfo by Tom Stellard · 7 years ago
- 5f8f34e4 Remove \brief commands from doxygen comments. by Adrian Prantl · 7 years ago
- c4796d4 [AMDGPU] Make sure all super regs of reserved regs are marked reserved. by Geoff Berry · 8 years ago
- f1caa28 MachineFunction: Return reference from getFunction(); NFC by Matthias Braun · 8 years ago
- b3bde2e Fix a bunch more layering of CodeGen headers that are in Target by David Blaikie · 8 years ago
- 920cc2f [AMDGPU] Fix pointer info for pseudo source for r600 by Yaxun Liu · 8 years ago
- 72518ea Add iterator range MachineRegisterInfo::liveins(), adopt users, NFC by Krzysztof Parzyszek · 8 years ago
- 6bda14b Sort the remaining #include lines in include/... and lib/.... by Chandler Carruth · 8 years ago
- fa929a2 Cyle -> Cycle; NFCI by Sanjay Patel · 9 years ago
- cc31871 Make TargetInstrInfo::isPredicable take a const reference, NFC by Krzysztof Parzyszek · 9 years ago
- 734bb7b [AMDGPU] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). by Eugene Zelenko · 9 years ago
- 1b9fc8e Finish renaming remaining analyzeBranch functions by Matt Arsenault · 9 years ago
- e8e0f5c Make analyzeBranch family of instruction names consistent by Matt Arsenault · 9 years ago
- a2b036e AArch64: Use TTI branch functions in branch relaxation by Matt Arsenault · 9 years ago
- 1872096 CodeGen: Give MachineBasicBlock::reverse_iterator a handle to the current MI by Duncan P. N. Exon Smith · 9 years ago
- 44f6d69 AMDGPU/R600: Remove macros by Matt Arsenault · 9 years ago
- f197b1f ADT: Remove all ilist_iterator => pointer casts, NFC by Duncan P. N. Exon Smith · 9 years ago
- 22ff865 [AMDGPU] Fix lifetime of SmallVector temporaries. by Benjamin Kramer · 9 years ago
- 941a705 MachineFunction: Return reference for getFrameInfo(); NFC by Matthias Braun · 9 years ago
- d7f4414 AMDGPU/R600: Delete dead code. by Matt Arsenault · 9 years ago
- 71c30a1 Rename AnalyzeBranch* to analyzeBranch*. by Jacques Pienaar · 9 years ago
- 52a4d9b AMDGPU: Move R600 only pieces into R600 classes by Matt Arsenault · 9 years ago
- 4d29511 AMDGPU: Remove implicit iterator conversions, NFC by Duncan P. N. Exon Smith · 9 years ago
- 9cfc75c CodeGen: Use MachineInstr& in TargetInstrInfo, NFC by Duncan P. N. Exon Smith · 9 years ago
- 43e92fe AMDGPU: Cleanup subtarget handling. by Matt Arsenault · 9 years ago
- bdc4956 Pass DebugLoc and SDLoc by const ref. by Benjamin Kramer · 9 years ago
- fac8d7e AMDGPU/R600: There are other uses for ALU_LITERAL besides Imm by Jan Vesely · 9 years ago
- bbc2231 AMDGPU/R600: Minor cleanup in InstrInfo by Jan Vesely · 9 years ago
- df3a20c AMDGPU: Add a shader calling convention by Nicolai Haehnle · 9 years ago
- 8226fc4 AMDGPU: Simplify boolean conditional return statements by Matt Arsenault · 10 years ago
- 6307eb5 CodeGen: TII: Take MachineInstr& in predicate API, NFC by Duncan P. N. Exon Smith · 10 years ago
- 1242ce9 AMDGPU: Remove some purely R600 functions from AMDGPUInstrInfo by Tom Stellard · 10 years ago
- 2ff7262 AMDGPU: Move subtarget specific code out of AMDGPUInstrInfo.cpp by Tom Stellard · 10 years ago
- c536bd9 Pass BranchProbability/BlockMass by value instead of const& as they are small. NFC. by Cong Hou · 10 years ago
- e61cbd1 Replace copy-pasted debug value skipping with MBB::getLastNonDebugInstr by Benjamin Kramer · 10 years ago
- 45bb48e R600 -> AMDGPU rename by Tom Stellard · 10 years ago[Renamed from llvm/lib/Target/R600/R600InstrInfo.cpp]
- c88bf54 [CodeGen] ArrayRef'ize cond/pred in various TII APIs. NFC. by Ahmed Bougacha · 10 years ago
- 6c5b511 Remove the need to cache the subtarget in the R600 TargetRegisterInfo classes. by Eric Christopher · 11 years ago
- 468e055 R600: Use c++11 style for loop by Jan Vesely · 11 years ago
- 143f02c Remove unused argument to CreateTargetScheduleState and change by Eric Christopher · 11 years ago
- e12a6ba Eliminate some deep std::vector copies. NFC. by Benjamin Kramer · 11 years ago
- fc6de42 Have MachineFunction cache a pointer to the subtarget to make lookups by Eric Christopher · 11 years ago
- d913448 Remove the TargetMachine forwards for TargetSubtargetInfo based by Eric Christopher · 11 years ago
- 0163e03 R600: Remove unused function by Matt Arsenault · 11 years ago
- 762af96 R600: Make ShaderType private by Matt Arsenault · 11 years ago
- 880a80a R600: Use LDS and vectors for private memory by Tom Stellard · 11 years ago
- bc5b537 R600: Remove AMDIL instruction and register definitions by Tom Stellard · 11 years ago
- 2e59a45 R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtarget by Tom Stellard · 11 years ago
- d881e91 R600: Drop use of cached TargetMachine in R600InstrInfo.cpp by Tom Stellard · 11 years ago
- 062a2ba [C++] Use 'nullptr'. Target edition. by Craig Topper · 11 years ago
- d174b72 [cleanup] Lift using directives, DEBUG_TYPE definitions, and even some by Chandler Carruth · 11 years ago
- b6d0bd4 [C++11] Replace llvm::next and llvm::prior with std::next and std::prev. by Benjamin Kramer · 12 years ago
- a64353e R600: Remove successive JUMP in AnalyzeBranch when AllowModify is true by Tom Stellard · 12 years ago
- cd6b0a6 R600: Implement TargetInstrInfo::isLegalToSplitMBBAt() by Tom Stellard · 12 years ago
- d12ccbd [weak vtables] Remove a bunch of weak vtables by Juergen Ributzka · 12 years ago
- 49109a2 Revert r194865 and r194874. by Alexey Samsonov · 12 years ago
- 745d429 R600: Make dot_4 instructions predicable by Vincent Lejeune · 12 years ago
- dbedae8 [weak vtables] Remove a bunch of weak vtables by Juergen Ributzka · 12 years ago
- 8f9fc20 R600: Fix scheduling of instructions that use the LDS output queue by Tom Stellard · 12 years ago
- 81d871d R600/SI: Add support for private address space load/store by Tom Stellard · 12 years ago
- 26a3b67 R600: Simplify handling of private address space by Tom Stellard · 12 years ago
- c460b0d R600: Remove unused InstrInfo::getMovImmInstr() function by Tom Stellard · 12 years ago
- a4da6fb R600: add a pass that merges clauses. by Vincent Lejeune · 12 years ago
- 269708b R600: Enable -verify-machineinstrs in some tests. by Vincent Lejeune · 12 years ago
- d2f96b9 IfConverter: Use TargetSchedule for instruction latencies by Arnold Schwaighofer · 12 years ago
- 7f6fa4c R600: Don't use trans slot for instructions that read LDS source registers by Tom Stellard · 12 years ago
- 744efa4 R600: Use shared op optimization when checking cycle compatibility by Vincent Lejeune · 12 years ago
- 7e2c832 R600: Non vector only instruction can be scheduled on trans unit by Vincent Lejeune · 12 years ago
- 4d5c5e5 R600: Use SchedModel enum for is{Trans,Vector}Only functions by Vincent Lejeune · 12 years ago
- f3d166a R600: Add support for i8 and i16 local memory stores by Tom Stellard · 12 years ago
- 676c16d R600: Add IsExport bit to TableGen instruction definitions by Tom Stellard · 12 years ago
- 0344cdf R600: Add 64-bit float load/store support by Tom Stellard · 12 years ago
- ca69a53 Revert "R600: Non vector only instruction can be scheduled on trans unit" by Tom Stellard · 12 years ago
- 4dd4184 Revert "R600: Use SchedModel enum for is{Trans,Vector}Only functions" by Tom Stellard · 12 years ago
- bb3f931 R600: Avoid more than 4 literals in the same instruction group at scheduling by Vincent Lejeune · 12 years ago
- df18804 R600: Non vector only instruction can be scheduled on trans unit by Vincent Lejeune · 12 years ago
- 79afe17 R600: Use SchedModel enum for is{Trans,Vector}Only functions by Vincent Lejeune · 12 years ago
- 8402144 R600: Move CONST_ADDRESS folding into AMDGPUDAGToDAGISel::Select() by Tom Stellard · 12 years ago
- b94011f Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size. by Craig Topper · 12 years ago
- f04bbd8 Replacing an empty switch with its moral equivalent. No functional changes intended. by Aaron Ballman · 12 years ago
- ce49974 R600: Do not predicated basic block with multiple alu clause by Vincent Lejeune · 12 years ago
- a8a5024 R600: Fix an unitialized variable in R600InstrInfo.cpp by Vincent Lejeune · 12 years ago
- 3969064 R600: Unbreak GCC build. by Benjamin Kramer · 12 years ago
- 77a8352 R600: Support schedule and packetization of trans-only inst by Vincent Lejeune · 12 years ago
- bb8a8721 R600: Bank Swizzle now display SCL equivalent by Vincent Lejeune · 12 years ago
- c026e8b R600: Add local memory support via LDS by Tom Stellard · 12 years ago
- ce54033 R600: Add support for GROUP_BARRIER instruction by Tom Stellard · 12 years ago
- 5eb903d R600: Add ALUInst bit to tablegen definitions v2 by Tom Stellard · 12 years ago
- 02661d9 R600: Use new getNamedOperandIdx function generated by TableGen by Tom Stellard · 12 years ago
- 41d4cf2 R600: PV stores Reg id, not index by Vincent Lejeune · 12 years ago
- a6c6e1b R600: Rework subtarget info and remove AMDILDevice classes by Tom Stellard · 12 years ago
- 37e9adb Don't cache the instruction and register info from the TargetMachine, because by Bill Wendling · 12 years ago
- aad5376 R600: Make sure to schedule AR register uses and defs in the same clause by Tom Stellard · 12 years ago
- c689679 R600: Const/Neg/Abs can be folded to dot4 by Vincent Lejeune · 12 years ago