Gitiles
Code Review Sign In
gerrit-public.fairphone.software / toolchain / llvm-project / 81fe1fbf4abd00b24e078a80cb15a2d2c1343f11 / llvm / lib / Target / AMDGPU / SIInstrInfo.cpp
  1. 16de4fd [AMDGPU] Add sdwa support for ADD|SUB U64 decomposed Pseudos by Ron Lieberman · 7 years ago
  2. ba559ac [AMDGPU] Split 64-Bit XNOR to 64-Bit NOT/XOR by Graham Sellers · 7 years ago
  3. a7b0005 AMDGPU: Divergence-driven selection of scalar buffer load intrinsics by Nicolai Haehnle · 7 years ago
  4. 3d9afa2 [AMDGPU] Combine DPP mov with use instructions (VOP1/2/3) by Valery Pykhtin · 7 years ago
  5. c660386 Revert r347871 "Fix: Add support for TFE/LWE in image intrinsic" by David Stuttard · 7 years ago
  6. 04f7a4d [AMDGPU] Add and update scalar instructions by Graham Sellers · 7 years ago
  7. de02e4b Add support for TFE/LWE in image intrinsics by David Stuttard · 7 years ago
  8. d7eebd6 [CodeGen][NFC] Make `TII::getMemOpBaseImmOfs` return a base operand by Francis Visoiu Mistrih · 7 years ago
  9. 88ce3dc AMDGPU: Record SGPR spills when restoring too by Matt Arsenault · 7 years ago
  10. eabb8dd AMDGPU: Fix analyzeBranch failing with pseudoterminators by Matt Arsenault · 7 years ago
  11. 13d3371 [AMDGPU] Always pass TRI into findRegister[Use/Def]OperandIdx by Stanislav Mekhanoshin · 7 years ago
  12. bc233f5 Revert "AMDGPU: Divergence-driven selection of scalar buffer load intrinsics" by Nicolai Haehnle · 7 years ago
  13. c6c6272 [AMDGPU] Remove FeatureVGPRSpilling by Scott Linder · 7 years ago
  14. b0b741e AMDGPU: Use scavengeRegisterBackwards by Matt Arsenault · 7 years ago
  15. c4a2ff0 AMDGPU: Divergence-driven selection of scalar buffer load intrinsics by Nicolai Haehnle · 7 years ago
  16. 823549a [AMDGPU] Legalize VGPR Rsrc operands for MUBUF instructions by Scott Linder · 7 years ago
  17. 2fb4480 [AMDGPU] Preliminary patch for divergence driven instruction selection. Load offset inlining pattern changed. by Alexander Timofeev · 7 years ago
  18. db7ee76 [AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed by Alexander Timofeev · 7 years ago
  19. 20cbe6f [AMDGPU] Preliminary patch for divergence driven instruction selection. Inline immediate move to V_MADAK_F32. by Alexander Timofeev · 7 years ago
  20. a805c96 [AMDGPU] Preliminary patch for divergence driven instruction selection. Fold immediate SMRD offset. by Alexander Timofeev · 7 years ago
  21. 834cbc6 Revert r341413 by Scott Linder · 7 years ago
  22. dfe089d [AMDGPU] Legalize VGPR Rsrc operands for MUBUF instructions by Scott Linder · 7 years ago
  23. 0da6350 AMDGPU: Remove remnants of old address space mapping by Matt Arsenault · 7 years ago
  24. 283b995 AMDGPU: Fix getInstSizeInBytes by Nicolai Haehnle · 7 years ago
  25. de6c421 AMDGPU: Shrink insts to fold immediates by Matt Arsenault · 7 years ago
  26. 35b1902 AMDGPU: Move canShrink into TII by Matt Arsenault · 7 years ago
  27. 904343f [AMDGPU] Add support for multi-dword s.buffer.load intrinsic by Tim Renouf · 7 years ago
  28. 5ca4128 [PSV] Update API to be able to use TargetCustom without UB. by Marcello Maggioni · 7 years ago
  29. c73c030 [MI] Change the array of `MachineMemOperand` pointers to be by Chandler Carruth · 7 years ago
  30. 7f0d05d AMDGPU: Force skip over s_sendmsg and exp instructions by Nicolai Haehnle · 7 years ago
  31. 0183c56 AMDGPU: Fix code size for return_to_epilog pseudo by Matt Arsenault · 7 years ago
  32. 5bfbae5 AMDGPU: Refactor Subtarget classes by Tom Stellard · 7 years ago
  33. c5a154d AMDGPU: Separate R600 and GCN TableGen files by Tom Stellard · 7 years ago
  34. 739174c [AMDGPU] Construct memory clauses before RA by Stanislav Mekhanoshin · 7 years ago
  35. 44b30b4 AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headers by Tom Stellard · 7 years ago
  36. 4329361 [AMDGPU] Added checks for dpp_ctrl value by Stanislav Mekhanoshin · 7 years ago
  37. 5f8f34e4 Remove \brief commands from doxygen comments. by Adrian Prantl · 7 years ago
  38. 0084adc AMDGPU: Add Vega12 and Vega20 by Matt Arsenault · 7 years ago
  39. a4bfb3c [AMDGPU] Truncate packed inline constant by Stanislav Mekhanoshin · 7 years ago
  40. b21f959 AMDGPU: Move a flawed assert when spilling SGPRs by Matt Arsenault · 7 years ago
  41. adc59d7 AMDGPU: Assign enum name to stack ID by Matt Arsenault · 7 years ago
  42. 7a87977 AMDGPU: Legalize the operand of SI_INIT_M0 by Nicolai Haehnle · 7 years ago
  43. 160f857 [AMDGPU] Use packed literals with zero either lower or hi part by Stanislav Mekhanoshin · 7 years ago
  44. 13e77db Fix layering of MachineValueType.h by moving it from CodeGen to Support by David Blaikie · 8 years ago
  45. 69932e4 AMDGPU: Don't leave dead illegal VGPR->SGPR copies by Matt Arsenault · 8 years ago
  46. 2a99fa2 [AMDGPU] added writelane intrinsic by Tim Renouf · 8 years ago
  47. 7d92b7e AMDGPU: Fix S_BUFFER_LOAD_DWORD_SGPR moveToVALU by Marek Olsak · 8 years ago
  48. d4bb329 AMDGPU: Fold inline offset for loads properly in moveToVALU on GFX9 by Marek Olsak · 8 years ago
  49. f1caa28 MachineFunction: Return reference from getFunction(); NFC by Matthias Braun · 8 years ago
  50. 5f7f32c [AMDGPU] SDWA: add support for PRESERVE into SDWA peephole. by Sam Kolton · 8 years ago
  51. 686d5c7 AMDGPU: Use carry-less adds in FI elimination by Matt Arsenault · 8 years ago
  52. 84445dd AMDGPU: Use gfx9 carry-less add/sub instructions by Matt Arsenault · 8 years ago
  53. 39980da AMDGPU: Consistently check for immediates in SIInstrInfo::FoldImmediate by Nicolai Haehnle · 8 years ago
  54. b3bde2e Fix a bunch more layering of CodeGen headers that are in Target by David Blaikie · 8 years ago
  55. 301162c AMDGPU: Replace i64 add/sub lowering by Matt Arsenault · 8 years ago
  56. ffadcb7 AMDGPU: Fold immediate offset into BUFFER_LOAD_DWORD lowered from SMEM by Marek Olsak · 8 years ago
  57. 5914ece AMDGPU: Select s_buffer_load_dword with a non-constant SGPR offset by Marek Olsak · 8 years ago
  58. ce76ea0 AMDGPU: Add new intrinsic llvm.amdgcn.kill(i1) by Marek Olsak · 8 years ago
  59. 9ab1fa6 AMDGPU: Fix not accounting for instruction size in bundles by Matt Arsenault · 8 years ago
  60. ce4ddd0 AMDGPU: VALU carry-in and v_cndmask condition cannot be EXEC by Nicolai Haehnle · 8 years ago
  61. fdcdd88 AMDGPU: Fix crash on immediate operand by Matt Arsenault · 8 years ago
  62. ca8946a AMDGPU: Start selecting s_xnor_{b32, b64} by Konstantin Zhuravlyov · 8 years ago
  63. 1f2f57a7 Fix warnings in r313297. by Jan Sjodin · 8 years ago
  64. c317287 AMDGPU: Fix violating constant bus restriction by Matt Arsenault · 8 years ago
  65. 312ccf7 Add AddresSpace to PseudoSourceValue. by Jan Sjodin · 8 years ago
  66. ecb43ef AMDGPU: Don't spill SP reg like a normal CSR by Matt Arsenault · 8 years ago
  67. 7fe9a5d Allow target to decide when to cluster loads/stores in misched by Stanislav Mekhanoshin · 8 years ago
  68. 710da42 [AMDGPU] Produce madak and madmk from the two-address pass by Stanislav Mekhanoshin · 8 years ago
  69. 949fac9 [AMDGPU] Fix shouldClusterMemOps to process flat loads by Stanislav Mekhanoshin · 8 years ago
  70. 59e1282 [AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). by Eugene Zelenko · 8 years ago
  71. 66b9bd6 [AMDGPU] Implement llvm.amdgcn.set.inactive intrinsic by Connor Abbott · 8 years ago
  72. 92638ab [AMDGPU] Add support for Whole Wavefront Mode by Connor Abbott · 8 years ago
  73. 8c217d0 [AMDGPU] Add an llvm.amdgcn.wqm intrinsic for WQM by Connor Abbott · 8 years ago
  74. 8623e8d AMDGPU: Pass special input registers to functions by Matt Arsenault · 8 years ago
  75. 9608a289 AMDGPU: Make areMemAccessesTriviallyDisjoint more aware of segment flat by Matt Arsenault · 8 years ago
  76. 37a58e0 AMDGPU: Fix getMemOpBaseRegImmOfs for flat with offsets by Matt Arsenault · 8 years ago
  77. db78273 Add an ID field to StackObjects by Matt Arsenault · 8 years ago
  78. 5b27072 [AMDGPU] Do not insert an instruction into worklist twice in movetovalu by Alfred Huang · 8 years ago
  79. 0f5b350 [AMDGPU] Fix -Wimplicit-fallthrough warnings. NFCI. by Simon Pilgrim · 8 years ago
  80. 3f031e7 AMDGPU: Add operand target flags serialization by Matt Arsenault · 8 years ago
  81. a179d25 [AMDGPU] SDWA: several fixes for V_CVT and VOPC instructions by Sam Kolton · 8 years ago
  82. 43cc6c4 AMDGPU: M0 operands to spill/restore opcodes are dead by Nicolai Haehnle · 8 years ago
  83. 3c4933f [AMDGPU] SDWA: add support for GFX9 in peephole pass by Sam Kolton · 8 years ago
  84. 549c89d [AMDGPU] SDWA: merge VI and GFX9 pseudo instructions by Sam Kolton · 8 years ago
  85. 05c2647 AMDGPU: Don't add same implicit use multiple times by Matt Arsenault · 8 years ago
  86. 89ad17c AMDGPU: Verify that flat offsets aren't used pre-GFX9 by Matt Arsenault · 8 years ago
  87. 6bda14b Sort the remaining #include lines in include/... and lib/.... by Chandler Carruth · 8 years ago
  88. dde28a8 AMDGPU/GlobalISel: Mark 32-bit float constants as legal by Tom Stellard · 8 years ago
  89. ea8a4ed AMDGPU: Use appropriate soffset for spilling by Matt Arsenault · 8 years ago
  90. 994a43d AMDGPUCodeGen: Fix warnings in r303111. [-Wunused-variable] by NAKAMURA Takumi · 8 years ago
  91. a06bfe0 Re-submit AMDGPUMachineCFGStructurizer. by Jan Sjodin · 8 years ago
  92. 0e28982 Revert 303091. by Jan Sjodin · 8 years ago
  93. e9d2ddc Add AMDGPUMachineCFGStructurizer. by Jan Sjodin · 8 years ago
  94. 44e25f3 Move size and alignment information of regclass to TargetRegisterInfo by Krzysztof Parzyszek · 8 years ago
  95. 5dea645 AMDGPU: Move v_readlane lane select from VGPR to SGPR by Nicolai Haehnle · 8 years ago
  96. ef44978 AMDGPU: Fix crash when scheduling non-memory SMRD instructions by Nicolai Haehnle · 8 years ago
  97. 88938d4 AMDGPU: Fix S_PACK_HH_B32_B16 - We really ought to zero out lower 16 bits by Konstantin Zhuravlyov · 8 years ago
  98. 86b0a54 [AMDGPU] added SIInstrInfo::getAddNoCarry() helper by Stanislav Mekhanoshin · 8 years ago
  99. d24aeb2 AMDGPU/GFX9: Do not use v_pack_b32_f16 when packing by Konstantin Zhuravlyov · 8 years ago
  100. 21a4382 AMDGPU: Diagnose illegal SGPR to VGPR copies by Matt Arsenault · 8 years ago