Log - 81fe1fbf4abd00b24e078a80cb15a2d2c1343f11 - toolchain/llvm-project

f192cdb [ARM] ComputeKnownBits to handle extract vectors by Diogo N. Sampaio · 7 years ago
d800ee4 [ARM] Always use the version of computeKnownBits that returns a value. NFCI. by Simon Pilgrim · 7 years ago
b1bbd5d [ARM] Complete the Thumb1 shift+and->shift+shift transforms. by Eli Friedman · 7 years ago
ae3b66b ARM: use acquire/release instruction variants when available. by Tim Northover · 7 years ago
5745b6a ARM: use target-specific SUBS node when combining cmp with cmov. by Tim Northover · 7 years ago
ecc7dcb [ARM] Don't expand sdiv when optimising for minsize by Sjoerd Meijer · 7 years ago
7d7d41d [ARM] Fix CPSR liveness in tMOVCCr_pseudo lowering. by Eli Friedman · 7 years ago
30f1d69 [NFC] Rename minnan and maxnan to minimum and maximum by Thomas Lively · 7 years ago
4bb928c ARM: Use BKPT instead of TRAP to implement llvm.debugtrap. by Peter Collingbourne · 7 years ago
4005f9a ARM: handle checking aliases with out-of-bounds GEPs by Saleem Abdulrasool · 7 years ago
5abb607 [ARM][NEON] Improve vector popcnt lowering with PADDL (PR39281) by Simon Pilgrim · 7 years ago
5ab09a6 [ARM] Fix correctness checks in promoteToConstantPool. by Eli Friedman · 7 years ago
bb993be [ARM] Use preferred alignment for constants in promoteToConstantPool. by Eli Friedman · 7 years ago
0a0c2e6 [ARM] Share predecessor bookkeeping in CombineBaseUpdate. NFCI. by Nirav Dave · 7 years ago
79518b0 [AtomicExpandPass]: Add a hook for custom cmpxchg expansion in IR by Alex Bradbury · 7 years ago
c15d47b ARM: align loops to 4 bytes on Cortex-M3 and Cortex-M4. by Tim Northover · 7 years ago
68df812 [MinGW] Move code for indicating "potentially not DSO local" into shouldAssumeDSOLocal. NFC. by Martin Storsjo · 7 years ago
2dcaa41 [MinGW] [ARM] Add stubs for potential automatic dllimported variables by Martin Storsjo · 7 years ago
96e3cd8 [ARM] Lower llvm.ctlz.i32 to a libcall when clz is not available. by Eli Friedman · 7 years ago
c11e2b9 [ARM] Handle all-ones mask explicitly in targetShrinkDemandedConstant. by Eli Friedman · 7 years ago
9dd1d45 [AArch64] Add Tiny Code Model for AArch64 by David Green · 7 years ago
66654b7 [SDAG] Remove the reliance on MI's allocation strategy for by Chandler Carruth · 7 years ago
0d12e90 [ARM] Make PerformSHLSimplify add nodes to the DAG worklist correctly. by Eli Friedman · 7 years ago
6b84a48 Fix unused lambda capture warning from r339472. by Eli Friedman · 7 years ago
e1687a89 [ARM] Adjust AND immediates to make them cheaper to select. by Eli Friedman · 7 years ago
b33a4c0 [ARM] FP16: support vector INT_TO_FP and FP_TO_INT by Sjoerd Meijer · 7 years ago
b264944 [ARM] FP16: support the vector vmin and vmax variants by Sjoerd Meijer · 7 years ago
f78650a Remove trailing space by Fangrui Song · 7 years ago
733f4ed [ARM] Prefer lsls+lsrs over lsls+ands or lsrs+ands in Thumb1. by Eli Friedman · 7 years ago
e00cf4f ARM: stop explicitly marking armv7k libcalls as hard-float. NFC. by Tim Northover · 7 years ago
d2c7392 [ARM] Treat cmn immediates as legal in isLegalICmpImmediate. by Eli Friedman · 7 years ago
4660379 [NEON] Fix combining of vldx_dup intrinsics with updating of base addresses by Ivan A. Kosarev · 7 years ago
fd10286 [ARM] Fix PR37382: Don't optimize mul.with.overflow on thumbv6m. by Vadzim Dambrouski · 7 years ago
7231598 [NEON] Support vldNq intrinsics in AArch32 (LLVM part) by Ivan A. Kosarev · 7 years ago
847daa1 [NEON] Support VST1xN intrinsics in AArch32 mode (LLVM part) by Ivan A. Kosarev · 7 years ago
60a991e [NEON] Support VLD1xN intrinsics in AArch32 mode (LLVM part) by Ivan A. Kosarev · 7 years ago
73c5337 Revert r333819 "[NEON] Support VLD1xN intrinsics in AArch32 mode (Clang part)" by Ivan A. Kosarev · 7 years ago
51f19b9 [NEON] Support VLD1xN intrinsics in AArch32 mode (Clang part) by Ivan A. Kosarev · 7 years ago
f47d9f3 [ARM] Remove code handling ADDC/ADDE/SUBC/SUBE by Amaury Sechet · 7 years ago
63fead0 [ARM] Enable SETCCCARRY lowering for Thumb1. by Eli Friedman · 7 years ago
4e3eec3 ARM: be conservative when asked load/store alignment of weird type. by Tim Northover · 7 years ago
d34e60c Rename DEBUG macro to LLVM_DEBUG. by Nicola Zaghen · 7 years ago
4f729f6 [ARM] Add support for SETCCCARRY instead of SETCCE by Amaury Sechet · 7 years ago
f91b6a8 [ARM] Select result 1 from ConvertBooleanCarryToCarryFlag's result automatically. NFC by Amaury Sechet · 7 years ago
28e0a6f ARM: don't try to over-align large vectors as arguments. by Tim Northover · 7 years ago
5f8f34e4 Remove \brief commands from doxygen comments. by Adrian Prantl · 7 years ago
834f7dc [ARM] FP16 vmaxnm/vminnm scalar instructions by Sjoerd Meijer · 7 years ago
ac96d7c [ARM] FP16 VSEL codegen by Sjoerd Meijer · 7 years ago
2fa1436 [IR][CodeGen] Remove dependency on EVT from IR/Function.cpp. Move EVT to CodeGen layer. by Craig Topper · 7 years ago
a1e77c0 [ARM] Support float literals under XO by Christof Douma · 7 years ago
36a0f22 Fix layering by moving ValueTypes.h from CodeGen to IR by David Blaikie · 8 years ago
13e77db Fix layering of MachineValueType.h by moving it from CodeGen to Support by David Blaikie · 8 years ago
4a025cc [ARM] Support float literals under XO by Christof Douma · 8 years ago
9a55c1b [ARM, AArch64] Check the no-stack-arg-probe attribute for dynamic stack probes by Martin Storsjo · 8 years ago
d16037d [ARM] Support for v4f16 and v8f16 vectors by Sjoerd Meijer · 8 years ago
d391a1a [ARM] FP16 codegen support for VSEL by Sjoerd Meijer · 8 years ago
af30f06 [ARM] Fix for PR36577 by Sjoerd Meijer · 8 years ago
9f9e468 [TLS] use emulated TLS if the target supports only this mode by Chih-Hung Hsieh · 8 years ago
512f7ee [ARM] Lower lower saturate to 0 and lower saturate to -1 using bit-operations by Pablo Barrio · 8 years ago
f8bf2ec [MachineOperand][Target] MachineOperand::isRenamable semantics changes by Geoff Berry · 8 years ago
4d5c404 [ARM] Lower BR_CC for f16 by Sjoerd Meijer · 8 years ago
d41059a [ARM] Materialise some boolean values to avoid a branch by Roger Ferrer Ibanez · 8 years ago
e28cb83 [ARM] Allow 64- and 128-bit types with 't' inline asm constraint by Pablo Barrio · 8 years ago
89ea264 [ARM] Armv8.2-A FP16 code generation (part 3/3) by Sjoerd Meijer · 8 years ago
9d9a865 [ARM] FullFP16 LowerReturn Fix by Sjoerd Meijer · 8 years ago
7746899 Revert "[ARM] Lower lower saturate to 0 and lower saturate to -1 using bit-operations" by Evgeniy Stepanov · 8 years ago
2e442a7 [ARM] Lower lower saturate to 0 and lower saturate to -1 using bit-operations by Pablo Barrio · 8 years ago
98d5359 [ARM] Armv8.2-A FP16 code generation (part 2/3) by Sjoerd Meijer · 8 years ago
011de9c [ARM] Armv8.2-A FP16 code generation (part 1/3) by Sjoerd Meijer · 8 years ago
665784f [ARM] Expand long shifts for Thumb1 to __aeabi_ calls by Weiming Zhao · 8 years ago
4ed94a0 [ARM] Call __chkstk for dynamic stack allocation in all windows environments by Martin Storsjo · 8 years ago
bbcaf4a [ARM] Optimize {s,u}mul.with.overflow. by Joel Galenson · 8 years ago
5627c21 [ARM] Add codegen for SMMULR, SMMLAR and SMMLSR by Andre Vieira · 8 years ago
6f4e827 [ARM] Optimize {s,u}{add,sub}.with.overflow. by Joel Galenson · 8 years ago
c3aa6d8 [ARM] Lower unsigned saturation to USAT by Florian Hahn · 8 years ago
0e6694d Silence a bunch of implicit fallthrough warnings by Adrian Prantl · 8 years ago
a4852d2c X86/AArch64/ARM: Factor out common sincos_stret logic; NFCI by Matthias Braun · 8 years ago
f1caa28 MachineFunction: Return reference from getFunction(); NFC by Matthias Braun · 8 years ago
7d7adf4 TLI: Allow using PSV for intrinsic mem operands by Matt Arsenault · 8 years ago
1117133 DAG: Expose all MMO flags in getTgtMemIntrinsic by Matt Arsenault · 8 years ago
60c4310 [MachineOperand][MIR] Add isRenamable to MachineOperand. by Geoff Berry · 8 years ago
5ea0f25 [ARM] Use ADDCARRY / SUBCARRY by Roger Ferrer Ibanez · 8 years ago
a8a83d1 [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register. by Francis Visoiu Mistrih · 8 years ago
2b43858 Fix function pointer tail calls in armv8-M.base by Pablo Barrio · 8 years ago
c85cc41 [ARM] Allow using emulated tls on platforms other than ELF by Martin Storsjo · 8 years ago
b3bde2e Fix a bunch more layering of CodeGen headers that are in Target by David Blaikie · 8 years ago
39bcd4e [ARM] 't' asm constraint should accept i32 by Yi Kong · 8 years ago
4629f52 [ARM, AArch64] Fix an assert message, Darwin isn't the only target supporting TLS. NFC. by Martin Storsjo · 8 years ago
76d5ac4 [arm] Fix Unnecessary reloads from GOT. by Evgeniy Stepanov · 8 years ago
842aa90 [ARM] Place jump table as the first operand in additions by Momchil Velikov · 8 years ago
3f833ed Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering by David Blaikie · 8 years ago
242052c [ARM] and, or, xor and add with shl combine by Sam Parker · 8 years ago
9dfbc10 Revert r313618 "[ARM] Use ADDCARRY / SUBCARRY" by Roger Ferrer Ibanez · 8 years ago
d5dfb62 [ARM] Honor -mfloat-abi for libcall calling convention by Eli Friedman · 8 years ago
1f74211 [ARM] OrCombineToBFI function by Sam Parker · 8 years ago
ccb209b [ARM] Swap cmp operands for automatic shifts by Sam Parker · 8 years ago
7a22a49 ISel type legalization: add debug messages. NFCI. by Sjoerd Meijer · 8 years ago
211f47a [ARM] isTruncateFree fix by Sam Parker · 8 years ago
076468c [ARM] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). by Eugene Zelenko · 8 years ago
8d0180c [ARM] Use ADDCARRY / SUBCARRY by Roger Ferrer Ibanez · 8 years ago