Gitiles
Code Review Sign In
gerrit-public.fairphone.software / toolchain / llvm-project / 81fe1fbf4abd00b24e078a80cb15a2d2c1343f11 / llvm / lib / Target / ARM / Thumb1InstrInfo.cpp
  1. aea4208 [ARM] Allow the scheduler to clone a node with glue to avoid a copy CPSR ↔ GPR. by Roger Ferrer Ibanez · 8 years ago
  2. d2cc6fd [ARM] Accept a subset of Thumb GPR register class when emitting an SP-relative by Momchil Velikov · 8 years ago
  3. caf9ea6 Remove redundant includes from lib/Target/ARM. by Michael Zolotukhin · 8 years ago
  4. 6bda14b Sort the remaining #include lines in include/... and lib/.... by Chandler Carruth · 8 years ago
  5. 9b9a535 Re-commit r301040 "X86: Don't emit zero-byte functions on Windows" by Hans Wennborg · 8 years ago
  6. 0459300 Revert r301040 "X86: Don't emit zero-byte functions on Windows" by Hans Wennborg · 8 years ago
  7. cb3e810 X86: Don't emit zero-byte functions on Windows by Hans Wennborg · 8 years ago
  8. 1388e2f In Thumb1, materialize a move between low registers as a `movs`, if CPSR isn't live. by Artyom Skrobov · 9 years ago
  9. 4f8c3e1 [ARM] CodeGen: Remove AddDefaultPred. NFC. by Diana Picus · 9 years ago
  10. 941a705 MachineFunction: Return reference for getFrameInfo(); NFC by Matthias Braun · 9 years ago
  11. 82f4631 Don't pass Reloc::Model to places that already have it. NFC. by Rafael Espindola · 9 years ago
  12. bdc4956 Pass DebugLoc and SDLoc by const ref. by Benjamin Kramer · 9 years ago
  13. e40c8a2 PseudoSourceValue: Replace global manager with a manager in a machine function. by Alex Lorenz · 10 years ago
  14. 0d28f80 Rename all references to old mailing lists to new lists.llvm.org address. by Tanya Lattner · 10 years ago
  15. e9119e4 MC: Modernize MCOperand API naming. NFC. by Jim Grosbach · 10 years ago
  16. 3408583 Remove the need to cache the subtarget in the ARM TargetRegisterInfo by Eric Christopher · 11 years ago
  17. 22b2ad2 Get the cached subtarget off the MachineFunction rather than by Eric Christopher · 11 years ago
  18. 44937d9 Lower thumbv4t & thumbv5 lo->lo copies through a push-pop sequence by Jonathan Roelofs · 11 years ago
  19. dc08c30 [ARM] In dynamic-no-pic mode, ARM's post-RA pseudo expansion was incorrectly by Akira Hatanaka · 11 years ago
  20. e5b6e0d [stack protector] Fix a potential security bug in stack protector where the by Akira Hatanaka · 11 years ago
  21. a925326 Prune includes in ARM target. by Craig Topper · 12 years ago
  22. f95178e Don't cache the instruction and register info from the TargetMachine, because by Bill Wendling · 12 years ago
  23. ed0881b Use the new script to sort the includes of every file under lib. by Chandler Carruth · 13 years ago
  24. c7242e0 Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent. by Craig Topper · 13 years ago
  25. 1fcf5bc Prune some includes by Craig Topper · 14 years ago
  26. 188ed9d Reorder includes to match coding standards. Fix an issue or two exposed by that. by Craig Topper · 14 years ago
  27. 617f84dd ARM implement TargetInstrInfo::getNoopForMachoTarget() by Jim Grosbach · 14 years ago
  28. b22310f Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. by Jia Liu · 14 years ago
  29. 465101b Make use of MachinePointerInfo::getFixedStack. This removes all mention by Jay Foad · 14 years ago
  30. e9cc901 Refact ARM Thumb1 tMOVr instruction family. by Jim Grosbach · 14 years ago
  31. b98ab91 Thumb1 register to register MOV instruction is predicable. by Jim Grosbach · 14 years ago
  32. d86f34d Refactor away tSpill and tRestore pseudos in ARM backend. by Jim Grosbach · 14 years ago
  33. 1e210d0 Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc by Evan Cheng · 14 years ago
  34. d08fbd1 Move callee-saved regs spills / reloads to TFI by Anton Korobeynikov · 15 years ago
  35. e3d864b convert targets to the new MF.getMachineMemOperand interface. by Chris Lattner · 15 years ago
  36. 0961c55 RISC architectures get their memory operand folding for free. by Jakob Stoklund Olesen · 15 years ago
  37. d7b3300 Replace copyRegToReg with copyPhysReg for ARM. by Jakob Stoklund Olesen · 15 years ago
  38. c5d7122 Thumb1 functions using @llvm.returnaddress were not saving the incoming LR. by Bob Wilson · 15 years ago
  39. 44f9dfc Next round of tail call changes. Register used in a tail by Dale Johannesen · 15 years ago
  40. 168ced9 Implement @llvm.returnaddress. rdar://8015977. by Evan Cheng · 15 years ago
  41. 779c69b Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it by Dan Gohman · 15 years ago
  42. efb126a Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot. by Evan Cheng · 15 years ago
  43. 6f306d7 use DebugLoc default ctor instead of DebugLoc::getUnknownLoc() by Chris Lattner · 15 years ago
  44. 7d116ce Don't leak a MachineInstruction from Thumb1InstrInfo::restoreCalleeSavedRegisters. by Jeffrey Yasskin · 16 years ago
  45. 947f04b Change ARM ld/st multiple instructions to have variant instructions for by Bob Wilson · 16 years ago
  46. d1a8a78 Update Thumb1 storeRegToStackSlot() and loadRegFromStackSlot() to properly by Jim Grosbach · 16 years ago
  47. 30f2ac7 Silence a clang warning about the deprecated (but perfectly reasonable in by John McCall · 16 years ago
  48. 047a767 Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor of by Dan Gohman · 16 years ago
  49. fe86442 Refactor code. by Evan Cheng · 16 years ago
  50. 4e9f379 80-column cleanup of file header comments by Jim Grosbach · 16 years ago
  51. 8b5278a t2ldrpci_pic can be used for blockaddress as well. by Evan Cheng · 16 years ago
  52. 207b246 - Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative by Evan Cheng · 16 years ago
  53. 14635da Use NEON reg-reg moves, where profitable. This reduces "domain-cross" stalls, when we used to mix vfp and neon code (the former were used for reg-reg moves) by Anton Korobeynikov · 16 years ago
  54. 1a4492b Fix a couple more places where we are creating ld / st instructions without memoperands. by Evan Cheng · 16 years ago
  55. 73789b8 Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate the by Bob Wilson · 16 years ago
  56. b659dff Forgot about ARM::tPUSH. It also has a new writeback operand. by Evan Cheng · 16 years ago
  57. 6f012d8 ARM::tPOP and tPOP_RET each has an extra writeback operand now. by Evan Cheng · 16 years ago
  58. e5801bd It's ok to spill a tGPR register as long as it's still allocated a low register. by Evan Cheng · 16 years ago
  59. cc9ca35 Shrinkify Thumb2 load / store multiple instructions. by Evan Cheng · 16 years ago
  60. e98a3c3 Move the getInlineAsmLength virtual method from TAI to TII, where by Chris Lattner · 16 years ago
  61. 780748d - More refactoring. This gets rid of all of the getOpcode calls. by Evan Cheng · 16 years ago
  62. 38b7eee More DCE. by Evan Cheng · 16 years ago
  63. 18688f4 Get rid of more dead code. by Evan Cheng · 16 years ago
  64. 056c669 Get rid of some more getOpcode calls. by Evan Cheng · 16 years ago
  65. c47e109 Use t2LDRi12 and t2STRi12 to load / store to / from stack frames. Eliminate more getOpcode calls. by Evan Cheng · 16 years ago
  66. 0e5b149 Merge isLoadFromStackSlot into one since it behaves the same regardless of sub-target. by Evan Cheng · 16 years ago
  67. 26b51b1 Just use a single isMoveInstr to catch all the cases. by Evan Cheng · 16 years ago
  68. faede73 Rename tMOVhi2lor to tMOVgpr2tgpr. It's not moving from a high register to a low register. It's moving from a GPR register class to a more restrictive tGPR class. Also change tMOVlor2hir, and tMOVhir2hir. by Evan Cheng · 16 years ago
  69. f3a1fce Change Thumb2 jumptable codegen to one that uses two level jumps: by Evan Cheng · 16 years ago
  70. 95fc6ee Remove unused member functions. by Eli Friedman · 16 years ago
  71. 6cfbe61 FLDD, FLDS, FCPYD, FCPYS, FSTD, FSTS, VMOVD, VMOVQ maps to the same instructions on all sub-targets. by Evan Cheng · 16 years ago
  72. cdd405d Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen. by David Goodwin · 16 years ago
  73. 6deba28 Fix frame index elimination to correctly handle thumb-2 addressing modes that don't allow negative offsets. During frame elimination convert *i12 opcode to a *i8 when necessary due to a negative offset. by David Goodwin · 16 years ago
  74. c5df7e2 Emit cross regclass register moves for thumb2. Minor code duplication cleanup. by Anton Korobeynikov · 16 years ago
  75. cd4cdd1 Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically. by Evan Cheng · 16 years ago
  76. 03ab0bb Generalize opcode selection in ARMBaseRegisterInfo. by David Goodwin · 16 years ago
  77. af7451b Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first. by David Goodwin · 16 years ago
  78. ade05a3 Checkpoint refactoring of ThumbInstrInfo and ThumbRegisterInfo into Thumb1InstrInfo, Thumb2InstrInfo, Thumb1RegisterInfo and Thumb2RegisterInfo. Move methods from ARMInstrInfo to ARMBaseInstrInfo to prepare for sharing with Thumb2. by David Goodwin · 16 years ago[Copied (83%) from llvm/lib/Target/ARM/ThumbInstrInfo.cpp]
  79. 0f2158b Simplify a bit by Anton Korobeynikov · 16 years ago
  80. a1b5b18 ARM refactoring. Step 2: split RegisterInfo by Anton Korobeynikov · 16 years ago
  81. 99152f3 Split thumb-related stuff into separate classes. by Anton Korobeynikov · 16 years ago