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gerrit-public.fairphone.software / toolchain / llvm-project / 9560af848c3df64a1cb84d402e03384d2b0732fe / llvm / lib / Target / ARM / Disassembler / ARMDisassembler.cpp
  1. 9560af8 Fixed disassembler for vstm/vldm ARM VFP instructions. by Silviu Baranga · 13 years ago
  2. 9d8f6f3 ARM: Tweak tADDrSP definition for consistent operand order. by Jim Grosbach · 13 years ago
  3. f435b09 Refactor IT handling not to store the bottom bit of the condition code in the mask operand in the MCInst. by Richard Barton · 13 years ago
  4. e960000 Refactor Thumb ITState handling in ARM Disassembler to more efficiently use its vector by Richard Barton · 13 years ago
  5. ca45af9 Added support for disassembling unpredictable swp/swpb ARM instructions. by Silviu Baranga · 13 years ago
  6. 41f1fcd Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the disassembler. Since the upredicability conditions are complex, C++ code was added to handle them. by Silviu Baranga · 13 years ago
  7. 29ae538 Fix ARM disassembly of VLD2 (single 2-element structure to all lanes) by Kevin Enderby · 13 years ago
  8. 40d4e47 Fix a few more places in the ARM disassembler so that branches get by Kevin Enderby · 14 years ago
  9. 72f18bb Fixed a case of ARM disassembly getting an assert on a bad encoding by Kevin Enderby · 14 years ago
  10. d2980cd Fix ARM disassembly of VLD instructions with writebacks.  And add test a case by Kevin Enderby · 14 years ago
  11. 7a3973d ARMDisassembler: drop bogus dependency on ARMCodeGen by Dylan Noblesmith · 14 years ago
  12. f6e7e12 Remove unnecessary llvm:: qualifications by Craig Topper · 14 years ago
  13. 4afd7d2 Added soft fail checks for the disassembler when decoding some corner cases of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM. by Silviu Baranga · 14 years ago
  14. d213f21 Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDRSHT instruction on ARM by Silviu Baranga · 14 years ago
  15. 7e7d5ee Fix ARM disassembly of VST1 and VST2 instructions with writeback. And add test by Kevin Enderby · 14 years ago
  16. 32a4933 The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this. by Silviu Baranga · 14 years ago
  17. ca658c2 Use uint16_t to store registers and opcode in static tables in the target specific backends. by Craig Topper · 14 years ago
  18. eed9992 Tidy up. Remove dead code that slipped into previous commit. by Jim Grosbach · 14 years ago
  19. ed428bc ARM more NEON VLD/VST composite physical register refactoring. by Jim Grosbach · 14 years ago
  20. 13a292c ARM refactor more NEON VLD/VST instructions to use composite physregs by Jim Grosbach · 14 years ago
  21. 520eb3b Fix a bug in the ARM disassembly of the neon VLD2 all lanes instruction. by Kevin Enderby · 14 years ago
  22. e5307f9 ARM Refactor VLD/VST spaced pair instructions. by Jim Grosbach · 14 years ago
  23. c988e0c ARM refactor away a bunch of VLD/VST pseudo instructions. by Jim Grosbach · 14 years ago
  24. 56b662c Make MemoryObject accessor members const again by Derek Schuff · 14 years ago
  25. 1489b52 Fix the symbolic operand added for the C disassmbler API for the ARM bl by Kevin Enderby · 14 years ago
  26. 6fbcd8d Updated the llvm-mc disassembler C API to support for the X86 target. by Kevin Enderby · 14 years ago
  27. b22310f Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. by Jia Liu · 14 years ago
  28. 428704e Make the EDis tables const. by Benjamin Kramer · 14 years ago
  29. e55c556 Convert assert(0) to llvm_unreachable by Craig Topper · 14 years ago
  30. 8b2dcad Enable streaming of bitcode by Derek Schuff · 14 years ago
  31. 46a9f01 More dead code removal (using -Wunreachable-code) by David Blaikie · 14 years ago
  32. 4a5c887 ARM NEON VTBL/VTBX assembly parsing and encoding. by Jim Grosbach · 14 years ago
  33. 88ac761 ARM NEON refactor VST2 w/ writeback instructions. by Jim Grosbach · 14 years ago
  34. 8d24618 ARM NEON VST2 assembly parsing and encoding. by Jim Grosbach · 14 years ago
  35. d146a02 ARM assembly parsing and encoding for VLD2 with writeback. by Jim Grosbach · 14 years ago
  36. 23c30b9 Remove unused variable by Matt Beaumont-Gay · 14 years ago
  37. a68c9a8 ARM parsing for VLD1 all lanes, with writeback. by Jim Grosbach · 14 years ago
  38. 5ee209c ARM assembly parsing and encoding for four-register VST1. by Jim Grosbach · 14 years ago
  39. 98d032f ARM assembly parsing and encoding for three-register VST1. by Jim Grosbach · 14 years ago
  40. 05060f0 Fix a misplaced paren bug. by Owen Anderson · 14 years ago
  41. 0ac9058 Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32. by Owen Anderson · 14 years ago
  42. 8ca13de Re-apply 144430, this time with the associated isel and disassmbler bits. by Jim Grosbach · 14 years ago
  43. 48b5bbf Remove the unnecessary dependency on libARMCodeGen from libARMDisassembler. by Benjamin Kramer · 14 years ago
  44. ec5c5f70 The rules disallowing single-register reglist operands only apply to the POP alias, not to LDM/STM instructions. Revert r143552. by Owen Anderson · 14 years ago
  45. fad59da Register list operands are not allowed to contain only a single register. Alternate encodings are used in that case. by Owen Anderson · 14 years ago
  46. 69e54a7 Fix disassembly of some VST1 instructions. by Owen Anderson · 14 years ago
  47. 05df460 ARM VST1 w/ writeback assembly parsing and encoding. by Jim Grosbach · 14 years ago
  48. 40703f4 More not-crashing NEON disassembly updates for the vld refactoring. by Owen Anderson · 14 years ago
  49. dde461c Reapply r143202, with a manual decoding hook for SWP. This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle. by Owen Anderson · 14 years ago
  50. 8a6ebd0 Add some NEON stores to the VLD decoding hook that were accidentally omitted previously. by Owen Anderson · 14 years ago
  51. 17ec1a1 ARM assembly parsing and encoding for VLD1 with writeback. by Jim Grosbach · 14 years ago
  52. 92fd05e ARM assembly parsing and encoding for VLD1 w/ writeback. by Jim Grosbach · 14 years ago
  53. 2098cb1 ARM refactor am6offset usage for VLD1. by Jim Grosbach · 14 years ago
  54. 295b1e8 Fix a NEON disassembly case that was broken in the recent refactorings. As more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely. by Owen Anderson · 14 years ago
  55. 0d6d098 Move various generated tables into read-only memory, fixing up const correctness along the way. by Benjamin Kramer · 14 years ago
  56. 11c0b34 Assembly parsing for 4-register sequential variant of VLD2. by Jim Grosbach · 14 years ago
  57. 118b38c Assembly parsing for 2-register sequential variant of VLD2. by Jim Grosbach · 14 years ago
  58. 846bcff Assembly parsing for 4-register variant of VLD1. by Jim Grosbach · 14 years ago
  59. c4360fe Assembly parsing for 3-register variant of VLD1. by Jim Grosbach · 14 years ago
  60. 2f2e3c4 ARM VLD parsing and encoding. by Jim Grosbach · 14 years ago
  61. 79ebc51 Tidy up. Trailing whitespace. by Jim Grosbach · 14 years ago
  62. 3495791 Removed set, but unused variables. by Chad Rosier · 14 years ago
  63. 8b47836 Fix a non-firing assert. Change: by Richard Trieu · 14 years ago
  64. a7ad9f3 Fix undefined shift. Patch by Ahmed Charles. by Eli Friedman · 14 years ago
  65. 44f76ea SETEND is not allowed in an IT block. by Owen Anderson · 14 years ago
  66. a098a89 ARM addrmode5 represents the 'U' bit of the encoding backwards. by Jim Grosbach · 14 years ago
  67. 54a20ed Thumb2 assembly parsing and encoding for LDC/STC. by Jim Grosbach · 14 years ago
  68. 8007320 addrmode2 is gone from these, so no need for the reg0 operand. by Jim Grosbach · 14 years ago
  69. 6a5c150 Fix the check for nested IT instructions in the disassembler. We need to perform the check before adding the Thumb predicate, which pops on entry off the ITBlock queue. by Owen Anderson · 14 years ago
  70. 5dcda64 Adding back support for printing operands symbolically to ARM's new disassembler by Kevin Enderby · 14 years ago
  71. efc761a ARM fix encoding of VMOV.f32 and VMOV.f64 immediates. by Jim Grosbach · 14 years ago
  72. f01e2de ASR #32 is not allowed on Thumb2 USAT and SSAT instructions. by Owen Anderson · 14 years ago
  73. 987a878 Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated. by Owen Anderson · 14 years ago
  74. ffa8428 Revert r140412. This affects more instructions than intended. by Owen Anderson · 14 years ago
  75. 7591d0c Thumb2 register-shifted-register loads cannot target the PC or the SP. by Owen Anderson · 14 years ago
  76. 163be01 tMOVSr is not allowed in an IT block either. by Owen Anderson · 14 years ago
  77. 61e4604 CPS instructions are UNPREDICTABLE inside IT blocks. by Owen Anderson · 14 years ago
  78. f902d92 Thumb2 TBB and TBH instructions are only allowed at the end of IT blocks, not in the middle. by Owen Anderson · 14 years ago
  79. 05541f4 Thumb2 assembly parsing and encoding for TBB/TBH. by Jim Grosbach · 14 years ago
  80. ddfcec9 Handle STRT (and friends) like LDRT (and friends) for decoding purposes. Port over additional encoding tests to decoding tests. by Owen Anderson · 14 years ago
  81. 502cd9d Bitfield mask instructions are unpredictable if the encoded LSB is higher than the encoded MSB. by Owen Anderson · 14 years ago
  82. b925e93 Fix bitfield decoding based on Eli's feedback. by Owen Anderson · 14 years ago
  83. bcfa9a6 Thumb2 pre-indexed loads/stores use the restricted GPR set for Rt. by Owen Anderson · 14 years ago
  84. 3ca958c Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32). by Owen Anderson · 14 years ago
  85. fe82365 Fix disassembly of Thumb2 LDRSH with a #-0 offset. by Owen Anderson · 14 years ago
  86. a0c3b97 Don't attach annotations to MCInst's. Instead, have the disassembler return, and the printer accept, an annotation string which can be passed through if the client cares about annotations. by Owen Anderson · 14 years ago
  87. f1e3844 Nested IT blocks are UNPREDICTABLE. Mark them as such when disassembling them. by Owen Anderson · 14 years ago
  88. a9ebf6f Port more encoding tests to decoding tests, and correct an improper Thumb2 pre-indexed load decoding this uncovered. by Owen Anderson · 14 years ago
  89. 53db43b LDM writeback is not allowed if Rn is in the target register list. by Owen Anderson · 14 years ago
  90. 5bfb0e0 Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands. by Owen Anderson · 14 years ago
  91. 29cfe6c Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches. by Owen Anderson · 14 years ago
  92. a05627e Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH. by Jim Grosbach · 14 years ago
  93. 33d3953 All conditional branches are disallowed in IT blocks, not just CBZ/CBNZ. by Owen Anderson · 14 years ago
  94. 2fefa42 Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block. by Owen Anderson · 14 years ago
  95. 7db8d69 Thumb2 assembly parsing and encoding for LDRD(immediate). by Jim Grosbach · 14 years ago
  96. f174959 Remove the "common" set of instructions shared between ARM and Thumb2 modes. This is no longer needed now that Thumb2 has its own copy of the STC/LDC instructions. by Owen Anderson · 14 years ago
  97. 18d17aa Create Thumb2 versions of STC/LDC, and reenable the relevant tests. by Owen Anderson · 14 years ago
  98. 8067df9 Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler. by James Molloy · 14 years ago
  99. cd5612d Port more assembler tests over to disassembler tests, and fix a minor logic error that exposed. by Owen Anderson · 14 years ago
  100. 4c493e8 Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= handling to llvm-mc. Reviewed by Owen Anderson. by James Molloy · 14 years ago