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gerrit-public.fairphone.software / toolchain / llvm-project / 9c0b86a76dbe024c643bd59eaf7d9c33388d3386 / llvm / lib / Target / ARM / AsmParser / ARMAsmParser.cpp
  1. 9c0b86a Thumb2 assembly parsing and encoding for STR. by Jim Grosbach · 14 years ago
  2. 099c976 Thumb2 assembly parsing and encoding for STMIA. by Jim Grosbach · 14 years ago
  3. d73c645 Thumb2 assembly parsing and encoding for SMMULL. by Jim Grosbach · 14 years ago
  4. 5e6d5cd Kill some dead code. by Jim Grosbach · 14 years ago
  5. 6c45b75 Tidy up a bit. by Jim Grosbach · 14 years ago
  6. f9799d2 Thumb2 assembly parsing and encoding for SMLAL. by Jim Grosbach · 14 years ago
  7. d7791b9 Fix a crasher in Thumb2 MOV-immediate encoding for certain inputs. by Owen Anderson · 14 years ago
  8. 9c8b993 Thumb2 assembly parsing and encoding for MUL. by Jim Grosbach · 14 years ago
  9. 0ecd395 Thumb2 assembly parsing and encoding for MSR/MRS. by Jim Grosbach · 14 years ago
  10. 18b8b17 Thumb2 assembly parsing for MOV in IT block. by Jim Grosbach · 14 years ago
  11. 3ac26b1 ARM fix assembly parser handling of ranges in register lists. by Jim Grosbach · 14 years ago
  12. 75461af Remove unnecessary scope resolution operator. by Jim Grosbach · 14 years ago
  13. e3a6a82 There's only 16 regs legal in a register list. by Jim Grosbach · 14 years ago
  14. 44ae2da Teach the Thumb ASM parser that BKPT is allowed in IT blocks, even though it is always executed unconditionally. by Owen Anderson · 14 years ago
  15. 3337e39 Tidy up a bit. by Jim Grosbach · 14 years ago
  16. b908b7a Thumb2 parsing and encoding for MOV(immediate). by Jim Grosbach · 14 years ago
  17. 29cfe6c Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches. by Owen Anderson · 14 years ago
  18. 62c3395 Thumb2 assembly parsing and encoding for MLA and MLS. by Jim Grosbach · 14 years ago
  19. a05627e Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH. by Jim Grosbach · 14 years ago
  20. 7db8d69 Thumb2 assembly parsing and encoding for LDRD(immediate). by Jim Grosbach · 14 years ago
  21. c086f68 Thumb2 assembly parsing and encoding for LDR pre-indexed w/ writeback. by Jim Grosbach · 14 years ago
  22. 2392c53 Thumb2 assembly parsing and encoding for LDRBT. by Jim Grosbach · 14 years ago
  23. e0ebc1c Thumb2 assembly parsing and encoding for LDR(register). by Jim Grosbach · 14 years ago
  24. 5bfa8ba Thumb2 parsing and encoding for LDR(immediate). by Jim Grosbach · 14 years ago
  25. a31f223 Thumb2 parsing and encoding for LDMIA. by Jim Grosbach · 14 years ago
  26. 39c6e1d Better diagnostic location information for mnemonic suffices. by Jim Grosbach · 14 years ago
  27. 803898f Thumb2 parsing and encoding for CLREX. by Jim Grosbach · 14 years ago
  28. f471ac3 ARM .code directive should always go to the streamer. by Jim Grosbach · 14 years ago
  29. a0d34d3 Thumb2 parsing and encoding of B instruction. by Jim Grosbach · 14 years ago
  30. f6d5d60 ARM 'rscs' mnemonic is carry-setting 'rsc', not 'rs' with a 'cs' condition code. by Jim Grosbach · 14 years ago
  31. 35d240f t2Bcc is allowed to have a predicate without a preceding IT instruction. by Owen Anderson · 14 years ago
  32. 1d3c137 Thumb2 assembly parsing and encoding for ADD(immediate). by Jim Grosbach · 14 years ago
  33. 99bc846 Thumb2 t2Bcc should encode as t2B when condition is 'always'. by Jim Grosbach · 14 years ago
  34. cfa9421 Remove FIXME. Thumb2 MOV instruction will use separate custom tricks. by Jim Grosbach · 14 years ago
  35. c61fc8f tBcc is OK to be predicated in Thumb2 outside of IT blocks (obviously). by Jim Grosbach · 14 years ago
  36. 6d606fb Tweak Thumb1 ADD encoding selection a bit. by Jim Grosbach · 14 years ago
  37. ed16ec4 Thumb2 parsing and encoding for IT blocks. by Jim Grosbach · 14 years ago
  38. 967674d Improve handling of #-0 offsets for many more pre-indexed addressing modes. by Owen Anderson · 14 years ago
  39. f02d98d Add support for parsing #-0 on non-memory-operand immediate values, and add a testcase that necessitates it. by Owen Anderson · 14 years ago
  40. b9d4e37 ARM assembly parsing tweak for pldw. by Jim Grosbach · 14 years ago
  41. 3d1eac8 Thumb2 assembler parsing and encoding of IT instruction. by Jim Grosbach · 14 years ago
  42. 16d33f3 invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure. by Owen Anderson · 14 years ago
  43. 1c171b1 Explicitly disallow predication in Thumb1 assembly. by Jim Grosbach · 14 years ago
  44. 838ed3a Thumb .n mnemonic qualifiers can be ignored for now. by Jim Grosbach · 14 years ago
  45. 4b701af Thumb parsing and encoding for SUB (SP minu immediate). by Jim Grosbach · 14 years ago
  46. 0a0b307 Thumb parsing and encoding support for ADD SP instructions. by Jim Grosbach · 14 years ago
  47. 6ccd79f Add missing explicit writeback operand to tSTMIA_UPD. by Jim Grosbach · 14 years ago
  48. 2bb4035 Move TargetRegistry and TargetSelect from Target to Support where they belong. by Evan Cheng · 14 years ago
  49. 4d6c9d7 Some refactoring so TargetRegistry.h no longer has to include any files from MC. by Evan Cheng · 14 years ago
  50. d80d169 Thumb parsing and encoding for STM. by Jim Grosbach · 14 years ago
  51. 169b2be Factor low reg checking into a helper function. by Jim Grosbach · 14 years ago
  52. 3636be3 Thumb parsing and encoding for SBC. by Jim Grosbach · 14 years ago
  53. c3c32d9 Thumb parsing and encoding for RSB. by Jim Grosbach · 14 years ago
  54. 38c59fc Improve error checking for tPUSH and tPOP register lists. by Jim Grosbach · 14 years ago
  55. 139acd2 Thumb assemmbly parsing diagnostic improvements for LDM. by Jim Grosbach · 14 years ago
  56. 5c932b2 Tighten up ARM reglist validation a bit. by Jim Grosbach · 14 years ago
  57. 2597722 Thumb parsing and encoding support for NOP. by Jim Grosbach · 14 years ago
  58. 37aa348 Thumb assembly parsing and encoding for NEG. by Jim Grosbach · 14 years ago
  59. 459422d Be more lenient on tied operand matching for MUL. by Jim Grosbach · 14 years ago
  60. 8e04849 Thumb assembly parsing and encoding for MUL. by Jim Grosbach · 14 years ago
  61. f86cd37 Thumb assembly parsing and encoding for MOV. by Jim Grosbach · 14 years ago
  62. 5503c3a Thumb assembly parsing and encoding for LSL(immediate). by Jim Grosbach · 14 years ago
  63. 26d3587 Thumb assembly parsing and encoding for LDRH. by Jim Grosbach · 14 years ago
  64. a32c753 Thumb assembly parsing and encoding for LDRB. by Jim Grosbach · 14 years ago
  65. 23983d6 Thumb assembly parsing and encoding for LDR(immediate) form T2. by Jim Grosbach · 14 years ago
  66. 7473329 Use helper function to check for low registers. by Jim Grosbach · 14 years ago
  67. 3fe94e3 Thumb assembly parsing and encoding for LDR(immediate) form T1. by Jim Grosbach · 14 years ago
  68. 90103cc Thumb assembly parsing and encoding for LDM instruction. by Jim Grosbach · 14 years ago
  69. 6ddb568 Add missing 'break'. by Jim Grosbach · 14 years ago
  70. cbd4ab1 Thumb assembly parsing and encoding for B. by Jim Grosbach · 14 years ago
  71. d3e8e29 Thumb assembly parsing and encoding for ASR. by Jim Grosbach · 14 years ago
  72. 46dd413 ARM clean up the imm_sr operand class representation. by Jim Grosbach · 14 years ago
  73. e9ab47a Thumb ADD(immediate) parsing support. by Jim Grosbach · 14 years ago
  74. b7fa2c0 Thumb parsing diagnostics for low-reg requirements on ADD and MOV. by Jim Grosbach · 14 years ago
  75. 64610e5 Add missing exit for 'case'. by Jim Grosbach · 14 years ago
  76. 58ffdcc Thumb assembly parsing and encoding for ADD(register) instruction. by Jim Grosbach · 14 years ago
  77. 7283da9 Move some logic into a helper function and expand the commentary. by Jim Grosbach · 14 years ago
  78. 3e941ae ARM thumb assembly parsing for arithmetic flag setting instructions. by Jim Grosbach · 14 years ago
  79. 120a96a MCTargetAsmParser target match predicate support. by Jim Grosbach · 14 years ago
  80. 8cffa28 ARM vector compare to zero instruction assembly parsing support. by Jim Grosbach · 14 years ago
  81. a2b8b60 ARM load shifted register pre-index fix shift value asm parser encoding. by Jim Grosbach · 14 years ago
  82. d886f8c ARM STRH assembly parsing and encoding. by Jim Grosbach · 14 years ago
  83. eb09f49 ARM STRD assembly parsing and encoding. by Jim Grosbach · 14 years ago
  84. d564bf3 ARM STR(immediate) assembly parsing and encoding. by Jim Grosbach · 14 years ago
  85. 27ad83d ARM push of a single register encodes as pre-indexed STR. by Jim Grosbach · 14 years ago
  86. 8ba76c6 ARM pop of a single register encodes as post-indexed LDR. by Jim Grosbach · 14 years ago
  87. cd4dd25 ARM LDRH(immediate) assembly parsing and encoding support. by Jim Grosbach · 14 years ago
  88. 1d9d5e9 ARM LDRD(register) assembly parsing and encoding. by Jim Grosbach · 14 years ago
  89. f7164b2 Fix typo. Not quite sure how that slipped in there. by Jim Grosbach · 14 years ago
  90. 5b96b80 ARM LDRD(immediate) assembly parsing and encoding support. by Jim Grosbach · 14 years ago
  91. 95466ce ARM load/store label parsing. by Jim Grosbach · 14 years ago
  92. 3d0b3a3 ARM load instruction shifted register index operands. by Jim Grosbach · 14 years ago
  93. c320c85 ARM indexed load assembly parsing and encoding. by Jim Grosbach · 14 years ago
  94. a70fbfd5 ARM simplify the postidx_reg operand encoding. by Jim Grosbach · 14 years ago
  95. cd17c12 ARM assembly parsing and encoding for LDR instructions. by Jim Grosbach · 14 years ago
  96. d359571 ARM refactoring assembly parsing of memory address operands. by Jim Grosbach · 14 years ago
  97. 51726e2 ARM SRS instruction parsing, diassembly and encoding support. by Jim Grosbach · 14 years ago
  98. c4dc52c ARM assembly parsing and encoding for RFE instruction. by Jim Grosbach · 14 years ago
  99. dd475c3 PLD and PLI are not predicable in ARM mode. by Jim Grosbach · 14 years ago
  100. a03ab0e ARM assembly parsing and encoding for BLX (immediate). by Jim Grosbach · 14 years ago