Log - a7714a0ff986950eb42bd2417486d58ab4620d78 - toolchain/llvm-project

a7714a0 misched: Target-independent support for load/store clustering. by Andrew Trick · 13 years ago
f1ff84c misched: Infrastructure for weak DAG edges. by Andrew Trick · 13 years ago
c280f41 Silence GCC warning about falling off the end of a non-void function. by Benjamin Kramer · 13 years ago
3ca33ac misched: Heuristics based on the machine model. by Andrew Trick · 13 years ago
4d1fa71 misched: Rename RemainingCount to avoid confusion with remaining resources. by Andrew Trick · 13 years ago
d9d4be0 misched: Added handleMove support for updating all kill flags, not just for allocatable regs. by Andrew Trick · 13 years ago
90f711d misched: ILP scheduler for experimental heuristics. by Andrew Trick · 13 years ago
dd79f0f misched: Use the TargetSchedModel interface wherever possible. by Andrew Trick · 13 years ago
984d98b misched: avoid scheduling an instruction twice. by Andrew Trick · 13 years ago
a2733e9 misched: add a hook for custom DAG postprocessing. by Andrew Trick · 13 years ago
19f49ac Release build: guard dump functions with by Manman Ren · 13 years ago
7a8e100 Reorganize MachineScheduler interfaces and publish them in the header. by Andrew Trick · 13 years ago
742534c Release build: guard dump functions with "ifndef NDEBUG" by Manman Ren · 13 years ago
ae53561 Simplify the computeOperandLatency API. by Andrew Trick · 13 years ago
a538d83 Add a getName function to MachineFunction. Use it in places that previously did getFunction()->getName(). Remove includes of Function.h that are no longer needed. by Craig Topper · 13 years ago
35521e2 Fix a typo (the the => the) by Sylvestre Ledru · 13 years ago
87255e3 I'm introducing a new machine model to simultaneously allow simple by Andrew Trick · 13 years ago
2f26b34 misched: allow NULL InstrItineraries. by Andrew Trick · 13 years ago
8c9e672 misched: avoid scheduling instructions that can't be dispatched. by Andrew Trick · 13 years ago
ce27bb9 misched: count micro-ops toward the issue limit. by Andrew Trick · 13 years ago
b9f84bb Guard private fields that are unused in Release builds with #ifndef NDEBUG. by Benjamin Kramer · 13 years ago
05ff466 Move RegisterClassInfo.h. by Andrew Trick · 13 years ago
88517f6 Move RegisterPressure.h. by Andrew Trick · 13 years ago
4544606 misched: API for minimum vs. expected latency. by Andrew Trick · 13 years ago
d36adec misched: comments from code review. by Andrew Trick · 13 years ago
4e7f6a7 misched: trace formatting by Andrew Trick · 13 years ago
85d8f0c Silence unused variable warnings from when assertions are disabled. by Kaelyn Uhrain · 13 years ago
a306a8a misched: Use the same scheduling heuristics with -misched-topdown/bottomup. by Andrew Trick · 13 years ago
79d3eec misched: Trace regpressure. by Andrew Trick · 13 years ago
a8ad5f7 misched: Give each ReadyQ a unique ID by Andrew Trick · 13 years ago
61f1a27 misched: Added ScoreboardHazardRecognizer. by Andrew Trick · 13 years ago
ca47335 misched: Release bottom roots in reverse order. by Andrew Trick · 13 years ago
dd375dd misched: rename ReadyQ class by Andrew Trick · 13 years ago
f378617 misched: copy comments so compareRPDelta is readable by itself. by Andrew Trick · 13 years ago
6a50baa comments by Andrew Trick · 13 years ago
276a3e8 misched: trace ReadyQ. by Andrew Trick · 13 years ago
2202577 misched: Added 3-level regpressure back-off. by Andrew Trick · 13 years ago
47a1fea comment by Andrew Trick · 13 years ago
463b2f1 misched: fix liveness iterators by Andrew Trick · 13 years ago
c5d7008 misched: Print machineinstrs with -debug-only=misched by Andrew Trick · 13 years ago
419eae2 misched: tracing register pressure heuristics. by Andrew Trick · 13 years ago
7ee9de5 misched: Add register pressure backoff to ConvergingScheduler. by Andrew Trick · 13 years ago
795c112 misched: Release only unscheduled nodes into ReadyQ. by Andrew Trick · 13 years ago
95dafd8 misched: Added ReadyQ container wrapper for Top and Bottom Queues. by Andrew Trick · 13 years ago
4add42f misched: Introducing Top and Bottom register pressure trackers during scheduling. by Andrew Trick · 13 years ago
4d4b546 Fix a naughty header include that breaks "installed" builds. by Andrew Trick · 14 years ago
c3ea005 misched: try (not too hard) to place debug values where they belong by Andrew Trick · 14 years ago
cc45a28 misched: ignore debug values during scheduling by Andrew Trick · 14 years ago
8863992 misched: DAG builder support for tracking register pressure within the current scheduling region. by Andrew Trick · 14 years ago
779b32a misched: Add finalizeScheduler to complete the target interface. by Andrew Trick · 14 years ago
adb03b9 misched: trace LiveIntervals after scheduling. by Andrew Trick · 14 years ago
54f7def misched: obvious iterator update fixes for bottom-up. by Andrew Trick · 14 years ago
de670c0 misched: cleanup main loop by Andrew Trick · 14 years ago
dd98c49 Add an option to the MI scheduler to cut off scheduling after a fixed number of by Lang Hames · 14 years ago
05e7a84 Silence operator precedence warnings. by Benjamin Kramer · 14 years ago
8823dec misched: implemented a framework for top-down or bottom-up scheduling. by Andrew Trick · 14 years ago
72515be misched comments by Andrew Trick · 14 years ago
af1bee7 misched: handle scheduler that insert instructions at empty region boundaries. by Andrew Trick · 14 years ago
edfe2ec misched: handle scheduling region boundaries nicely. by Andrew Trick · 14 years ago
8c207e4 misched interface: rename Begin/End to RegionBegin/RegionEnd since they are not private. by Andrew Trick · 14 years ago
1c0ec45 misched comments by Andrew Trick · 14 years ago
a21daf7 revert 152356: verify misched changes using -misched=shuffle. by Andrew Trick · 14 years ago
4530068 misched: allow the default scheduler to be one chosen by the target. by Andrew Trick · 14 years ago
bc3b4e3 Cache MBB->begin. It's possible the scheduler / bundler may change MBB->begin(). by Evan Cheng · 14 years ago
02a80da misched interface: Expose the MachineScheduler pass. by Andrew Trick · 14 years ago
9a0c583 misched prep: Expose the ScheduleDAGInstrs interface so targets may by Andrew Trick · 14 years ago
a316faa misched prep: rename InsertPos to End. by Andrew Trick · 14 years ago
52226d4 misched preparation: rename core scheduler methods for consistency. by Andrew Trick · 14 years ago
60cf03e misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles. by Andrew Trick · 14 years ago
a5f1956 Added -view-misched=dags options. by Andrew Trick · 14 years ago
3b6eb1e misched: Use the StartBlock/FinishBlock hooks by Andrew Trick · 14 years ago
46cc9a4 Initialize SUnits before DAG building. by Andrew Trick · 14 years ago
d9f2152 MachineScheduler shouldn't use/preserve LiveDebugVariables. by Lang Hames · 14 years ago
77d2051 Disentangle moving a machine instr from updating LiveIntervals. by Lang Hames · 14 years ago
d3f8fe8 RegAlloc superpass: includes phi elimination, coalescing, and scheduling. by Andrew Trick · 14 years ago
c24e09b comment by Andrew Trick · 14 years ago
e57583a misched: bug in debug output. by Andrew Trick · 14 years ago
de9f897 stale comment by Andrew Trick · 14 years ago
ad33d5a Add a "moveInstr" method to LiveIntervals. This can be used to move instructions by Lang Hames · 14 years ago
7ccdc5c misched: Inital interface and implementation for ScheduleTopDownLive and ShuffleInstructions. by Andrew Trick · 14 years ago
e1c034f Renamed MachineScheduler to ScheduleTopDownLive. by Andrew Trick · 14 years ago
59ac4fb misched: Initial code for building an MI level scheduling DAG by Andrew Trick · 14 years ago
1d028a3 misched: Added ScheduleDAGInstrs::IsPostRA by Andrew Trick · 14 years ago
7e120f4 misched: Invoke the DAG builder on each sequence of schedulable instructions. by Andrew Trick · 14 years ago
6344087 Move things around to make the file navigable, even though it will probably be split up later. by Andrew Trick · 14 years ago
e77e84e Added the MachineSchedulerPass skeleton. by Andrew Trick · 14 years ago