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gerrit-public.fairphone.software / toolchain / llvm-project / a9a7bf68ee35ffbe2fd6a8ac06290f24f94e16f9 / llvm / lib / Target / ARM / Disassembler / ARMDisassembler.cpp
  1. f57c197 Reflect the MC/MCDisassembler split on the include/ level. by Benjamin Kramer · 10 years ago
  2. f277c8a [ARM] Add new system registers to ARMv8-M Baseline/Mainline by Bradley Smith · 10 years ago
  3. 65b8538 [ARM] Add ARMv8.2-A FP16 scalar instructions by Oliver Stannard · 10 years ago
  4. 47f2452 # This is a combination of 2 commits. # The first commit's message is: by Reid Kleckner · 10 years ago
  5. 42f6e90 [ARM] Add new system registers to ARMv8-M Baseline/Mainline by Bradley Smith · 10 years ago
  6. 187d33e Revert "[ARM] Add ARMv8.2-A FP16 scalar instructions" by Reid Kleckner · 10 years ago
  7. 2de8c16 [ARM] Add ARMv8.2-A FP16 vector instructions by Oliver Stannard · 10 years ago
  8. 48568cb [ARM] Add ARMv8.2-A FP16 scalar instructions by Oliver Stannard · 10 years ago
  9. 67cf33d Test commit by Vinicius Tinti · 10 years ago
  10. b4398107 [ARM] Allow SP in rGPR, starting from ARMv8 by Artyom Skrobov · 10 years ago
  11. cf29644 [ARM] Handle +t2dsp feature as an ArchExtKind in ARMTargetParser.def by Artyom Skrobov · 10 years ago
  12. f97999d Explicitly clear the MI operand list when getInstruction() is called. Call MI.clear() within MCD::OPC_Decode case and inside of translateInstruction() for the X86 target. Remove now unnecessary MI.clear() from ARMDisassembler. by Cameron Esfahani · 10 years ago
  13. f00654e Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC) by Alexander Kornienko · 10 years ago
  14. 70bc5f1 Fixed/added namespace ending comments using clang-tidy. NFC by Alexander Kornienko · 10 years ago
  15. db0712f Use std::bitset for SubtargetFeatures. by Michael Kuperstein · 10 years ago
  16. e9119e4 MC: Modernize MCOperand API naming. NFC. by Jim Grosbach · 10 years ago
  17. c3434b3 Reverting r237234, "Use std::bitset for SubtargetFeatures" by Michael Kuperstein · 10 years ago
  18. aba4a34 Use std::bitset for SubtargetFeatures by Michael Kuperstein · 10 years ago
  19. 0e0f8d2 [ARM] Add v8.1a "Privileged Access Never" extension by Vladimir Sukharev · 11 years ago
  20. f817c1c Use 'override/final' instead of 'virtual' for overridden methods by Alexander Kornienko · 11 years ago
  21. 29704e7 Revert "Use std::bitset for SubtargetFeatures" by Michael Kuperstein · 11 years ago
  22. 774b441 Use std::bitset for SubtargetFeatures by Michael Kuperstein · 11 years ago
  23. efd7a96 Reverting r229831 due to multiple ARM/PPC/MIPS build-bot failures. by Michael Kuperstein · 11 years ago
  24. ba5b04c Use std::bitset for SubtargetFeatures by Michael Kuperstein · 11 years ago
  25. 3131e85 [ARM] SSAT/USAT with an 'asr #32' shift should result in an undefined encoding rather than unpredictable by Bradley Smith · 11 years ago
  26. cdfa931 Remove unused function. by Asiri Rathnayake · 11 years ago
  27. 30895f9 Add post-decode checking of HVC instruction. by Charlie Turner · 11 years ago
  28. 7fc5b87 Pass an ArrayRef to MCDisassembler::getInstruction. by Rafael Espindola · 11 years ago
  29. 4aa6bea Misc style fixes. NFC. by Rafael Espindola · 11 years ago
  30. f2572c5 [ARM] Remove dead code identified by the Clang static analyzer. by Tilmann Scheller · 11 years ago
  31. 9e89d8c [ARM] Honor FeatureD16 in the assembler and disassembler by Oliver Stannard · 11 years ago
  32. 39a85ab [Thumb2] Improve disassembly of memory hints by Oliver Stannard · 11 years ago
  33. 92c816c Thumb2 M-class MSR instruction support changes by Renato Golin · 11 years ago
  34. ee843ef ARM: implement MRS/MSR (banked reg) system instructions. by Tim Northover · 11 years ago
  35. 137ce60 Allow only disassembling of M-class MSR masks that the assembler knows how to assemble back. by James Molloy · 11 years ago
  36. 84e68b2 [Modules] Fix potential ODR violations by sinking the DEBUG_TYPE by Chandler Carruth · 11 years ago
  37. a1bc0f5 [MC] Require an MCContext when constructing an MCDisassembler. by Lang Hames · 12 years ago
  38. dc9ff75 ARM: rename ARMle/ARMbe with ARMLE/ARMBE, and Thumble/Thumbbe with ThumbLE/ThumbBE by Christian Pirker · 12 years ago
  39. 2a11160 Add ARM big endian Target (armeb, thumbeb) by Christian Pirker · 12 years ago
  40. ca7e3e5 [C++11] Add 'override' keyword to virtual methods that override their base class. by Craig Topper · 12 years ago
  41. e686cec [ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (ARM encodings) by Artyom Skrobov · 12 years ago
  42. c1be9c1 [ARM] NEON instructions were erroneously decoded from certain invalid encodings by Artyom Skrobov · 12 years ago
  43. 08a8660 ARM: provide diagnostics on more writeback LDM/STM instructions by Tim Northover · 12 years ago
  44. 510de64 [ARM] Remove an unused function from the disassembler. by Joey Gouly · 12 years ago
  45. 3308909 [ARMv8] Add support for the v8 cryptography extensions. by Amara Emerson · 12 years ago
  46. c34bf73 This corrects creation of operands for t2PLDW. It also removes the definition of t2PLDWpci, by Mihai Popa · 12 years ago
  47. df68600 [ARMv8] Add support for the NEON instructions vmaxnm/vminnm. by Joey Gouly · 12 years ago
  48. 18ce7e4 Remove an unneeded call to 'UpdateThumbVFPPredicate', spotted by Amaury. by Joey Gouly · 12 years ago
  49. cc4ff9e Add support for MC assembling and disassembling of vsel{ge, gt, eq, vs} instructions. by Joey Gouly · 12 years ago
  50. 8449c0d ARM: check predicate bits for thumb instructions by Amaury de la Vieuville · 12 years ago
  51. 8175bda ARM: rGPR is meant to be unpredictable, not undefined by Amaury de la Vieuville · 12 years ago
  52. 2f0ac8d ARM: fix IT decoding by Amaury de la Vieuville · 12 years ago
  53. 4b6c076 ARM: enable decoding of pc-relative PLD/PLI by Amaury de la Vieuville · 12 years ago
  54. 4d3e3f2 ARM: fix thumb literal loads decoding by Amaury de la Vieuville · 12 years ago
  55. e2bb1d1 ARM: thumb stores cannot use PC as dest register by Amaury de la Vieuville · 12 years ago
  56. bd2b610 ARM: fix B decoding by Amaury de la Vieuville · 12 years ago
  57. 064546c ARM: Enforce decoding rules for VLDn instructions by Amaury de la Vieuville · 12 years ago
  58. 53ff029 ARM: Fix STREX/LDREX reecoding by Amaury de la Vieuville · 12 years ago
  59. 43cb13a ARM: ISB cannot be passed the same options as DMB by Amaury de la Vieuville · 12 years ago
  60. f4ec0c85 ARM: fix VMOVvnf32 decoding when ambiguous with VCVT by Amaury de la Vieuville · 12 years ago
  61. 68bcd02 ARM: enforce SRS decoding constraints by Amaury de la Vieuville · 12 years ago
  62. 631df63 ARM: fix CPS decoding when ambiguous with QADD by Amaury de la Vieuville · 12 years ago
  63. ea7bb57 ARM: fix VCVT decoding by Amaury de la Vieuville · 12 years ago
  64. 4173e29 ARM: add fstmx and fldmx instructions for assembly by Tim Northover · 12 years ago
  65. df1ecbd7 Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros. by Michael J. Spencer · 12 years ago
  66. 534d3a4 Remove the Copied parameter from MemoryObject::readBytes. by Benjamin Kramer · 12 years ago
  67. ad1084d Add MCSymbolizer for symbolic/annotated disassembly. by Ahmed Bougacha · 12 years ago
  68. f41e3f5 VSTn instructions have a number of encoding constraints which are not implemented. I have added these using wrapper methods around the original custom decoder (incidentally - this is a huge poorly written method that should be cleaned up. I have left it as is since the changes would be much to hard to review). by Mihai Popa · 12 years ago
  69. dcf0922 Q registers are encoded in fields of the same length as D registers. As Q registers are half as many, the ARM reference manual mandates the least significant bit to be zeroed out. Failure to do so should result in an undefined instruction. With this change test/MC/Disassembler/ARM/invalid-VQADD-arm.txt is passing (removed XFAIL). by Mihai Popa · 12 years ago
  70. 8bad66e Replace some bit operations with simpler ones. No functionality change. by Benjamin Kramer · 12 years ago
  71. dc1764c5 The purpose of the patch is to fix the syntax of ARM mrc and mrc2 instructions when they are used to write to the APSR. In this case, the destination operand should be APSR_nzcv, and the encoding of the target should be 0b1111 (same as for PC). In pre-UAL syntax, this form used the PC register as a textual target. This is still allowed for backward compatibility. by Mihai Popa · 12 years ago
  72. a83d5e9 ARM: Fix encoding of hint instruction for Thumb. by Quentin Colombet · 12 years ago
  73. 27ff504 ARM: Permit "sp" in ARM variant of STREXD instructions by Tim Northover · 13 years ago
  74. a155ab2 ARM: permit "sp" in ARM variants of MOVW/MOVT instructions by Tim Northover · 13 years ago
  75. 6f03f62 Fix treatment of ARM unallocated hint instructions. by Quentin Colombet · 13 years ago
  76. 772cf46 Fix issue with disassembler decoding CBZ/CBNZ immediates as negatives when the upper bit is set. by Gordon Keiser · 13 years ago
  77. f686be4 Patch by Gordon Keiser! by Joe Abbey · 13 years ago
  78. e3d3230 Remove edis - the enhanced disassembler. Fixes PR14654. by Roman Divacky · 13 years ago
  79. ed0881b Use the new script to sort the includes of every file under lib. by Chandler Carruth · 13 years ago
  80. 136d674 Fixed the arm disassembly of invalid BFI instructions to not build a bad MCInst by Kevin Enderby · 13 years ago
  81. 6fd9624 Fix ARM's b.w instruction for thumb 2 and the encoding T4. The branch target by Kevin Enderby · 13 years ago
  82. b23926d Fix a bug where a 32-bit address with the high bit does not get symbolicated by Kevin Enderby · 13 years ago
  83. 0c97e76 Fix the handling of edge cases in ARM shifted operands. by Tim Northover · 13 years ago
  84. 00e071a Diagnose invalid alignments on duplicating VLDn instructions. by Tim Northover · 13 years ago
  85. fb3cdd8 Check for invalid alignment values when decoding VLDn/VSTn (single ln) instructions. by Tim Northover · 13 years ago
  86. 228e6d4 Fix integer undefined behavior due to signed left shift overflow in LLVM. by Richard Smith · 13 years ago
  87. f6add7e Remove unnecessary include of ARMGenInstrInfo.inc. by Craig Topper · 13 years ago
  88. ecaef49 Switch the fixed-length disassembler to be table-driven. by Jim Grosbach · 13 years ago
  89. 6a43bf7 Fix #13035, a bug around Thumb instruction LDRD/STRD with negative #0 offset index issue. by Jiangning Liu · 13 years ago
  90. 288e1af Fix #13138, a bug around ARM instruction DSB encoding and decoding issue. by Jiangning Liu · 13 years ago
  91. 35521e2 Fix a typo (the the => the) by Sylvestre Ledru · 13 years ago
  92. 1dc44dc Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters) (and do it properly this time! by Richard Barton · 13 years ago
  93. aeed158 Revert r159938 (and r159945) to appease the buildbots. by Chad Rosier · 13 years ago
  94. 5beef2d Oops - correct broken disassembly for VMOV by Richard Barton · 13 years ago
  95. c9e1c94f Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters) by Richard Barton · 13 years ago
  96. f1ef87d Correct decoder for T1 conditional B encoding by Richard Barton · 13 years ago
  97. 70c1aa0 ARMDisassembler.cpp: Fix utf8 char in comments. by NAKAMURA Takumi · 13 years ago
  98. cabbae6 Tweak to the fix in r156212, as with the change in removing the shift the by Kevin Enderby · 13 years ago
  99. 8ce1ada Fix a bug in the ARM disassembler for wide branch conditional instructions by Kevin Enderby · 13 years ago
  100. 9142230 Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bits by Kevin Enderby · 13 years ago